From eecda0233e26678df1f9394ab942c840cc08b5ce Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Mon, 27 Mar 2023 14:21:35 +0200 Subject: drm/bridge: tc358768: hardcode parallel data format cfg to 1 Set parallel data format to 1 [0], as required by Verdin AM62 V1.0, the default is 0 and it will lead to wrong colors on this specific hardware. [0] 1 = R[1:0], G[1:0], B[1:0], R[7:2], G[7:2], B[7:2] Upstream-Status: Inappropriate [other] A configurable solution to solve this was send upstream, however the discussion stalled [1] and it's not clear the next steps. As a short term work-around just hard-code this to what we need. [1] https://lore.kernel.org/all/20230330095941.428122-4-francesco@dolcini.it/ Signed-off-by: Francesco Dolcini --- drivers/gpu/drm/bridge/tc358768.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index f6373c6cdf89..8566a72700bf 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -864,6 +864,10 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) if (mode->flags & DRM_MODE_FLAG_PHSYNC) tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0)); + /* PDataF: Parallel Data Format */ + val = 1; /* FIXME: hardcoded for Verdin AM62 V1.0 */ + tc358768_update_bits(priv, TC358768_CONFCTL, BIT(8) | BIT(9), val << 8); + /* Start DSI Tx */ tc358768_write(priv, TC358768_DSI_START, 0x1); -- cgit v1.2.3