From ef2fffe1540044bd2b454997b54058bd727491f3 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Sat, 11 Sep 2010 19:46:41 -0700 Subject: [ARM/tegra] ODM: Enabled EMC DFS for Elpida LPDDR2. Enabled EMC DFS for Whistler E1112 board with Elpida LPDDR2. Change-Id: Id6a09e1b96120d44af95498d9c6ef8e3e318bb0b Reviewed-on: http://git-master/r/7044 Tested-by: Aleksandr Frid Reviewed-by: Yu-Huan Hsu --- .../odm_kit/query/whistler/nvodm_query.c | 350 +++++++++++++++++++++ 1 file changed, 350 insertions(+) diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c index 810453f8e00e..9e22d67dc84e 100644 --- a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c +++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c @@ -1218,6 +1218,334 @@ static const NvOdmSdramControllerConfigAdv s_NvOdmE1112SamsungEmcConfigTable[] = } }; +static const NvOdmSdramControllerConfigAdv s_NvOdmE1112ElpidaEmcConfigTable[] = +{ + { + 0x20, /* Rev 2.0 */ + 18000, /* SDRAM frquency */ + 900, /* EMC core voltage */ + 46, /* Number of EMC parameters below */ + { + 0x00000002, /* RC */ + 0x00000006, /* RFC */ + 0x00000003, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x00000038, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000003, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x0000004b, /* TREFBW */ + 0x00000003, /* QUSE_EXTRA */ + 0x00000003, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xa06804ae, /* CFG_DIG_DLL */ + 0x007f3810, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000002, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + 0x20, /* Rev 2.0 */ + 27000, /* SDRAM frquency */ + 950, /* EMC core voltage */ + 46, /* Number of EMC parameters below */ + { + 0x00000002, /* RC */ + 0x00000006, /* RFC */ + 0x00000003, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x00000054, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000004, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000071, /* TREFBW */ + 0x00000003, /* QUSE_EXTRA */ + 0x00000003, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xa06804ae, /* CFG_DIG_DLL */ + 0x007f3810, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000003, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + 0x20, /* Rev 2.0 */ + 54000, /* SDRAM frquency */ + 1000, /* EMC core voltage */ + 46, /* Number of EMC parameters below */ + { + 0x00000004, /* RC */ + 0x00000008, /* RFC */ + 0x00000003, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000005, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x000000a8, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000008, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x000000e1, /* TREFBW */ + 0x00000004, /* QUSE_EXTRA */ + 0x00000000, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xa06804ae, /* CFG_DIG_DLL */ + 0x007f3810, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000005, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + 0x20, /* Rev 2.0 */ + 108000, /* SDRAM frquency */ + 1000, /* EMC core voltage */ + 46, /* Number of EMC parameters below */ + { + 0x00000007, /* RC */ + 0x0000000f, /* RFC */ + 0x00000005, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000005, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x0000017f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000010, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x000001c2, /* TREFBW */ + 0x00000004, /* QUSE_EXTRA */ + 0x00000001, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xa06804ae, /* CFG_DIG_DLL */ + 0x007f6010, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x0000000a, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + 0x20, /* Rev 2.0 */ + 150000, /* SDRAM frquency */ + 1000, /* EMC core voltage */ + 46, /* Number of EMC parameters below */ + { + 0x00000009, /* RC */ + 0x00000014, /* RFC */ + 0x00000007, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000005, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x0000021f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000015, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000270, /* TREFBW */ + 0x00000004, /* QUSE_EXTRA */ + 0x00000001, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xa04c04ae, /* CFG_DIG_DLL */ + 0x007fb010, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x0000000e, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + 0x20, /* Rev 2.0 */ + 300000, /* SDRAM frquency */ + 1200, /* EMC core voltage */ + 46, /* Number of EMC parameters below */ + { + 0x00000012, /* RC */ + 0x00000027, /* RFC */ + 0x0000000d, /* RAS */ + 0x00000006, /* RP */ + 0x00000007, /* R2W */ + 0x00000005, /* W2R */ + 0x00000003, /* R2P */ + 0x00000009, /* W2P */ + 0x00000006, /* RD_RCD */ + 0x00000006, /* WR_RCD */ + 0x00000003, /* RRD */ + 0x00000003, /* REXT */ + 0x00000002, /* WDV */ + 0x00000006, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000c, /* RDV */ + 0x0000045f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000004, /* PDEX2WR */ + 0x00000004, /* PDEX2RD */ + 0x00000006, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000e, /* RW2PDEN */ + 0x0000002a, /* TXSR */ + 0x00000003, /* TCKE */ + 0x0000000f, /* TFAW */ + 0x00000007, /* TRPAB */ + 0x00000005, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x000004e0, /* TREFBW */ + 0x00000005, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000282, /* FBIO_CFG5 */ + 0xe03c048b, /* CFG_DIG_DLL */ + 0x007fd010, /* DLL_XFORM_DQS */ + 0x00000000, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x0000001b, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + } +}; + // Wake Events static NvOdmWakeupPadInfo s_NvOdmWakeupPadInfo[] = @@ -1334,6 +1662,20 @@ static NvBool NvOdmIsE1112Samsung(void) return NvOdmIsBoardPresent(s_WhistlerE1112Samsung, NV_ARRAY_SIZE(s_WhistlerE1112Samsung)); } + +static NvBool NvOdmIsE1112Elpida(void) +{ + // A list of Whistler E1112 processor boards with Elpida LPDDR2 + // charcterized by s_NvOdmE1112ElpidaEmcConfigTable (fill in + // ID/SKU/FAB fields, revision fields are ignored) + static const NvOdmBoardInfo s_WhistlerE1112Elpida[] = + { + // ID SKU FAB Rev Minor Rev + { BOARD_ID_WHISTLER_E1112, 0x0A00, 0x00, BOARD_REV_ALL, BOARD_REV_ALL} + }; + return NvOdmIsBoardPresent(s_WhistlerE1112Elpida, + NV_ARRAY_SIZE(s_WhistlerE1112Elpida)); +} #endif static NvBool NvOdmIsCpuRailPreserved(void) @@ -1715,6 +2057,14 @@ NvOdmQuerySdramControllerConfigGet(NvU32 *pEntries, NvU32 *pRevision) *pEntries = NV_ARRAY_SIZE(s_NvOdmE1112SamsungEmcConfigTable); return (const void*)s_NvOdmE1112SamsungEmcConfigTable; } + else if (NvOdmIsE1112Elpida()) + { + if (pRevision) + *pRevision = s_NvOdmE1112ElpidaEmcConfigTable[0].Revision; + if (pEntries) + *pEntries = NV_ARRAY_SIZE(s_NvOdmE1112ElpidaEmcConfigTable); + return (const void*)s_NvOdmE1112ElpidaEmcConfigTable; + } #endif if (pEntries) *pEntries = 0; -- cgit v1.2.3