From 23a71fd616bf77fcc630ea514c469b0dd09cb99c Mon Sep 17 00:00:00 2001 From: Scott Branden Date: Fri, 20 Mar 2015 18:06:22 -0700 Subject: dt-bindings: brcm: rationalize Broadcom documentation naming This patchset attempts to standardize the naming of dt-bindings documents based on the Broadcom vendor prefix of brcm. Although there are no guidelines currently present for how to name the dt-bindings document the "vendor,binding.txt" style is in use by some of the other vendors. Acked-by: Lee Jones Acked-by: Florian Fainelli Acked-by: Gregory Fong Acked-by: Stephen Warren Signed-off-by: Scott Branden Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/bus/bcma.txt | 53 ---------------------- .../devicetree/bindings/bus/brcm,bus-axi.txt | 53 ++++++++++++++++++++++ 2 files changed, 53 insertions(+), 53 deletions(-) delete mode 100644 Documentation/devicetree/bindings/bus/bcma.txt create mode 100644 Documentation/devicetree/bindings/bus/brcm,bus-axi.txt (limited to 'Documentation/devicetree/bindings/bus') diff --git a/Documentation/devicetree/bindings/bus/bcma.txt b/Documentation/devicetree/bindings/bus/bcma.txt deleted file mode 100644 index edd44d802139..000000000000 --- a/Documentation/devicetree/bindings/bus/bcma.txt +++ /dev/null @@ -1,53 +0,0 @@ -Driver for ARM AXI Bus with Broadcom Plugins (bcma) - -Required properties: - -- compatible : brcm,bus-axi - -- reg : iomem address range of chipcommon core - -The cores on the AXI bus are automatically detected by bcma with the -memory ranges they are using and they get registered afterwards. -Automatic detection of the IRQ number is not working on -BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide -them manually through device tree. Use an interrupt-map to specify the -IRQ used by the devices on the bus. The first address is just an index, -because we do not have any special register. - -The top-level axi bus may contain children representing attached cores -(devices). This is needed since some hardware details can't be auto -detected (e.g. IRQ numbers). Also some of the cores may be responsible -for extra things, e.g. ChipCommon providing access to the GPIO chip. - -Example: - - axi@18000000 { - compatible = "brcm,bus-axi"; - reg = <0x18000000 0x1000>; - ranges = <0x00000000 0x18000000 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0x000fffff 0xffff>; - interrupt-map = - /* Ethernet Controller 0 */ - <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 1 */ - <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - - /* PCIe Controller 0 */ - <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - - chipcommon { - reg = <0x00000000 0x1000>; - - gpio-controller; - #gpio-cells = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/bus/brcm,bus-axi.txt b/Documentation/devicetree/bindings/bus/brcm,bus-axi.txt new file mode 100644 index 000000000000..edd44d802139 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/brcm,bus-axi.txt @@ -0,0 +1,53 @@ +Driver for ARM AXI Bus with Broadcom Plugins (bcma) + +Required properties: + +- compatible : brcm,bus-axi + +- reg : iomem address range of chipcommon core + +The cores on the AXI bus are automatically detected by bcma with the +memory ranges they are using and they get registered afterwards. +Automatic detection of the IRQ number is not working on +BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide +them manually through device tree. Use an interrupt-map to specify the +IRQ used by the devices on the bus. The first address is just an index, +because we do not have any special register. + +The top-level axi bus may contain children representing attached cores +(devices). This is needed since some hardware details can't be auto +detected (e.g. IRQ numbers). Also some of the cores may be responsible +for extra things, e.g. ChipCommon providing access to the GPIO chip. + +Example: + + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; + ranges = <0x00000000 0x18000000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = + /* Ethernet Controller 0 */ + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 1 */ + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + + /* PCIe Controller 0 */ + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + + chipcommon { + reg = <0x00000000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; -- cgit v1.2.3