From 78c43a059a718c1ef12f6bb826d2e39a6d22024e Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 26 May 2020 15:59:23 +0300 Subject: dt-bindings: bus: Add Baikal-T1 AXI-bus binding AXI3-bus is the main communication bus connecting all high-speed peripheral IP-cores with RAM controller and with MIPS P5600 cores on Baikal-T1 SoC. This binding describes the DW AMBA 3 AXI Inteconnect and Errors Handler Block synthesized on top of it, which are responsible for the AXI-bus traffic arbitration and errors reporting upstream to CPU. Baikal-T1 AXI-bus DT node is supposed to be compatible with "be,bt1-axi" and "simple-bus" drivers, should have reg property with AXI-bus QOS registers space, syscon phandle reference to the Baikal-T1 System Controller, IRQ line declared, AXI Interconnect reference clock and reset line. Link: https://lore.kernel.org/r/20200526125928.17096-2-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin Reviewed-by: Rob Herring Cc: Alexey Malahov Cc: Paul Burton Cc: Olof Johansson Cc: linux-mips@vger.kernel.org Cc: soc@kernel.org Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/bus/baikal,bt1-axi.yaml | 107 +++++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml (limited to 'Documentation/devicetree/bindings/bus') diff --git a/Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml b/Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml new file mode 100644 index 000000000000..203bc0e5346b --- /dev/null +++ b/Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 AXI-bus + +maintainers: + - Serge Semin + +description: | + AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all + high-speed peripheral IP-cores with RAM controller and with MIPS P5600 + cores. Traffic arbitration is done by means of DW AXI Interconnect (so + called AXI Main Interconnect) routing IO requests from one block to + another: from CPU to SoC peripherals and between some SoC peripherals + (mostly between peripheral devices and RAM, but also between DMA and + some peripherals). In case of any protocol error, device not responding + an IRQ is raised and a faulty situation is reported to the AXI EHB + (Errors Handler Block) embedded on top of the DW AXI Interconnect and + accessible by means of the Baikal-T1 System Controller. + +allOf: + - $ref: /schemas/simple-bus.yaml# + +properties: + compatible: + contains: + const: baikal,bt1-axi + + reg: + minItems: 1 + items: + - description: Synopsys DesignWare AXI Interconnect QoS registers + - description: AXI EHB MMIO system controller registers + + reg-names: + minItems: 1 + items: + - const: qos + - const: ehb + + '#interconnect-cells': + const: 1 + + syscon: + $ref: /schemas/types.yaml#definitions/phandle + description: Phandle to the Baikal-T1 System Controller DT node + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Main Interconnect uplink reference clock + + clock-names: + items: + - const: aclk + + resets: + items: + - description: Main Interconnect reset line + + reset-names: + items: + - const: arst + +unevaluatedProperties: false + +required: + - compatible + - reg + - reg-names + - syscon + - interrupts + - clocks + - clock-names + +examples: + - | + #include + + bus@1f05a000 { + compatible = "baikal,bt1-axi", "simple-bus"; + reg = <0 0x1f05a000 0 0x1000>, + <0 0x1f04d110 0 0x8>; + reg-names = "qos", "ehb"; + #address-cells = <1>; + #size-cells = <1>; + #interconnect-cells = <1>; + + syscon = <&syscon>; + + ranges; + + interrupts = ; + + clocks = <&ccu_axi 0>; + clock-names = "aclk"; + + resets = <&ccu_axi 0>; + reset-names = "arst"; + }; +... -- cgit v1.2.3