From 38279cac36397477d14edf84eff77c8454bc259a Mon Sep 17 00:00:00 2001 From: Chanwoo Choi Date: Fri, 27 Nov 2015 12:55:23 +0900 Subject: PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line This patch adds the detailed correlation between sub-blocks and power line for Exynos3250, Exynos4210 and Exynos4x12. Signed-off-by: Chanwoo Choi Acked-by: MyungJoo Ham Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/devfreq/exynos-bus.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) (limited to 'Documentation/devicetree/bindings/devfreq') diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt index 2fa15dc08fe6..7dbd4abfca33 100644 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -53,6 +53,57 @@ Optional properties only for parent bus device: - exynos,voltage-tolerance: the percentage value for bus voltage tolerance which is used to calculate the max voltage. +Detailed correlation between sub-blocks and power line according to Exynos SoC: +- In case of Exynos3250, there are two power line as following: + VDD_MIF |--- DMC + + VDD_INT |--- LEFTBUS (parent device) + |--- PERIL + |--- MFC + |--- G3D + |--- RIGHTBUS + |--- PERIR + |--- FSYS + |--- LCD0 + |--- PERIR + |--- ISP + |--- CAM + +- In case of Exynos4210, there is one power line as following: + VDD_INT |--- DMC (parent device) + |--- LEFTBUS + |--- PERIL + |--- MFC(L) + |--- G3D + |--- TV + |--- LCD0 + |--- RIGHTBUS + |--- PERIR + |--- MFC(R) + |--- CAM + |--- FSYS + |--- GPS + |--- LCD0 + |--- LCD1 + +- In case of Exynos4x12, there are two power line as following: + VDD_MIF |--- DMC + + VDD_INT |--- LEFTBUS (parent device) + |--- PERIL + |--- MFC(L) + |--- G3D + |--- TV + |--- IMAGE + |--- RIGHTBUS + |--- PERIR + |--- MFC(R) + |--- CAM + |--- FSYS + |--- GPS + |--- LCD0 + |--- ISP + Example1: Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to power line (regulator). The MIF (Memory Interface) AXI bus is used to -- cgit v1.2.3