From 634e936cfe5f2965e2af52cdbf9ccd4da121390e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Thu, 22 Aug 2019 12:44:15 +0200 Subject: dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs. Signed-off-by: Guido Günther --- .../bindings/display/bridge/nwl-dsi.yaml | 155 +++++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml (limited to 'Documentation/devicetree/bindings/display') diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file mode 100644 index 000000000000..24d17a6310dc --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Northwest Logic MIPI-DSI controller on i.MX SoCs + +maintainers: + - Guido Gúnther + - Robert Chiras + +description: | + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for + the SOCs NWL MIPI-DSI host controller. + +properties: + compatible: + const: fsl,imx8mq-nwl-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DSI core clock + - description: RX_ESC clock (used in escape mode) + - description: TX_ESC clock (used in escape mode) + - description: PHY_REF clock + + clock-names: + items: + - const: core + - const: rx_esc + - const: tx_esc + - const: phy_ref + + mux-controls: + description: + mux controller node to use for operating the input mux + + phys: + maxItems: 1 + description: + A phandle to the phy module representing the DPHY + + phy-names: + items: + - const: dphy + + power-domains: + maxItems: 1 + description: + A phandle to the power domain + + resets: + description: + phandles to the reset controller + items: + - description: dsi byte reset line + - description: dsi dpi reset line + - description: dsi esc reset line + - description: dsi pclk reset line + + reset-names: + items: + - const: byte + - const: dpi + - const: esc + - const: pclk + + ports: + type: object + description: + A node containing DSI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/graph.txt. + + port@0: + type: object + description: + Input port node to receive pixel data from the + display controller + + port@1: + type: object + description: + DSI output port node to the panel or the next bridge + in the chain + +patternProperties: + "^panel@[0-9]+$": true + +required: + - clock-names + - clocks + - compatible + - interrupts + - mux-controls + - phy-names + - phys + - ports + - reg + - reset-names + - resets + +examples: + - | + + mipi_dsi: mipi_dsi@30a00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30A00000 0x300>; + clocks = <&clk 163>, <&clk 244>, <&clk 245>, <&clk 164>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref"; + interrupts = <0 34 4>; + mux-controls = <&mux 0>; + power-domains = <&pgc_mipi>; + resets = <&src 0>, <&src 1>, <&src 2>, <&src 3>; + reset-names = "byte", "dpi", "esc", "pclk"; + phys = <&dphy>; + phy-names = "dphy"; + + panel@0 { + compatible = "rocktech,jh057n00900"; + reg = <0>; + port@0 { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; -- cgit v1.2.3 From 8536dc2e273e00fa5b8c68ba7c8da60bcecd1f57 Mon Sep 17 00:00:00 2001 From: Robert Chiras Date: Thu, 29 Aug 2019 11:02:59 +0300 Subject: dt-bindings: display/bridge: nwl-dsi: Document video_pll clock Add documentation for a new clock 'video_pll'. Signed-off-by: Robert Chiras --- Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings/display') diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml index 24d17a6310dc..5e445bdc9187 100644 --- a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml @@ -30,6 +30,7 @@ properties: - description: RX_ESC clock (used in escape mode) - description: TX_ESC clock (used in escape mode) - description: PHY_REF clock + - description: VIDEO_PLL clock clock-names: items: @@ -37,6 +38,7 @@ properties: - const: rx_esc - const: tx_esc - const: phy_ref + - const: video_pll mux-controls: description: -- cgit v1.2.3 From d0ca828d6bbae32d393ac45740ae50c5f150c3cf Mon Sep 17 00:00:00 2001 From: Robert Chiras Date: Thu, 29 Aug 2019 11:03:59 +0300 Subject: dt-bindings: display/bridge: nwl-dsi: Document fsl,clock-drop-level property Add documentation for a new property: 'fsl,clock-drop-level'. Signed-off-by: Robert Chiras --- Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree/bindings/display') diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml index 5e445bdc9187..dbdf6d069a44 100644 --- a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml @@ -93,6 +93,10 @@ properties: DSI output port node to the panel or the next bridge in the chain + fsl,clock-drop-level: + description: + Specifies the level at wich the crtc_clock should be dropped + patternProperties: "^panel@[0-9]+$": true -- cgit v1.2.3