From 9ff532cfc12b143946b31e2b94162b3692eadc61 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Mon, 20 Jan 2020 14:07:10 +0800 Subject: MLK-23252-7 dt-bindings: phy: Add binding for i.MX8mp LDB controller Add devicetree bindings for i.MX8mp LDB controller. The controller supports two four data lane LVDS channels and supports single/dual channel mode. The controller connects with LCDIFv3 on i.MX8mp SoC. Reviewed-by: Sandor Yu Signed-off-by: Liu Ying --- .../devicetree/bindings/display/imx/ldb.txt | 24 +++++++++++++--------- 1 file changed, 14 insertions(+), 10 deletions(-) (limited to 'Documentation/devicetree/bindings/display') diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt index fb7ee4971d8b..4b0e76858929 100644 --- a/Documentation/devicetree/bindings/display/imx/ldb.txt +++ b/Documentation/devicetree/bindings/display/imx/ldb.txt @@ -10,15 +10,15 @@ Required properties: - #address-cells : should be <1> - #size-cells : should be <0> - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb" or - "fsl,imx8qm-ldb" or "fsl,imx8qxp-ldb". + "fsl,imx8qm-ldb" or "fsl,imx8qxp-ldb" or "fsl,imx8mp-ldb". All LDB versions are similar. i.MX6q/dl has an additional multiplexer in the front to select any of the two or four IPU display interfaces as input for each LVDS channel. i.MX8qm LDB supports 10bit RGB input and needs an additional phy. - i.MX8qxp LDB only supports one LVDS encoder channel(either - channel0 or channel1). + i.MX8qxp and i.MX8mp LDB only supports one LVDS encoder + channel(either channel0 or channel1). - gpr : should be <&gpr> on i.MX53 and i.MX6q. The phandle points to the iomuxc-gpr region containing the LVDS control register. @@ -44,6 +44,8 @@ Required properties: The following clocks are expected on i.MX8qxp: "aux_pixel" - auxiliary pixel clock in dual channel mode "aux_bypass" - auxiliary bypass clock in dual channel mode + The following clocks are expected on i.MX8mp: + "ldb" - ldb root clock The needed clock numbers for each are documented in Documentation/devicetree/bindings/clock/imx5-clock.txt, and in Documentation/devicetree/bindings/clock/imx6q-clock.txt, and in @@ -54,9 +56,9 @@ Required properties: Optional properties: - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q, i.MX8qm - and i.MX8qxp + i.MX8qxp and i.MX8mp - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, - not used on i.MX6q, i.MX8qm and i.MX8qxp + not used on i.MX6q, i.MX8qm, i.MX8qxp and i.MX8mp - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should be configured - one input will be distributed on both outputs in dual channel mode @@ -78,13 +80,15 @@ Required properties: On i.MX6, there should be four input ports (port@[0-3]) that correspond to the four LVDS multiplexer inputs. On i.MX8qm, the two channels of LDB connect to one display interface of DPU. - A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm - and i.MX8qxp) must be connected to a panel input port or a bridge input port. + On i.MX8mp, the two channels of LDB connect to LCDIFv3. + A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm, + i.MX8qxp and i.MX8mp) must be connected to a panel input port or a bridge + input port. Optionally, the output port can be left out if display-timings are used instead. - - phys: the phandle for the LVDS PHY device. Valid only on i.MX8qm and - i.MX8qxp. - - phy-names: should be "ldb_phy". Valid only on i.MX8qm and i.MX8qxp. + - phys: the phandle for the LVDS PHY device. Valid only on i.MX8qm, i.MX8qxp + and i.MX8mp. + - phy-names: should be "ldb_phy". Valid only on i.MX8qm, i.MX8qxp and i.MX8mp. Optional properties (required if display-timings are used): - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing -- cgit v1.2.3