From a087a95aa2ce963e64b8f36c267b011ebe8cd842 Mon Sep 17 00:00:00 2001 From: Fancy Fang Date: Fri, 15 Mar 2019 12:09:58 +0800 Subject: MLK-21150-3 drm/bridge: sec-dsim: add a new property 'pref-rate' Add a new property 'pref-rate' support which can be used to assign a different clock frequency for the DPHY PLL reference clock in the dtb file. And if this property does not exist, the default clock frequency for the reference clock will be used. And according to the spec, the DPHY PLL reference clk frequency should be in [6MHz, 300MHz] range. Signed-off-by: Fancy Fang --- Documentation/devicetree/bindings/display/bridge/sec_dsim.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings/display') diff --git a/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt index 9bc5e9dd2539..fd4246136d37 100644 --- a/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt +++ b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt @@ -16,6 +16,9 @@ Required properties: "pll-ref" - DSIM PHY PLL reference clock - assigned-clocks: phandles to clocks that requires initial configuration - assigned-clock-rates: rates of the clocks that requires initial configuration +- pref-clk: Assign DPHY PLL reference clock frequency. If not exists, + DSIM bridge driver will use the default lock frequency + which is 27MHz. - port: input and output port nodes with endpoint definitions as defined in Documentation/devicetree/bindings/graph.txt; the input port should be connected to an encoder or a -- cgit v1.2.3