From 0e81504511b72577a39c9b37860fed333bac8eca Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Tue, 19 Feb 2019 11:36:25 +0800 Subject: dt-bindings: display: imx: ldb: Add i.MXqm LDB compatible string and properties This patch adds device tree binding support for i.MXqm LDB, including compatible string and additional properties. Signed-off-by: Liu Ying --- .../devicetree/bindings/display/imx/ldb.txt | 37 +++++++++++++++------- 1 file changed, 26 insertions(+), 11 deletions(-) (limited to 'Documentation/devicetree/bindings/display') diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt index 38c637fa39dd..51a157a231a7 100644 --- a/Documentation/devicetree/bindings/display/imx/ldb.txt +++ b/Documentation/devicetree/bindings/display/imx/ldb.txt @@ -9,15 +9,20 @@ nodes describing each of the two LVDS encoder channels of the bridge. Required properties: - #address-cells : should be <1> - #size-cells : should be <0> - - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". - Both LDB versions are similar, but i.MX6 has an additional - multiplexer in the front to select any of the four IPU display - interfaces as input for each LVDS channel. + - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb" or + "fsl,imx8qm-ldb". + All LDB versions are similar. + i.MX6q/dl has an additional multiplexer in the front to select + any of the two or four IPU display interfaces as input for each + LVDS channel. + i.MX8qm LDB supports 10bit RGB input and needs an additional + phy. - gpr : should be <&gpr> on i.MX53 and i.MX6q. The phandle points to the iomuxc-gpr region containing the LVDS control register. - clocks, clock-names : phandles to the LDB divider and selector clocks and to - the display interface selector clocks, as described in + the display interface selector clocks or pixel and + bypass clocks as described in Documentation/devicetree/bindings/clock/clock-bindings.txt The following clocks are expected on i.MX53: "di0_pll" - LDB LVDS channel 0 mux @@ -29,14 +34,19 @@ Required properties: On i.MX6q the following additional clocks are needed: "di2_sel" - IPU2 DI0 mux "di3_sel" - IPU2 DI1 mux + The following clocks are expected on i.MX8qm: + "pixel" - pixel clock + "bypass" - bypass clock The needed clock numbers for each are documented in Documentation/devicetree/bindings/clock/imx5-clock.txt, and in - Documentation/devicetree/bindings/clock/imx6q-clock.txt. + Documentation/devicetree/bindings/clock/imx6q-clock.txt, and in + Documentation/devicetree/bindings/clock/imx8qm-lpcg.txt. +- power-domains : phandle pointing to power domain, only required by i.MX8qm. Optional properties: - - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q + - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q and i.MX8qm - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, - not used on i.MX6q + not used on i.MX6q and i.MX8qm - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should be configured - one input will be distributed on both outputs in dual channel mode @@ -57,9 +67,13 @@ Required properties: (lvds-channel@[0,1], respectively). On i.MX6, there should be four input ports (port@[0-3]) that correspond to the four LVDS multiplexer inputs. - A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected - to a panel input port. Optionally, the output port can be left out if - display-timings are used instead. + On i.MX8qm, the two channels of LDB connect to one display interface of DPU. + A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm) + must be connected to a panel input port or a bridge input port. + Optionally, the output port can be left out if display-timings are used + instead. + - phys: the phandle for the LVDS PHY device. Valid only on i.MX8qm. + - phy-names: should be "ldb_phy". Valid only on i.MX8qm. Optional properties (required if display-timings are used): - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing @@ -69,6 +83,7 @@ Optional properties (required if display-timings are used): This describes how the color bits are laid out in the serialized LVDS signal. - fsl,data-width : should be <18> or <24> + Additionally, <30> for i.MX8qm. example: -- cgit v1.2.3 From 15409f90e647e2898b5679a08cd642aa8a7beee0 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Tue, 19 Feb 2019 14:22:17 +0800 Subject: dt-bindings: display: imx: ldb: Add i.MXqxp LDB compatible string and properties This patch adds device tree binding support for i.MXqxp LDB, including compatible string and additional properties. Signed-off-by: Liu Ying --- .../devicetree/bindings/display/imx/ldb.txt | 25 ++++++++++++++-------- 1 file changed, 16 insertions(+), 9 deletions(-) (limited to 'Documentation/devicetree/bindings/display') diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt index 51a157a231a7..f4ffeb4c5008 100644 --- a/Documentation/devicetree/bindings/display/imx/ldb.txt +++ b/Documentation/devicetree/bindings/display/imx/ldb.txt @@ -10,13 +10,15 @@ Required properties: - #address-cells : should be <1> - #size-cells : should be <0> - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb" or - "fsl,imx8qm-ldb". + "fsl,imx8qm-ldb" or "fsl,imx8qxp-ldb". All LDB versions are similar. i.MX6q/dl has an additional multiplexer in the front to select any of the two or four IPU display interfaces as input for each LVDS channel. i.MX8qm LDB supports 10bit RGB input and needs an additional phy. + i.MX8qxp LDB only supports one LVDS encoder channel(either + channel0 or channel1). - gpr : should be <&gpr> on i.MX53 and i.MX6q. The phandle points to the iomuxc-gpr region containing the LVDS control register. @@ -40,16 +42,20 @@ Required properties: The needed clock numbers for each are documented in Documentation/devicetree/bindings/clock/imx5-clock.txt, and in Documentation/devicetree/bindings/clock/imx6q-clock.txt, and in - Documentation/devicetree/bindings/clock/imx8qm-lpcg.txt. -- power-domains : phandle pointing to power domain, only required by i.MX8qm. + Documentation/devicetree/bindings/clock/imx8qm-lpcg.txt, and in + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- power-domains : phandle pointing to power domain, only required by i.MX8qm and + i.MX8qxp. Optional properties: - - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q and i.MX8qm + - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q, i.MX8qm + and i.MX8qxp - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, - not used on i.MX6q and i.MX8qm + not used on i.MX6q, i.MX8qm and i.MX8qxp - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should be configured - one input will be distributed on both outputs in dual channel mode + Currently, i.MX8qxp doesn't support dual channel mode. LVDS Channel ============ @@ -68,12 +74,13 @@ Required properties: On i.MX6, there should be four input ports (port@[0-3]) that correspond to the four LVDS multiplexer inputs. On i.MX8qm, the two channels of LDB connect to one display interface of DPU. - A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm) - must be connected to a panel input port or a bridge input port. + A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm + and i.MX8qxp) must be connected to a panel input port or a bridge input port. Optionally, the output port can be left out if display-timings are used instead. - - phys: the phandle for the LVDS PHY device. Valid only on i.MX8qm. - - phy-names: should be "ldb_phy". Valid only on i.MX8qm. + - phys: the phandle for the LVDS PHY device. Valid only on i.MX8qm and + i.MX8qxp. + - phy-names: should be "ldb_phy". Valid only on i.MX8qm and i.MX8qxp. Optional properties (required if display-timings are used): - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing -- cgit v1.2.3 From 0f332579595db4324fb29ec01c1289c160916bc2 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Fri, 15 Nov 2019 10:20:13 +0800 Subject: dt-bindings: display: imx: ldb: Correct pixel and bypass clock description Not only i.MX8qm LDB requires pixel and bypass clocks, but also i.MX8qxp LDB does. This patch corrects pixel and bypass clock description by explicitly saying that i.MX8qxp LDB requires the clocks. Signed-off-by: Liu Ying --- Documentation/devicetree/bindings/display/imx/ldb.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/display') diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt index f4ffeb4c5008..3a2968315210 100644 --- a/Documentation/devicetree/bindings/display/imx/ldb.txt +++ b/Documentation/devicetree/bindings/display/imx/ldb.txt @@ -36,7 +36,7 @@ Required properties: On i.MX6q the following additional clocks are needed: "di2_sel" - IPU2 DI0 mux "di3_sel" - IPU2 DI1 mux - The following clocks are expected on i.MX8qm: + The following clocks are expected on i.MX8qm and i.MX8qxp: "pixel" - pixel clock "bypass" - bypass clock The needed clock numbers for each are documented in -- cgit v1.2.3 From 92ec3526fc248930e14d3860743264ff2ddfd6d3 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Fri, 15 Nov 2019 10:35:04 +0800 Subject: dt-bindings: display: imx: ldb: Add i.MX8qxp LDB dual channel mode documentation i.MX8qxp LDB dual channel mode uses two LDB channels from two LDB instances, while all other LDB variants in other SoCs use two LDB channels from one LDB instance. This patch adds documentation for the special case of i.MX8qxp LDB dual channel mode. Signed-off-by: Liu Ying --- Documentation/devicetree/bindings/display/imx/ldb.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/display') diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt index 3a2968315210..fb7ee4971d8b 100644 --- a/Documentation/devicetree/bindings/display/imx/ldb.txt +++ b/Documentation/devicetree/bindings/display/imx/ldb.txt @@ -22,6 +22,8 @@ Required properties: - gpr : should be <&gpr> on i.MX53 and i.MX6q. The phandle points to the iomuxc-gpr region containing the LVDS control register. + - fsl,auxldb : phandle to auxiliary LDB which is used in dual channel mode. + Only required by i.MX8qxp. - clocks, clock-names : phandles to the LDB divider and selector clocks and to the display interface selector clocks or pixel and bypass clocks as described in @@ -39,6 +41,9 @@ Required properties: The following clocks are expected on i.MX8qm and i.MX8qxp: "pixel" - pixel clock "bypass" - bypass clock + The following clocks are expected on i.MX8qxp: + "aux_pixel" - auxiliary pixel clock in dual channel mode + "aux_bypass" - auxiliary bypass clock in dual channel mode The needed clock numbers for each are documented in Documentation/devicetree/bindings/clock/imx5-clock.txt, and in Documentation/devicetree/bindings/clock/imx6q-clock.txt, and in @@ -55,7 +60,6 @@ Optional properties: - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should be configured - one input will be distributed on both outputs in dual channel mode - Currently, i.MX8qxp doesn't support dual channel mode. LVDS Channel ============ -- cgit v1.2.3