From 2f9e74892d5c799ef491117aed766dd5aeac857c Mon Sep 17 00:00:00 2001 From: Robin Gong Date: Fri, 31 Mar 2017 15:53:39 +0800 Subject: MLK-14610 DMA: fsl-edma-v3: add fsl-edma-v3 support Add edma-v3 driver on i.mx8qm. Signed-off-by: Robin Gong (cherry picked from commit d0ac0971c2e637ebddc853f12f71d130f5df4f91) --- .../devicetree/bindings/dma/fsl-edma-v3.txt | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/fsl-edma-v3.txt (limited to 'Documentation/devicetree/bindings/dma') diff --git a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt new file mode 100644 index 000000000000..4c574937b729 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt @@ -0,0 +1,64 @@ +* Freescale enhanced Direct Memory Access(eDMA-v3) Controller + + The eDMA-v3 controller is inherited from FSL eDMA, and firstly is intergrated + on Freescale i.MX8QM SOC chip. The eDMA channels have multiplex capability by + programmble memory-mapped registers. Specific DMA request source has fixed channel. + +* eDMA Controller +Required properties: +- compatible : + - "fsl,imx8qm-edma" for eDMA used similar to that on i.MX8QM SoC + - "fsl,imx8qm-adma" for audio eDMA used on i.MX8QM +- reg : Specifies base physical address(s) and size of the eDMA channel registers. + Each eDMA channel has separated register's address and size. +- interrupts : A list of interrupt-specifiers, each channel has one interrupt. +- interrupt-names : Should contain: + "edma-chan12-tx" - the channel12 transmission interrupt +- #dma-cells : Must be <3>. + The 1st cell specifies the channel ID. + The 2nd cell specifies the channel priority. + The 3rd cell specifies the channel type like for transmit or receive: + 0: transmit, 1: receive. + See the SoC's reference manual for all the supported request sources. +- dma-channels : Number of channels supported by the controller + +Examples: +edma0: dma-controller@40018000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <4>; + interrupts = , + , + , + ; + interrupt-names = "edma-chan12-tx", "edma-chan13-tx", + "edma-chan14-tx", "edma-chan15-tx"; + status = "okay"; +}; + +* DMA clients +DMA client drivers that uses the DMA function must use the format described +in the dma.txt file, using a three-cell specifier for each channel: the 1st +specifies the channel number, the 2nd specifies the priority, and the 3rd +specifies the channel type is for transmit or receive: 0: transmit, 1: receive. + +Examples: +lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART1_CLK>; + clock-names = "ipg"; + assigned-clock-names = <&clk IMX8QM_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart1>; + dma-names = "tx","rx"; + dmas = <&edma0 15 0 0>, + <&edma0 14 0 1>; + status = "disabled"; +}; -- cgit v1.2.3