From 961997f3cd16db01aa438fb936978e03e8086210 Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Wed, 14 Jun 2017 10:36:25 -0500 Subject: dt-bindings: fpga: Add bindings document for Xilinx LogiCore PR Decoupler MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core. Signed-off-by: Moritz Fischer Signed-off-by: Michal Simek Cc: Sören Brinkmann Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Acked-by: Rob Herring Signed off-by: Alan Tull Signed-off-by: Greg Kroah-Hartman --- .../bindings/fpga/xilinx-pr-decoupler.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt (limited to 'Documentation/devicetree/bindings/fpga') diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file mode 100644 index 000000000000..8dcfba926bc7 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt @@ -0,0 +1,36 @@ +Xilinx LogiCORE Partial Reconfig Decoupler Softcore + +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more +decouplers / fpga bridges. +The controller can decouple/disable the bridges which prevents signal +changes from passing through the bridge. The controller can also +couple / enable the bridges which allows traffic to pass through the +bridge normally. + +The Driver supports only MMIO handling. A PR region can have multiple +PR Decouplers which can be handled independently or chained via decouple/ +decouple_status signals. + +Required properties: +- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by + "xlnx,pr-decoupler" +- regs : base address and size for decoupler module +- clocks : input clock to IP +- clock-names : should contain "aclk" + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup + 1 if driver should enable bridge at startup + Default is to leave bridge in current state. + +See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings. + +Example: + fpga-bridge@100000450 { + compatible = "xlnx,pr-decoupler-1.00", + "xlnx-pr-decoupler"; + regs = <0x10000045 0x10>; + clocks = <&clkc 15>; + clock-names = "aclk"; + bridge-enable = <0>; + }; -- cgit v1.2.3