From 7dd4eb4742e9c77e0ef9b458b0a48ec71bdead79 Mon Sep 17 00:00:00 2001 From: Franck LENORMAND Date: Wed, 4 Mar 2020 10:58:16 +0100 Subject: MLK-23421: dt-bindings: mailbox: imx-mu: add SECO MU support i.MX8/8X SECO MU is dedicated for communication between kernel and SECO. To use SECO MU more effectivly, add "fsl,imx8-seco-mu" compatible to support fast IPC. Signed-off-by: Peng Fan Signed-off-by: Franck LENORMAND --- Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree/bindings/mailbox') diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt index 9c43357c5924..2dd64b63b10c 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -23,6 +23,8 @@ Required properties: be included together with SoC specific compatible. There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu" compatible to support it. + To communicate with i.MX8 SCU, "fsl,imx8-mu-seco" could be + used for fast IPC - reg : Should contain the registers location and length - interrupts : Interrupt number. The interrupt specifier format depends on the interrupt controller parent. @@ -54,3 +56,10 @@ lsio_mu0: mailbox@5d1b0000 { interrupts = ; #mbox-cells = <2>; }; +sec_mu0: mailbox@31560000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x31560000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_SECO_MU_2>; +}; -- cgit v1.2.3