From a70eb9165e2a0f2867f0eb78f12665893d135ee1 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 10 Jun 2021 10:20:23 +0200 Subject: dt-binding: memory: pl353-smc: Rephrase the binding Reword this document before converting it to yaml. Signed-off-by: Miquel Raynal Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210610082040.2075611-2-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/pl353-smc.txt | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree/bindings/memory-controllers') diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt index d56615fd343a..f0b7fe173668 100644 --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt @@ -1,8 +1,7 @@ Device tree bindings for ARM PL353 static memory controller -PL353 static memory controller supports two kinds of memory -interfaces.i.e NAND and SRAM/NOR interfaces. -The actual devices are instantiated from the child nodes of pl353 smc node. +PL353 Static Memory Controller is a bus where you can connect two kinds +of memory interfaces: NAND and memory mapped interfaces (such as SRAM or NOR). Required properties: - compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell". @@ -13,9 +12,9 @@ Required properties: - address-cells : Must be 2. - size-cells : Must be 1. -Child nodes: - For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are -supported as child nodes. +The child device node represents the controller connected to the SMC +bus. Only one between: NAND controller, NOR controller and SRAM controller +is allowed in a single system. for NAND partition information please refer the below file Documentation/devicetree/bindings/mtd/partition.txt -- cgit v1.2.3 From 386783ea6d9f21374cb11e0e8b8b4bd9770ef485 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 10 Jun 2021 10:20:24 +0200 Subject: dt-binding: memory: pl353-smc: Document the range property The ranges property is missing in the description while actually used in the example. This property is actually needed, so mention it. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210610082040.2075611-3-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings/memory-controllers') diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt index f0b7fe173668..4210acf46a55 100644 --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt @@ -11,6 +11,8 @@ Required properties: - clocks : Clock phandles (see clock bindings for details). - address-cells : Must be 2. - size-cells : Must be 1. +- ranges : Memory bus areas for interacting with the devices. + Encodes CS to memory region association. The child device node represents the controller connected to the SMC bus. Only one between: NAND controller, NOR controller and SRAM controller -- cgit v1.2.3 From f1d19f7400132b45cab4ee60e974150699fe28b5 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 10 Jun 2021 10:20:25 +0200 Subject: dt-binding: memory: pl353-smc: Drop the partitioning section This sentence does not belong to this file as this file describes the bus on which various controllers are wired to. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210610082040.2075611-4-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation/devicetree/bindings/memory-controllers') diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt index 4210acf46a55..233b2fd8525b 100644 --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt @@ -18,8 +18,6 @@ The child device node represents the controller connected to the SMC bus. Only one between: NAND controller, NOR controller and SRAM controller is allowed in a single system. -for NAND partition information please refer the below file -Documentation/devicetree/bindings/mtd/partition.txt Example: smcc: memory-controller@e000e000 -- cgit v1.2.3 From 6c74a55e1d791be9758d9f23b1c5375854949188 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 10 Jun 2021 10:20:26 +0200 Subject: dt-binding: memory: pl353-smc: Describe the child reg property Each chil node should have a reg property, no matter the type of controller (NAND, NOR, SRAM). This should be part of the bindings. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210610082040.2075611-5-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree/bindings/memory-controllers') diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt index 233b2fd8525b..105160c795a1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt @@ -18,6 +18,10 @@ The child device node represents the controller connected to the SMC bus. Only one between: NAND controller, NOR controller and SRAM controller is allowed in a single system. +Required device node properties: + +- reg: Contains the chip-select id, the offset and the length + of the memory region requested by the device. Example: smcc: memory-controller@e000e000 -- cgit v1.2.3 From 540148ce3455f0dc4fac9414ac12337ae0ab7cf2 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 10 Jun 2021 10:20:27 +0200 Subject: dt-binding: memory: pl353-smc: Fix the example syntax and style Enhance the spacing, the comment style, add { }, remove (...). Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210610082040.2075611-6-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/pl353-smc.txt | 48 +++++++++++----------- 1 file changed, 25 insertions(+), 23 deletions(-) (limited to 'Documentation/devicetree/bindings/memory-controllers') diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt index 105160c795a1..46e17f5bc45b 100644 --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt @@ -24,27 +24,29 @@ Required device node properties: of the memory region requested by the device. Example: - smcc: memory-controller@e000e000 - compatible = "arm,pl353-smc-r2p1", "arm,primecell"; - clock-names = "memclk", "apb_pclk"; - clocks = <&clkc 11>, <&clkc 44>; - reg = <0xe000e000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region - 0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region - 0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region - nand_0: flash@e1000000 { - compatible = "arm,pl353-nand-r2p1" - reg = <0 0 0x1000000>; - (...) - }; - nor0: flash@e2000000 { - compatible = "cfi-flash"; - reg = <1 0 0x2000000>; - }; - nor1: flash@e4000000 { - compatible = "cfi-flash"; - reg = <2 0 0x2000000>; - }; + smcc: memory-controller@e000e000 { + compatible = "arm,pl353-smc-r2p1", "arm,primecell"; + clock-names = "memclk", "apb_pclk"; + clocks = <&clkc 11>, <&clkc 44>; + reg = <0xe000e000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ + 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ + 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ + + nand_0: flash@e1000000 { + compatible = "arm,pl353-nand-r2p1"; + reg = <0 0 0x1000000>; + }; + + nor0: flash@e2000000 { + compatible = "cfi-flash"; + reg = <1 0 0x2000000>; + }; + + nor1: flash@e4000000 { + compatible = "cfi-flash"; + reg = <2 0 0x2000000>; + }; }; -- cgit v1.2.3 From 29c6d09f39591eb3ea5e8e64ed42b28b9ae31f99 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 10 Jun 2021 10:20:28 +0200 Subject: dt-binding: memory: pl353-smc: Drop unsupported nodes from the example These nodes are given as examples and are not described nor used anywhere else. There is also no hardware of my knowledge compatible with these yet. If we want to be backward compatible, then we should avoid partially describing nodes and their content while there are no users. Plus, the examples are wrong (the addresses should be updated) so let's drop them before converting this file to yaml (only the NAND node, which will be fixed in the example and described somewhere else is kept). Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210610082040.2075611-7-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/pl353-smc.txt | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'Documentation/devicetree/bindings/memory-controllers') diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt index 46e17f5bc45b..3ff6a4a49302 100644 --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt @@ -39,14 +39,4 @@ Example: compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; }; - - nor0: flash@e2000000 { - compatible = "cfi-flash"; - reg = <1 0 0x2000000>; - }; - - nor1: flash@e4000000 { - compatible = "cfi-flash"; - reg = <2 0 0x2000000>; - }; }; -- cgit v1.2.3 From 9af22e1169dd6b0f498fa8f9bff7c44f721b1b20 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 10 Jun 2021 10:20:29 +0200 Subject: dt-binding: memory: pl353-smc: Fix the NAND controller node in the example To be fully valid, the NAND controller node in the example should be named nand-controller instead of flash, should be at the address @0,0 instead of @e1000000 and should have a couple of: - #address-cells - #size-cells properties. The label is being renamed nfc0 as well which is more usual than nand_0. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210610082040.2075611-8-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/memory-controllers') diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt index 3ff6a4a49302..ecd46856f139 100644 --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt @@ -35,8 +35,10 @@ Example: 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ - nand_0: flash@e1000000 { + nfc0: nand-controller@0,0 { compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; + #address-cells = <1>; + #size-cells = <0>; }; }; -- cgit v1.2.3 From d3d0e1e857110a2f8147b1aa3a045b1fccc1e7c3 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 10 Jun 2021 10:20:30 +0200 Subject: dt-binding: memory: pl353-smc: Convert to yaml Convert this binding file to yaml schema. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210610082040.2075611-10-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/arm,pl353-smc.yaml | 131 +++++++++++++++++++++ .../bindings/memory-controllers/pl353-smc.txt | 44 ------- 2 files changed, 131 insertions(+), 44 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt (limited to 'Documentation/devicetree/bindings/memory-controllers') diff --git a/Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml b/Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml new file mode 100644 index 000000000000..7a63c85ef8c5 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM PL353 Static Memory Controller (SMC) device-tree bindings + +maintainers: + - Miquel Raynal + - Naga Sureshkumar Relli + +description: + The PL353 Static Memory Controller is a bus where you can connect two kinds + of memory interfaces, which are NAND and memory mapped interfaces (such as + SRAM or NOR). + +# We need a select here so we don't match all nodes with 'arm,primecell' +select: + properties: + compatible: + contains: + const: arm,pl353-smc-r2p1 + required: + - compatible + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + items: + - const: arm,pl353-smc-r2p1 + - const: arm,primecell + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + reg: + items: + - description: + Configuration registers for the host and sub-controllers. + The three chip select regions are defined in 'ranges'. + + clocks: + items: + - description: clock for the memory device bus + - description: main clock of the SMC + + clock-names: + items: + - const: memclk + - const: apb_pclk + + ranges: + minItems: 1 + maxItems: 3 + description: | + Memory bus areas for interacting with the devices. Reflects + the memory layout with four integer values following: + 0 + items: + - description: NAND bank 0 + - description: NOR/SRAM bank 0 + - description: NOR/SRAM bank 1 + + interrupts: true + +patternProperties: + "@[0-3],[a-f0-9]+$": + type: object + description: | + The child device node represents the controller connected to the SMC + bus. The controller can be a NAND controller or a pair of any memory + mapped controllers such as NOR and SRAM controllers. + + properties: + compatible: + description: + Compatible of memory controller. + + reg: + items: + - items: + - description: | + Chip-select ID, as in the parent range property. + minimum: 0 + maximum: 2 + - description: | + Offset of the memory region requested by the device. + - description: | + Length of the memory region requested by the device. + + required: + - compatible + - reg + +required: + - compatible + - reg + - clock-names + - clocks + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + smcc: memory-controller@e000e000 { + compatible = "arm,pl353-smc-r2p1", "arm,primecell"; + reg = <0xe000e000 0x0001000>; + clock-names = "memclk", "apb_pclk"; + clocks = <&clkc 11>, <&clkc 44>; + ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ + 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ + 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ + #address-cells = <2>; + #size-cells = <1>; + + nfc0: nand-controller@0,0 { + compatible = "arm,pl353-nand-r2p1"; + reg = <0 0 0x1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt deleted file mode 100644 index ecd46856f139..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt +++ /dev/null @@ -1,44 +0,0 @@ -Device tree bindings for ARM PL353 static memory controller - -PL353 Static Memory Controller is a bus where you can connect two kinds -of memory interfaces: NAND and memory mapped interfaces (such as SRAM or NOR). - -Required properties: -- compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell". -- reg : Controller registers map and length. -- clock-names : List of input clock names - "memclk", "apb_pclk" - (See clock bindings for details). -- clocks : Clock phandles (see clock bindings for details). -- address-cells : Must be 2. -- size-cells : Must be 1. -- ranges : Memory bus areas for interacting with the devices. - Encodes CS to memory region association. - -The child device node represents the controller connected to the SMC -bus. Only one between: NAND controller, NOR controller and SRAM controller -is allowed in a single system. - -Required device node properties: - -- reg: Contains the chip-select id, the offset and the length - of the memory region requested by the device. - -Example: - smcc: memory-controller@e000e000 { - compatible = "arm,pl353-smc-r2p1", "arm,primecell"; - clock-names = "memclk", "apb_pclk"; - clocks = <&clkc 11>, <&clkc 44>; - reg = <0xe000e000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ - 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ - 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ - - nfc0: nand-controller@0,0 { - compatible = "arm,pl353-nand-r2p1"; - reg = <0 0 0x1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -- cgit v1.2.3