From f580fd3f9d78cf0425ab98950796c578d8a82167 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 26 Jun 2017 17:33:12 +0200 Subject: dt-bindings: misc: Add Tegra186 MISC registers bindings The MISC register block found on Tegra186 SoCs contains registers that can be used to identify a given chip and various strapping options. Signed-off-by: Thierry Reding --- .../devicetree/bindings/misc/nvidia,tegra186-misc.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt (limited to 'Documentation/devicetree/bindings/misc') diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt new file mode 100644 index 000000000000..892ba4384abc --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt @@ -0,0 +1,12 @@ +NVIDIA Tegra186 MISC register block + +The MISC register block found on Tegra186 SoCs contains registers that can be +used to identify a given chip and various strapping options. + +Required properties: +- compatible: Must be: + - Tegra186: "nvidia,tegra186-misc" +- reg: Should contain 2 entries: The first entry gives the physical address + and length of the register region which contains revision and debug + features. The second entry specifies the physical address and length + of the register region indicating the strapping options. -- cgit v1.2.3