From 241a373797283531a55c1f514514cacb3a0205b3 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 28 Aug 2020 11:12:54 +0800 Subject: dt-bindings: pci: layerscape-pci: Update the description of SCFG property Update the description of the second entry of 'fsl,pcie-scfg' property, as the LS1043A PCIe controller also has some control registers in SCFG block, while it has 3 controllers. Signed-off-by: Hou Zhiqiang --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/pci') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 4614ce591ae5..56e22df79bf3 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -35,7 +35,7 @@ Required properties: "intr": The interrupt that is asserted for controller interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. + The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software -- cgit v1.2.3