From 105b6717fdded72a2e7a839cfcf77dba05a08aea Mon Sep 17 00:00:00 2001 From: Xiaowei Bao Date: Wed, 6 Nov 2019 18:19:13 +0800 Subject: dt-bindings: pci: layerscape-pci: Add compatible strings for ls1028a Add compatible strings for ls1028a. Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings/pci') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index f36efa73a470..f7f706ffe43f 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -25,6 +25,7 @@ Required properties: EP mode: "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep" + "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep" "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep" - reg: base addresses and lengths of the PCIe controller register blocks. -- cgit v1.2.3 From 6d0d10f1bee40c4288c914c669e6fb96c31bd97f Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Sun, 23 Aug 2020 13:18:28 +0800 Subject: dt-bindings: pci: layerscape-pci: Add a optional property big-endian This property is to indicate the endianness when accessing the PEX_LUT and PF register block, so if these registers are implemented in big-endian, specify this property. Signed-off-by: Hou Zhiqiang --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree/bindings/pci') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index f7f706ffe43f..4614ce591ae5 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -41,6 +41,10 @@ Required properties: of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 { -- cgit v1.2.3 From 241a373797283531a55c1f514514cacb3a0205b3 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 28 Aug 2020 11:12:54 +0800 Subject: dt-bindings: pci: layerscape-pci: Update the description of SCFG property Update the description of the second entry of 'fsl,pcie-scfg' property, as the LS1043A PCIe controller also has some control registers in SCFG block, while it has 3 controllers. Signed-off-by: Hou Zhiqiang --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/pci') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 4614ce591ae5..56e22df79bf3 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -35,7 +35,7 @@ Required properties: "intr": The interrupt that is asserted for controller interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. + The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software -- cgit v1.2.3 From 890f821ac38f7d656b9f7ee0142d395d43d5c4b7 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Fri, 25 Jan 2019 17:25:21 +0800 Subject: PCI: imx: enable imx8qm/qxp pcie support Enable the imx8qm/qxp pcie support. Verified on the imx8qxp mek board. Signed-off-by: Richard Zhu --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation/devicetree/bindings/pci') diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index acea1cd444fd..de00aec17ce8 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -25,6 +25,8 @@ properties: - fsl,imx6qp-pcie - fsl,imx7d-pcie - fsl,imx8mq-pcie + - fsl,imx8qm-pcie + - fsl,imx8qxp-pcie reg: items: @@ -148,6 +150,15 @@ properties: the three PCIe PHY powers. This regulator can be supplied by both 1.8v and 3.3v voltage supplies (optional required). + hsio-cfg: + description: hsio configuration mode when the pcie node is supported. + mode 1: pciea 2 lanes and one sata ahci port. + mode 2: pciea 1 lane, pcieb 1 lane and one sata ahci port. + mode 3: pciea 2 lanes, pcieb 1 lane. + + local-addr: + description: the local address used in hsio module. + required: - compatible - reg -- cgit v1.2.3 From a7f8392d4a1c8ecddb5049bb4f970c4a5424ea0e Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 9 Feb 2021 10:34:49 +0800 Subject: MLK-25283-1 dt-binding: imx6q-pcie: add the l1sub for imx8m pcie Add one clkreq reset to support the L1sub for i.MX8M PCIe. Signed-off-by: Richard Zhu Reviewed-by: Jun Li --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings/pci') diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index de00aec17ce8..4be542d95635 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -159,6 +159,9 @@ properties: local-addr: description: the local address used in hsio module. + reset-names: + description: Must contain the following entries: "clkreq" + required: - compatible - reg -- cgit v1.2.3 From bd2f96226f39ad89057f7cd861992026d59beff3 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 9 Mar 2021 15:13:13 +0800 Subject: MLK-25334-1 dt-bindings: imx6q-pcie: add one property to disable l1ss support or not HW board design may not support the L1.1 ASPM, although the L1.1 ASPM can be supported by the SOC chip. So, export one property to disable L1.1 ASPM supported or not. Signed-off-by: Richard Zhu Reviewed-by: Jun Li (cherry picked from commit 7bd2d56b72d33e223305aa2ef9046c0e38f225e6) --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree/bindings/pci') diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 4be542d95635..8d944d02198f 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -162,6 +162,11 @@ properties: reset-names: description: Must contain the following entries: "clkreq" + l1ss-disabled: + description: Force to disable L1SS or not. If present then the L1 + substate would be force disabled although it might be supported by the + chip. + required: - compatible - reg -- cgit v1.2.3