From 05bcf727b39bb5a80eacfb0c1db297cf5c2d92ed Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 12 Feb 2020 20:37:59 +0800 Subject: MLK-23303-4 dt-bindings: phy: add imx pcie phy driver support Add one standalone PCIe PHY for iMX8MP PCIe. Signed-off-by: Richard Zhu Reviewed-by: Fugang Duan --- .../devicetree/bindings/phy/fsl,imx-pcie-phy.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt (limited to 'Documentation/devicetree/bindings/phy') diff --git a/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt new file mode 100644 index 000000000000..627b508ecadc --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt @@ -0,0 +1,22 @@ +* Freescale i.MX PCIE PHY binding + +Required properties: +- compatible: Should be "fsl,imx-pcie-phy" +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) +- reg: The base address and length of the registers +- clocks: Phandles to the clocks for each clock listed in clock-names +- clock-names: Must contain "phy" +- power-domains: Phandle to the power domain that the device is part of + +Example: + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mp-pcie-phy"; + reg = <0x0 0x32f00000 0x0 0x10000>; + clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + power-domains = <&pcie_pd>; + status = "disabled"; + }; -- cgit v1.2.3