From 3c97abb58120e5308ece03ca04fda02804b9d20e Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Wed, 18 Mar 2020 11:01:09 +0800 Subject: MLK-23616-1 dt-bindings: imx8mp-lvds-phy: Add APB clock relevant properties The phy registers are accessible after APB clock is enabled. So, add the relevant clock properties in device tree doc. Reviewed-by: Sandor Yu Signed-off-by: Liu Ying --- Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree/bindings/phy') diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml index 17d84c5533f4..2dc5e0038365 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml @@ -29,6 +29,13 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to block control syscon + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + port@0: type: object description: A port node pointing to the PHY instance0's port node @@ -74,6 +81,8 @@ examples: #address-cells = <1>; #size-cells = <0>; gpr = <&mediamix_blk_ctl>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "apb"; ldb_phy1: port@0 { reg = <0>; -- cgit v1.2.3