From 04d112690d2de4dada66952c0d29fc4b8eb82512 Mon Sep 17 00:00:00 2001 From: Chen Feng Date: Fri, 20 Nov 2015 10:10:04 +0800 Subject: reset: hisilicon: document hisi-hi6220 reset controllers bindings Add DT bindings documentation for hi6220 SoC reset controller. Signed-off-by: Chen Feng Signed-off-by: Philipp Zabel Acked-by: Rob Herring --- .../bindings/reset/hisilicon,hi6220-reset.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt (limited to 'Documentation/devicetree/bindings/reset') diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt new file mode 100644 index 000000000000..e0b185a944ba --- /dev/null +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt @@ -0,0 +1,34 @@ +Hisilicon System Reset Controller +====================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +The reset controller registers are part of the system-ctl block on +hi6220 SoC. + +Required properties: +- compatible: may be "hisilicon,hi6220-sysctrl" +- reg: should be register base and length as documented in the + datasheet +- #reset-cells: 1, see below + +Example: +sys_ctrl: sys_ctrl@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0x0 0xf7030000 0x0 0x2000>; + #clock-cells = <1>; + #reset-cells = <1>; +}; + +Specifying reset lines connected to IP modules +============================================== +example: + + uart1: serial@..... { + ... + resets = <&sys_ctrl PERIPH_RSTEN3_UART1>; + ... + }; + +The index could be found in . -- cgit v1.2.3