From f3baa35822fd8583137d5f442ac5be64efc754f9 Mon Sep 17 00:00:00 2001 From: Robert Chiras Date: Thu, 2 Mar 2017 14:01:46 +0200 Subject: MLK-14280: gpc: gpc driver not probed The GPC controller driver is handling two sections: interrupts and PGC (Power Gate Controller). The interrupts are handled in imx_gpcv2_init function, and the PGC is handled in imx_gpcv2_probe function. In kernel 4.9, the driver is probed by it's compatible entry in: OF_DECLARE_2(irqchip, imx_gpcv2, "fsl,imx7d-gpc", imx_gpcv2_init); Because the driver is already probed, imx_gpcv2_probe function is not called, since it is registered with the same compatible name. In order to separate the interrupts from PGC, this patch moves the regulator entrys in DTS to a new node: pgc. And, assign the probe function to this new node. Also, added DeviceTree documentation about the new added node. Since GPC (the block containing the PGC) didn't have any documentation, documented GPC too. Signed-off-by: Robert Chiras --- Documentation/devicetree/bindings/soc/fsl/gpc.txt | 56 +++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/gpc.txt (limited to 'Documentation/devicetree/bindings/soc') diff --git a/Documentation/devicetree/bindings/soc/fsl/gpc.txt b/Documentation/devicetree/bindings/soc/fsl/gpc.txt new file mode 100644 index 000000000000..a7d29282f8e3 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/gpc.txt @@ -0,0 +1,56 @@ +* General Power Controller (GPC) +------------------------------------------- +The General Power Controller (GPC) module controls the following functions: + - Provide low power mode control for A7 and M4 platform + - Provide Power domain management all ARM and SOC power domain + - Provide domain control mechanism based on A7 and M4 CPU domain + - Provide handshake with CCM for clock management in low power mode + - Provide handshake with SRC for power down and power up sequence + - Provide handshake with Analog for Deep Sleep Mode control + +Required properties: + - reg : Offset and length of the register set of the GPC block. + - compatible : Must contain a chip-specific GPC block compatible string + and (if applicable) may contain a chassis-version GPC compatible + string. Chip-specific strings are of the form "fsl,-gpc", + such as: + * "fsl,imx7d-gpc" + * "fsl,imx7s-gpc" + - interrupt-controller : Specifies that this is an interrupt controller + +Example: +The GPC node for imx7d: + gpc: gpc@303a0000 { + compatible = "fsl,imx7d-gpc"; + reg = <0x303a0000 0x1000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>; + }; + +* Power Gating Controller (PGC) +------------------------------------------- +The Power Gating Controller (PGC) is a power management component that controls the +power-down and power-up sequencing of individual subsystems. +The PGC block is found inside GPC, and share the same register. + +Required properties: + - compatible : Must contain a chip-specific PGC block compatible string + and (if applicable) may contain a chassis-version PGC compatible + string. Chip-specific strings are of the form "fsl,-pgc", + such as: + * "fsl,imx7d-pgc" + * "fsl,imx7s-pgc" + - *-supply : Specifies the regulators that can be managed by this PGC. For exampe: + * "mipi-phy-supply = <®_1p0d>;" + +Example: +The PGC node for imx7d: + pgc { + compatible = "fsl,imx7d-pgc"; + mipi-phy-supply = <®_1p0d>; + pcie-phy-supply = <®_1p0d>; + vcc-supply = <®_1p2>; + }; -- cgit v1.2.3