From b1b26e7ed411daade797a9397119aa1ce472f54e Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Fri, 22 Nov 2019 14:11:22 +0800 Subject: usb: dwc3: Add chip-specific compatible string Some Layerscape paltforms (such as LS1088A, LS2088A, etc) require update HW default cache type configuration to fix DWC3 init failure when applying property dma-coherent. Note that the cache type configuration is actually native feature of DWC3, not additional desgin coming from SoC, so add this support here. Signed-off-by: Ran Wang Reviewed-by: Jun Li --- Documentation/devicetree/bindings/usb/dwc3.txt | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/usb') diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index d2d5a8e99db5..45043c4c54ae 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -4,7 +4,15 @@ DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties as described in 'usb/generic.txt' Required properties: - - compatible: must be "snps,dwc3" + - compatible: must be "snps,dwc3" and (if applicable) may contain a + chip-specific compatible string in front of it to allow dwc3 driver be + able to update cache type configuration accordingly, otherwise + Layerscape SoC will encounter USB init failure when adding property + dma-coherent on device tree. + Example: + * "fsl,layerscape-dwc3", "snps,dwc3" + * "snps,dwc3" + - reg : Address and length of the register set for the device - interrupts: Interrupts used by the dwc3 controller. - clock-names: should contain "ref", "bus_early", "suspend" -- cgit v1.2.3