From 5a0a9bf0632e8a8e0bc8efc5d774aaef7812498e Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 20 Jun 2018 09:30:56 +0800 Subject: MLK-18637-2 pinctrl: add devicetree binding doc for i.MX8MM Add devicetree binding doc for i.MX8MM pinctrl driver. Signed-off-by: Anson Huang Reviewed-by: Bai Ping --- .../bindings/pinctrl/fsl,imx8mm-pinctrl.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt new file mode 100644 index 000000000000..380233d3931a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt @@ -0,0 +1,36 @@ +* Freescale i.MX8M Mini IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx8mm-iomuxc" for IOMUXC controller. +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in + pins-imx8mm.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX8M Mini + Reference Manual for detailed CONFIG settings. + +CONFIG bits definition: +PAD_CTL_LVTTL (1 << 8) +PAD_CTL_HYS (1 << 7) +PAD_CTL_PUE (1 << 6) +PAD_CTL_ODE (1 << 5) +PAD_CTL_SRE_SLOW (0 << 3) +PAD_CTL_SRE_MED (1 << 3) +PAD_CTL_SRE_FAST (2 << 3) +PAD_CTL_SRE_MAX (3 << 3) +PAD_CTL_DSE_HIZ (0 << 0) +PAD_CTL_DSE_255 (1 << 0) +PAD_CTL_DSE_105 (2 << 0) +PAD_CTL_DSE_75 (3 << 0) +PAD_CTL_DSE_85 (4 << 0) +PAD_CTL_DSE_65 (5 << 0) +PAD_CTL_DSE_45 (6 << 0) +PAD_CTL_DSE_40 (7 << 0) + +iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mm-iomuxc"; + reg = <0x0 0x30330000 0x0 0x10000>; +}; -- cgit v1.2.3