From 21295ceacff7db926544067c2835d87b52eeefdb Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Tue, 31 Jul 2018 01:11:13 +0200 Subject: dt-bindings: Add vendor prefix for CDTech(H.K.) Electronics Limited This adds a vendor prefix "cdtech" for CDTech(H.K.) Electronics Limited Website: www.cdtech-lcd.com Signed-off-by: Giulio Benetti Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20180730231117.5631-2-giulio.benetti@micronovasrl.com --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 2c3fc512e746..0f5453d1823c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -67,6 +67,7 @@ capella Capella Microsystems, Inc cascoda Cascoda, Ltd. cavium Cavium, Inc. cdns Cadence Design Systems Inc. +cdtech CDTech(H.K.) Electronics Limited ceva Ceva, Inc. chipidea Chipidea, Inc chipone ChipOne -- cgit v1.2.3 From 1a4d3f24efcb2a733cab7a872bb0a0634cfdec5a Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Tue, 31 Jul 2018 01:11:15 +0200 Subject: dt-bindings: Add CDTech S070WV95-CT16 panel bindings Add documentation for S070WV95-CT16 panel Signed-off-by: Giulio Benetti Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20180730231117.5631-4-giulio.benetti@micronovasrl.com --- .../bindings/display/panel/cdtech,s070wv95-ct16.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/cdtech,s070wv95-ct16.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/cdtech,s070wv95-ct16.txt b/Documentation/devicetree/bindings/display/panel/cdtech,s070wv95-ct16.txt new file mode 100644 index 000000000000..505615dfa0df --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/cdtech,s070wv95-ct16.txt @@ -0,0 +1,12 @@ +CDTech(H.K.) Electronics Limited 7" 800x480 color TFT-LCD panel + +Required properties: +- compatible: should be "cdtech,s070wv95-ct16" +- power-supply: as specified in the base binding + +Optional properties: +- backlight: as specified in the base binding +- enable-gpios: as specified in the base binding + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- cgit v1.2.3 From 94889b487bb9c2560226fc7dac08d28561e340b4 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Tue, 31 Jul 2018 01:11:17 +0200 Subject: dt-bindings: Add CDTech S043WQ26H-CT7 panel bindings Add documentation for S043WQ26H-CT7 panel Signed-off-by: Giulio Benetti Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20180730231117.5631-6-giulio.benetti@micronovasrl.com --- .../bindings/display/panel/cdtech,s043wq26h-ct7.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/cdtech,s043wq26h-ct7.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/cdtech,s043wq26h-ct7.txt b/Documentation/devicetree/bindings/display/panel/cdtech,s043wq26h-ct7.txt new file mode 100644 index 000000000000..057f7f3f6dbe --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/cdtech,s043wq26h-ct7.txt @@ -0,0 +1,12 @@ +CDTech(H.K.) Electronics Limited 4.3" 480x272 color TFT-LCD panel + +Required properties: +- compatible: should be "cdtech,s043wq26h-ct7" +- power-supply: as specified in the base binding + +Optional properties: +- backlight: as specified in the base binding +- enable-gpios: as specified in the base binding + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- cgit v1.2.3 From 7ad8b41cd8f5c2842646d01cdd576663caee04a7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 7 Sep 2018 12:19:46 +0800 Subject: drm/panel: simple: Add support for Banana Pi 7" S070WV20-CT16 panel This panel is marketed as Banana Pi 7" LCD display. On the back is a sticker denoting the model name S070WV20-CT16. This is a 7" 800x480 panel connected through a 24-bit RGB interface. However the panel only does 262k colors. Depending on the variant, the PCB attached to the panel module either supports DSI, or DSI + 24-bit RGB. DSI is converted to 24-bit RGB via an onboard ICN6211 MIPI DSI - RGB bridge chip, then fed to the panel itself. Signed-off-by: Chen-Yu Tsai Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20180907041948.19913-5-wens@csie.org --- .../bindings/display/panel/bananapi,s070wv20-ct16.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt b/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt new file mode 100644 index 000000000000..35bc0c839f49 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt @@ -0,0 +1,12 @@ +Banana Pi 7" (S070WV20-CT16) TFT LCD Panel + +Required properties: +- compatible: should be "bananapi,s070wv20-ct16" +- power-supply: see ./panel-common.txt + +Optional properties: +- enable-gpios: see ./simple-panel.txt +- backlight: see ./simple-panel.txt + +This binding is compatible with the simple-panel binding, which is specified +in ./simple-panel.txt. -- cgit v1.2.3 From 6cbe7cd15f953a8bb49cab9b85077e1ee4e0e999 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Mon, 24 Sep 2018 17:26:10 +0200 Subject: drm/panel: simple: Add DLC1010GIG panel Add support for the DLC DLC1010GIG 1280x800 10.1" LVDS panel to the simple-panel driver. Signed-off-by: Marco Felsch Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20180924152610.25939-1-m.felsch@pengutronix.de --- .../devicetree/bindings/display/panel/dlc,dlc1010gig.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/dlc,dlc1010gig.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/dlc,dlc1010gig.txt b/Documentation/devicetree/bindings/display/panel/dlc,dlc1010gig.txt new file mode 100644 index 000000000000..fbf5dcd15661 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/dlc,dlc1010gig.txt @@ -0,0 +1,12 @@ +DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel + +Required properties: +- compatible: should be "dlc,dlc1010gig" +- power-supply: See simple-panel.txt + +Optional properties: +- enable-gpios: See simple-panel.txt +- backlight: See simple-panel.txt + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- cgit v1.2.3 From 17fd7a9d324fd3af613ddd76f0439481acaad23d Mon Sep 17 00:00:00 2001 From: Stefan Mavrodiev Date: Thu, 12 Jul 2018 11:21:53 +0300 Subject: drm/panel: Add support for Olimex LCD-OLinuXino panel This patch adds Olimex Ltd. LCD-OLinuXino bridge panel driver. The panel is used with different LCDs (currently from 480x272 to 1280x800). A small EEPROM chip is used for identification, which holds some factory data and timing requirements. Signed-off-by: Stefan Mavrodiev Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/1531383729-13932-1-git-send-email-stefan@olimex.com --- .../display/panel/olimex,lcd-olinuxino.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino.txt b/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino.txt new file mode 100644 index 000000000000..a89f9c830a85 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino.txt @@ -0,0 +1,42 @@ +Binding for Olimex Ltd. LCD-OLinuXino bridge panel. + +This device can be used as bridge between a host controller and LCD panels. +Currently supported LCDs are: + - LCD-OLinuXino-4.3TS + - LCD-OLinuXino-5 + - LCD-OLinuXino-7 + - LCD-OLinuXino-10 + +The panel itself contains: + - AT24C16C EEPROM holding panel identification and timing requirements + - AR1021 resistive touch screen controller (optional) + - FT5x6 capacitive touch screnn controller (optional) + - GT911/GT928 capacitive touch screen controller (optional) + +The above chips share same I2C bus. The EEPROM is factory preprogrammed with +device information (id, serial, etc.) and timing requirements. + +Touchscreen bingings can be found in these files: + - input/touchscreen/goodix.txt + - input/touchscreen/edt-ft5x06.txt + - input/touchscreen/ar1021.txt + +Required properties: + - compatible: should be "olimex,lcd-olinuxino" + - reg: address of the configuration EEPROM, should be <0x50> + - power-supply: phandle of the regulator that provides the supply voltage + +Optional properties: + - enable-gpios: GPIO pin to enable or disable the panel + - backlight: phandle of the backlight device attacked to the panel + +Example: +&i2c2 { + panel@50 { + compatible = "olimex,lcd-olinuxino"; + reg = <0x50>; + power-supply = <®_vcc5v0>; + enable-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + }; +}; -- cgit v1.2.3 From 9f891dbe391054ec3fe0e5d14f995addd80f7900 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 12 Sep 2018 14:47:37 +0200 Subject: dt-bindings: allow optional phys in Rockchip dw_hdmi binding Some newer Rockchip SoCs use an Innosilicon hdmiphy accessed via general mmio, so allow these to be referenced via the regular phy interfaces and therefore add optional phy-related properties to the binding. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring Link: https://patchwork.freedesktop.org/patch/msgid/20180912124740.20343-4-heiko@sntech.de --- Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt index adc94fc3c9f8..937bfb472e1d 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt @@ -34,6 +34,8 @@ Optional properties - clock-names: May contain "cec" as defined in dw_hdmi.txt. - clock-names: May contain "grf", power for grf io. - clock-names: May contain "vpll", external clock for some hdmi phy. +- phys: from general PHY binding: the phandle for the PHY device. +- phy-names: Should be "hdmi" if phys references an external phy. Example: -- cgit v1.2.3 From 1c53ba8f22a125b770691030b279300ea982d3b1 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 12 Sep 2018 14:47:40 +0200 Subject: drm/rockchip: dw_hdmi: add dw-hdmi support for the rk3328 The rk3328 uses a dw-hdmi controller with an external hdmi phy from Innosilicon which uses the generic phy framework for access. Add the necessary data and the compatible for the rk3328 to the rockchip dw-hdmi driver. changes in v5: - disable CEC_5V option to make CEC actually work (Jonas) changes in v3: - reword as suggested by Rob to show that it's a dw-hdmi + Inno phy Signed-off-by: Heiko Stuebner Tested-by: Robin Murphy Acked-by: Rob Herring Reviewed-by: Zheng Yang Link: https://patchwork.freedesktop.org/patch/msgid/20180912124740.20343-7-heiko@sntech.de --- Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt index 937bfb472e1d..39143424a474 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt @@ -13,6 +13,7 @@ Required properties: - compatible: should be one of the following: "rockchip,rk3288-dw-hdmi" + "rockchip,rk3328-dw-hdmi" "rockchip,rk3399-dw-hdmi" - reg: See dw_hdmi.txt. - reg-io-width: See dw_hdmi.txt. Shall be 4. -- cgit v1.2.3 From 674c9e198c57930d6616007ba853f22df6657f72 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 23 Oct 2018 09:46:29 +0200 Subject: drm/panel: Add DT bindings for Samsung S6D16D0 This adds the device tree bindings for the Samsung S6D16D0 panel. This is a command mode only panel using DSI. Cc: devicetree@vger.kernel.org Cc: Andrzej Hajda Acked-by: Sam Ravnborg Reviewed-by: Rob Herring Signed-off-by: Linus Walleij Link: https://patchwork.freedesktop.org/patch/msgid/20181023074630.29186-1-linus.walleij@linaro.org --- .../bindings/display/panel/samsung,s6d16d0.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,s6d16d0.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6d16d0.txt b/Documentation/devicetree/bindings/display/panel/samsung,s6d16d0.txt new file mode 100644 index 000000000000..b94e366f451b --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/samsung,s6d16d0.txt @@ -0,0 +1,30 @@ +Samsung S6D16D0 4" 864x480 AMOLED panel + +Required properties: + - compatible: should be: + "samsung,s6d16d0", + - reg: the virtual channel number of a DSI peripheral + - vdd1-supply: I/O voltage supply + - reset-gpios: a GPIO spec for the reset pin (active low) + +The device node can contain one 'port' child node with one child +'endpoint' node, according to the bindings defined in +media/video-interfaces.txt. This node should describe panel's video bus. + +Example: +&dsi { + ... + + panel@0 { + compatible = "samsung,s6d16d0"; + reg = <0>; + vdd1-supply = <&foo>; + reset-gpios = <&foo_gpio 0 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; -- cgit v1.2.3 From b1ab1f32015d7ad2a6f94d11400381d82802ab38 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Fri, 5 Oct 2018 17:52:19 -0700 Subject: dt-bindings: Add Truly NT35597 panel driver bindings Add the device tree bindings for Truly NT35597 panel driver. This panel driver supports both single DSI and dual DSI. However, this patch series supports only dual DSI. Changes in v10: - Remove active high in the documentation for mode gpio - Fix commmit text detail about the board and also fix a typo Reviewed-by: Linus Walleij Reviewed-by: Sean Paul Reviewed-by: Rob Herring Signed-off-by: Abhinav Kumar Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/1538787139-28122-2-git-send-email-abhinavk@codeaurora.org --- .../devicetree/bindings/display/truly,nt35597.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/truly,nt35597.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/truly,nt35597.txt b/Documentation/devicetree/bindings/display/truly,nt35597.txt new file mode 100644 index 000000000000..f39c77ee36ea --- /dev/null +++ b/Documentation/devicetree/bindings/display/truly,nt35597.txt @@ -0,0 +1,59 @@ +Truly model NT35597 DSI display driver + +The Truly NT35597 is a generic display driver, currently only configured +for use in the 2K display on the Qualcomm SDM845 MTP board. + +Required properties: +- compatible: should be "truly,nt35597-2K-display" +- vdda-supply: phandle of the regulator that provides the supply voltage + Power IC supply +- vdispp-supply: phandle of the regulator that provides the supply voltage + for positive LCD bias +- vdispn-supply: phandle of the regulator that provides the supply voltage + for negative LCD bias +- reset-gpios: phandle of gpio for reset line + This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names + (active low) +- mode-gpios: phandle of the gpio for choosing the mode of the display + for single DSI or Dual DSI + This should be low for dual DSI and high for single DSI mode +- ports: This device has two video ports driven by two DSIs. Their connections + are modeled using the OF graph bindings specified in + Documentation/devicetree/bindings/graph.txt. + - port@0: DSI input port driven by master DSI + - port@1: DSI input port driven by secondary DSI + +Example: + + dsi@ae94000 { + panel@0 { + compatible = "truly,nt35597-2K-display"; + reg = <0>; + vdda-supply = <&pm8998_l14>; + vdispp-supply = <&lab_regulator>; + vdispn-supply = <&ibb_regulator>; + pinctrl-names = "default", "suspend"; + pinctrl-0 = <&dpu_dsi_active>; + pinctrl-1 = <&dpu_dsi_suspend>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + panel1_in: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; + }; + }; -- cgit v1.2.3 From 86619c3859c0ff066e519257442b37f90b1212af Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 24 Oct 2018 11:43:11 -0700 Subject: dt-bindings: new binding for Himax HX8357D display panels MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds a new binding for Himax HX8357D display panels. It includes a compatible string for one display (more can be added in the future). The YX350HV15 panel[1] is found in the Adafruit PiTFT 3.5" Touch Screen for Raspberry Pi. [1] https://learn.adafruit.com/adafruit-pitft-3-dot-5-touch-screen-for-raspberry-pi/downloads This binding is closely modeled after the ili9341 binding, for a similar product from adafruit. The primary difference is that the hx8357d doesn't have a reset line that I can find in the schematics. v2: Document the "reg" property (requested by Rob), fix commit message typo (Noralf) Signed-off-by: Eric Anholt Link: https://patchwork.freedesktop.org/patch/msgid/20181024184313.2967-2-eric@anholt.net Reviewed-by: Rob Herring Acked-by: Noralf Trønnes --- .../devicetree/bindings/display/himax,hx8357d.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/himax,hx8357d.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/himax,hx8357d.txt b/Documentation/devicetree/bindings/display/himax,hx8357d.txt new file mode 100644 index 000000000000..e641f664763d --- /dev/null +++ b/Documentation/devicetree/bindings/display/himax,hx8357d.txt @@ -0,0 +1,26 @@ +Himax HX8357D display panels + +This binding is for display panels using a Himax HX8357D controller in SPI +mode, such as the Adafruit 3.5" TFT for Raspberry Pi. + +Required properties: +- compatible: "adafruit,yx350hv15", "himax,hx8357d" +- dc-gpios: D/C pin +- reg: address of the panel on the SPI bus + +The node for this driver must be a child node of a SPI controller, hence +all mandatory properties described in ../spi/spi-bus.txt must be specified. + +Optional properties: +- rotation: panel rotation in degrees counter clockwise (0,90,180,270) +- backlight: phandle of the backlight device attached to the panel + +Example: + display@0{ + compatible = "adafruit,yx350hv15", "himax,hx8357d"; + reg = <0>; + spi-max-frequency = <32000000>; + dc-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + rotation = <90>; + backlight = <&backlight>; + }; -- cgit v1.2.3 From 37cd3c8768edc753d4323c338205ebf430fa43fb Mon Sep 17 00:00:00 2001 From: Javier Arteaga Date: Thu, 25 Oct 2018 16:35:40 +0100 Subject: iio: adc128s052: Add pin-compatible IDs The datasheets for ADC122S021 and ADC124S021 list two more pin-compatible alternatives for each device. Add their IDs as compatible strings. Suggested-by: Jonathan Cameron Signed-off-by: Javier Arteaga Signed-off-by: Dan O'Donovan Reviewed-by: Andy Shevchenko Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/ti-adc128s052.txt | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/ti-adc128s052.txt b/Documentation/devicetree/bindings/iio/adc/ti-adc128s052.txt index daa2b2c29428..c07ce1a3f5c4 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti-adc128s052.txt +++ b/Documentation/devicetree/bindings/iio/adc/ti-adc128s052.txt @@ -1,7 +1,14 @@ * Texas Instruments' ADC128S052, ADC122S021 and ADC124S021 ADC chip Required properties: - - compatible: Should be "ti,adc128s052", "ti,adc122s021" or "ti,adc124s021" + - compatible: Should be one of: + - "ti,adc128s052" + - "ti,adc122s021" + - "ti,adc122s051" + - "ti,adc122s101" + - "ti,adc124s021" + - "ti,adc124s051" + - "ti,adc124s101" - reg: spi chip select number for the device - vref-supply: The regulator supply for ADC reference voltage -- cgit v1.2.3 From 80fc9c457e99a6f568a56743dcd8ad8851723f5f Mon Sep 17 00:00:00 2001 From: Charles-Antoine Couret Date: Mon, 22 Oct 2018 23:02:43 +0200 Subject: dt-bindings: iio: adc: Add AD7949 device tree bindings in documentation Description how to invoke ad7949 driver from device tree file. Signed-off-by: Charles-Antoine Couret Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/ad7949.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/ad7949.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/ad7949.txt b/Documentation/devicetree/bindings/iio/adc/ad7949.txt new file mode 100644 index 000000000000..c7f5057356b1 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ad7949.txt @@ -0,0 +1,16 @@ +* Analog Devices AD7949/AD7682/AD7689 + +Required properties: + - compatible: Should be one of + * "adi,ad7949" + * "adi,ad7682" + * "adi,ad7689" + - reg: spi chip select number for the device + - vref-supply: The regulator supply for ADC reference voltage + +Example: +adc@0 { + compatible = "adi,ad7949"; + reg = <0>; + vref-supply = <&vdd_supply>; +}; -- cgit v1.2.3 From b45f2869a7aa067e5499ffe0ac1e32496e559638 Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Wed, 31 Oct 2018 14:43:04 +0000 Subject: dt-bindings: gpio: vf610: add optional clocks property On some SoCs(e.g. MX7ULP), GPIO clock is gatable and maybe disabled by default. Users have to make sure it's enabled before being able to access controller registers, otherwise an external abort error may occur. Let's add the optional clocks property to handle this case. For ULP GPIO clock, it includes two separate clocks: one is for GPIO controller Input/Output function clock while another is GPIO port control clock for interrupt function. Cc: Linus Walleij Cc: Mark Rutland Cc: Stefan Agner Cc: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/gpio-vf610.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt index 0ccbae44019c..ae254aadee35 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt @@ -24,6 +24,12 @@ Required properties for GPIO node: 4 = active high level-sensitive. 8 = active low level-sensitive. +Optional properties: +-clocks: Must contain an entry for each entry in clock-names. + See common clock-bindings.txt for details. +-clock-names: A list of clock names. For imx7ulp, it must contain + "gpio", "port". + Note: Each GPIO port should have an alias correctly numbered in "aliases" node. -- cgit v1.2.3 From f517232c5a95408e43b40aa9337e6b742beaa9da Mon Sep 17 00:00:00 2001 From: Aleksandr Aleksandrov Date: Mon, 15 Oct 2018 14:49:49 +0300 Subject: dt-bindings: vendor-prefix: new vendor - Emlid Add vendor Emlid Ltd to vendor-prefixes.txt Acked-by: Rob Herring Signed-off-by: Aleksandr Aleksandrov Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 4b1a2a8fcc16..1b531c730c87 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -113,6 +113,7 @@ edt Emerging Display Technologies eeti eGalax_eMPIA Technology Inc elan Elan Microelectronic Corp. embest Shenzhen Embest Technology Co., Ltd. +emlid Emlid, Ltd. emmicro EM Microelectronic emtrion emtrion GmbH endless Endless Mobile, Inc. -- cgit v1.2.3 From a53e71cedf184054cec1097665faf0e9f8e5b090 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 15 Sep 2017 09:34:23 +0200 Subject: dt-bindings: add compatibles for rk3066/rk3188 power controllers Add the compatible values for the power-domain controllers found on rk3066 and rk3188. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/soc/rockchip/power_domain.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt index 5d49d0a2ff29..8304eceb62e4 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt +++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt @@ -7,7 +7,9 @@ Required properties for power domain controller: - compatible: Should be one of the following. "rockchip,px30-power-controller" - for PX30 SoCs. "rockchip,rk3036-power-controller" - for RK3036 SoCs. + "rockchip,rk3066-power-controller" - for RK3066 SoCs. "rockchip,rk3128-power-controller" - for RK3128 SoCs. + "rockchip,rk3188-power-controller" - for RK3188 SoCs. "rockchip,rk3228-power-controller" - for RK3228 SoCs. "rockchip,rk3288-power-controller" - for RK3288 SoCs. "rockchip,rk3328-power-controller" - for RK3328 SoCs. @@ -23,7 +25,9 @@ Required properties for power domain sub nodes: - reg: index of the power domain, should use macros in: "include/dt-bindings/power/px30-power.h" - for PX30 type power domain. "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain. + "include/dt-bindings/power/rk3066-power.h" - for RK3066 type power domain. "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain. + "include/dt-bindings/power/rk3188-power.h" - for RK3188 type power domain. "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain. "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain. "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain. -- cgit v1.2.3 From 186172f465c29ee6b617af961723a3ce5029a9c8 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 3 Nov 2018 20:32:36 +0800 Subject: dt-binding: dwmac-sun8i: add H6 compatible string (w/ A64 fallback) The Allwinner H6 SoC features a Ethernet MAC that is similar to the one in A64. Add a compatible string for it with A64 fallback compatible string, in this case the A64 driver can be used. The "internal" PHY is not internal from the perspective of the H6 main die, instead it's on the co-packaged AC200 chip, and connected to the main die with RMII at the in-package Port A PIO bank. So from the SoC driver side it needs no special treatment. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 5bb3a18cc38d..54c66d0611cb 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -10,6 +10,7 @@ Required properties: "allwinner,sun8i-r40-gmac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" + "allwinner,sun50i-h6-emac", "allwinner-sun50i-a64-emac" - reg: address and length of the register for the device. - interrupts: interrupt for the device - interrupt-names: must be "macirq" -- cgit v1.2.3 From c445335a7696594378422df53792856f1d551246 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 4 Nov 2018 19:26:38 +0100 Subject: dt-bindings: bus: add H6 DE3 bus binding The Allwinner H6 DE3 bus is similar to the A64 DE2 one. Add its compatible string with the A64 string as fallback to the binding. Some description of the binding is modified to make it more generic. Reviewed-by: Rob Herring Signed-off-by: Icenowy Zheng [Fixed compatible name] Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-2-jernej.skrabec@siol.net --- Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt index 87dfb33fb3be..b9d533717dff 100644 --- a/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt +++ b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt @@ -1,11 +1,14 @@ -Device tree bindings for Allwinner A64 DE2 bus +Device tree bindings for Allwinner DE2/3 bus The Allwinner A64 DE2 is on a special bus, which needs a SRAM region (SRAM C) -to be claimed for enabling the access. +to be claimed for enabling the access. The DE3 on Allwinner H6 is at the same +situation, and the binding also applies. Required properties: - - compatible: Should contain "allwinner,sun50i-a64-de2" + - compatible: Should be one of: + - "allwinner,sun50i-a64-de2" + - "allwinner,sun50i-h6-de3", "allwinner,sun50i-a64-de2" - reg: A resource specifier for the register space - #address-cells: Must be set to 1 - #size-cells: Must be set to 1 -- cgit v1.2.3 From b9f9e9b8e42cae6de92617a6c45740e4e6eb6f7f Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 4 Nov 2018 19:26:42 +0100 Subject: dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description This commit adds necessary description and dt includes for H6 DE3 clock. It is very similar to others, but memory region has some additional registers not found in DE2. Reviewed-by: Rob Herring Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt index e94582e8b8a9..41a52c2acffd 100644 --- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt +++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt @@ -1,5 +1,5 @@ -Allwinner Display Engine 2.0 Clock Control Binding --------------------------------------------------- +Allwinner Display Engine 2.0/3.0 Clock Control Binding +------------------------------------------------------ Required properties : - compatible: must contain one of the following compatibles: @@ -8,6 +8,7 @@ Required properties : - "allwinner,sun8i-v3s-de2-clk" - "allwinner,sun50i-a64-de2-clk" - "allwinner,sun50i-h5-de2-clk" + - "allwinner,sun50i-h6-de3-clk" - reg: Must contain the registers base address and length - clocks: phandle to the clocks feeding the display engine subsystem. -- cgit v1.2.3 From fb3ef54246220ddd0ae3fc26e4c4c44a0001fbd3 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 4 Nov 2018 19:26:44 +0100 Subject: dt-bindings: display: sun4i-drm: Add H6 display engine compatibles This commit adds compatibles used in H6 display pipeline, namely for display engine, mixer and TV TCON. H6 display engine is somewhat similar to R40, just less TCONs and mixer support more features. Reviewed-by: Rob Herring Reviewed-by: Chen-Yu Tsai Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-8-jernej.skrabec@siol.net --- Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index 7854fff4fc16..62c83b351344 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -158,6 +158,7 @@ Required properties: * allwinner,sun9i-a80-tcon-tv * "allwinner,sun50i-a64-tcon-lcd", "allwinner,sun8i-a83t-tcon-lcd" * "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv" + * allwinner,sun50i-h6-tcon-tv, allwinner,sun8i-r40-tcon-tv - reg: base address and size of memory-mapped region - interrupts: interrupt associated to this IP - clocks: phandles to the clocks feeding the TCON. @@ -381,6 +382,7 @@ Required properties: * allwinner,sun8i-v3s-de2-mixer * allwinner,sun50i-a64-de2-mixer-0 * allwinner,sun50i-a64-de2-mixer-1 + * allwinner,sun50i-h6-de3-mixer-0 - reg: base address and size of the memory-mapped region. - clocks: phandles to the clocks feeding the mixer * bus: the mixer interface clock @@ -415,9 +417,10 @@ Required properties: * allwinner,sun8i-v3s-display-engine * allwinner,sun9i-a80-display-engine * allwinner,sun50i-a64-display-engine + * allwinner,sun50i-h6-display-engine - allwinner,pipelines: list of phandle to the display engine - frontends (DE 1.0) or mixers (DE 2.0) available. + frontends (DE 1.0) or mixers (DE 2.0/3.0) available. Example: -- cgit v1.2.3 From 9d0fdd4843329ceee9a4fe0852becf7260c98095 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 4 Nov 2018 19:26:55 +0100 Subject: dt-bindings: display: sunxi: add DT binding for Allwinner H6 DW HDMI The Allwinner H6 SoC uses a v2.12a DesignWare HDMI controller, with dedicated CEC and HDCP clocks added; the PHY connected is a standard DesignWare HDMI PHY. Add binding for it. Reviewed-by: Rob Herring Signed-off-by: Icenowy Zheng [added HDCP clock and reset] Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-19-jernej.skrabec@siol.net --- Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index 62c83b351344..478b288eebd9 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -79,6 +79,7 @@ Required properties: - compatible: value must be one of: * "allwinner,sun8i-a83t-dw-hdmi" * "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi" + * "allwinner,sun50i-h6-dw-hdmi" - reg: base address and size of memory-mapped region - reg-io-width: See dw_hdmi.txt. Shall be 1. - interrupts: HDMI interrupt number @@ -86,9 +87,14 @@ Required properties: * iahb: the HDMI bus clock * isfr: the HDMI register clock * tmds: TMDS clock + * cec: HDMI CEC clock (H6 only) + * hdcp: HDCP clock (H6 only) + * hdcp-bus: HDCP bus clock (H6 only) - clock-names: the clock names mentioned above - - resets: phandle to the reset controller - - reset-names: must be "ctrl" + - resets: + * ctrl: HDMI controller reset + * hdcp: HDCP reset (H6 only) + - reset-names: reset names mentioned above - phys: phandle to the DWC HDMI PHY - phy-names: must be "phy" @@ -109,6 +115,7 @@ Required properties: * allwinner,sun8i-h3-hdmi-phy * allwinner,sun8i-r40-hdmi-phy * allwinner,sun50i-a64-hdmi-phy + * allwinner,sun50i-h6-hdmi-phy - reg: base address and size of memory-mapped region - clocks: phandles to the clocks feeding the HDMI PHY * bus: the HDMI PHY interface clock -- cgit v1.2.3 From bbf81a9c7188531b0c391e916b5931e404e5be54 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 4 Nov 2018 19:27:02 +0100 Subject: dt-bindings: display: sun4i-drm: document H6 TCON TOP Allwinner H6 SoC has a cut down version of TCON TOP. Add binding documentation for it. Reviewed-by: Rob Herring Signed-off-by: Icenowy Zheng [expanded description] Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-26-jernej.skrabec@siol.net --- .../devicetree/bindings/display/sunxi/sun4i-drm.txt | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index 478b288eebd9..f426bdb42f18 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -228,24 +228,26 @@ It allows display pipeline to be configured in very different ways: \ [3] TCON-TV1 [1] - TVE1/RGB Note that both TCON TOP references same physical unit. Both mixers can be -connected to any TCON. +connected to any TCON. Not all TCON TOP variants support all features. Required properties: - compatible: value must be one of: * allwinner,sun8i-r40-tcon-top + * allwinner,sun50i-h6-tcon-top - reg: base address and size of the memory-mapped region. - clocks: phandle to the clocks feeding the TCON TOP * bus: TCON TOP interface clock * tcon-tv0: TCON TV0 clock - * tve0: TVE0 clock - * tcon-tv1: TCON TV1 clock - * tve1: TVE0 clock - * dsi: MIPI DSI clock + * tve0: TVE0 clock (R40 only) + * tcon-tv1: TCON TV1 clock (R40 only) + * tve1: TVE0 clock (R40 only) + * dsi: MIPI DSI clock (R40 only) - clock-names: clock name mentioned above - resets: phandle to the reset line driving the TCON TOP - #clock-cells : must contain 1 - clock-output-names: Names of clocks created for TCON TV0 channel clock, - TCON TV1 channel clock and DSI channel clock, in that order. + TCON TV1 channel clock (R40 only) and DSI channel clock (R40 only), in + that order. - ports: A ports node with endpoint definitions as defined in Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should -- cgit v1.2.3 From f611dfdb8544b5ac4228f4e3cb3b06ce15b9c74b Mon Sep 17 00:00:00 2001 From: Leilk Liu Date: Thu, 1 Nov 2018 14:02:18 +0800 Subject: spi: mediatek: Add bindings for mediatek MT8183 soc platform This patch adds a DT binding documentation for the MT8183 soc. Signed-off-by: Leilk Liu Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt index 236dcb0faf37..7940940b43e6 100644 --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt +++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt @@ -8,6 +8,7 @@ Required properties: - mediatek,mt7622-spi: for mt7622 platforms - mediatek,mt8135-spi: for mt8135 platforms - mediatek,mt8173-spi: for mt8173 platforms + - mediatek,mt8183-spi: for mt8183 platforms - #address-cells: should be 1. -- cgit v1.2.3 From 4642f0bede4f3e0e460ae0e52286df606832b291 Mon Sep 17 00:00:00 2001 From: Keiji Hayashibara Date: Fri, 26 Oct 2018 14:58:44 +0900 Subject: spi: uniphier: fix incorrect property items This commit fixes incorrect property because it was different from the actual. The parameters of '#address-cells' and '#size-cells' were removed, and 'interrupts', 'pinctrl-names' and 'pinctrl-0' were added. Fixes: 4dcd5c2781f3 ("spi: add DT bindings for UniPhier SPI controller") Signed-off-by: Keiji Hayashibara Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-uniphier.txt | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-uniphier.txt b/Documentation/devicetree/bindings/spi/spi-uniphier.txt index 504a4ecfc7b1..b04e66a52de5 100644 --- a/Documentation/devicetree/bindings/spi/spi-uniphier.txt +++ b/Documentation/devicetree/bindings/spi/spi-uniphier.txt @@ -5,18 +5,20 @@ UniPhier SoCs have SCSSI which supports SPI single channel. Required properties: - compatible: should be "socionext,uniphier-scssi" - reg: address and length of the spi master registers - - #address-cells: must be <1>, see spi-bus.txt - - #size-cells: must be <0>, see spi-bus.txt - - clocks: A phandle to the clock for the device. - - resets: A phandle to the reset control for the device. + - interrupts: a single interrupt specifier + - pinctrl-names: should be "default" + - pinctrl-0: pin control state for the default mode + - clocks: a phandle to the clock for the device + - resets: a phandle to the reset control for the device Example: spi0: spi@54006000 { compatible = "socionext,uniphier-scssi"; reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; resets = <&peri_rst 11>; }; -- cgit v1.2.3 From 2a35a643f138a97e3bfee0c599c72e5ca80ebe7c Mon Sep 17 00:00:00 2001 From: Keiji Hayashibara Date: Fri, 26 Oct 2018 14:58:45 +0900 Subject: spi: uniphier: re-add addressing properties In commit 7662d1dc17d4 ("spi: uniphier: fix incorrect property items") addressing properties of #address-cells and #size-cells were removed. Since it is not necessary to remove them, they are back again. Signed-off-by: Keiji Hayashibara Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-uniphier.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-uniphier.txt b/Documentation/devicetree/bindings/spi/spi-uniphier.txt index b04e66a52de5..e1201573a29a 100644 --- a/Documentation/devicetree/bindings/spi/spi-uniphier.txt +++ b/Documentation/devicetree/bindings/spi/spi-uniphier.txt @@ -5,6 +5,8 @@ UniPhier SoCs have SCSSI which supports SPI single channel. Required properties: - compatible: should be "socionext,uniphier-scssi" - reg: address and length of the spi master registers + - #address-cells: must be <1>, see spi-bus.txt + - #size-cells: must be <0>, see spi-bus.txt - interrupts: a single interrupt specifier - pinctrl-names: should be "default" - pinctrl-0: pin control state for the default mode @@ -16,6 +18,8 @@ Example: spi0: spi@54006000 { compatible = "socionext,uniphier-scssi"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; -- cgit v1.2.3 From 326e5c8d4a87512ee329efc1b45029767ec710bb Mon Sep 17 00:00:00 2001 From: Mason Yang Date: Wed, 17 Oct 2018 10:08:12 +0800 Subject: dt-binding: spi: Document Macronix controller bindings Document the bindings used by the Macronix controller. Signed-off-by: Mason Yang Reviewed-by: Boris Brezillon Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-mxic.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-mxic.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-mxic.txt b/Documentation/devicetree/bindings/spi/spi-mxic.txt new file mode 100644 index 000000000000..529f2dab2648 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-mxic.txt @@ -0,0 +1,34 @@ +Macronix SPI controller Device Tree Bindings +-------------------------------------------- + +Required properties: +- compatible: should be "mxicy,mx25f0a-spi" +- #address-cells: should be 1 +- #size-cells: should be 0 +- reg: should contain 2 entries, one for the registers and one for the direct + mapping area +- reg-names: should contain "regs" and "dirmap" +- interrupts: interrupt line connected to the SPI controller +- clock-names: should contain "ps_clk", "send_clk" and "send_dly_clk" +- clocks: should contain 3 entries for the "ps_clk", "send_clk" and + "send_dly_clk" clocks + +Example: + + spi@43c30000 { + compatible = "mxicy,mx25f0a-spi"; + reg = <0x43c30000 0x10000>, <0xa0000000 0x20000000>; + reg-names = "regs", "dirmap"; + clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 18>; + clock-names = "send_clk", "send_dly_clk", "ps_clk"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; -- cgit v1.2.3 From fb6a691a23ca4bcf10bbda603e22021776d51d56 Mon Sep 17 00:00:00 2001 From: Manish Narani Date: Thu, 25 Oct 2018 11:36:57 +0530 Subject: dt: bindings: Document ZynqMP DDRC in Synopsys documentation Add information for ZynqMP DDRC which reports the single bit errors that are corrected and the double bit errors that are detected. Signed-off-by: Manish Narani Signed-off-by: Borislav Petkov Reviewed-by: Rob Herring CC: Mark Rutland CC: amit.kucheria@linaro.org CC: devicetree@vger.kernel.org CC: leoyang.li@nxp.com CC: linux-arm-kernel@lists.infradead.org CC: linux-edac CC: mchehab@kernel.org CC: michal.simek@xilinx.com CC: sudeep.holla@arm.com Link: http://lkml.kernel.org/r/1540447621-22870-3-git-send-email-manish.narani@xilinx.com --- .../bindings/memory-controllers/synopsys.txt | 27 ++++++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt index a43d26d41e04..9d32762c47e1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt +++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt @@ -1,15 +1,32 @@ Binding for Synopsys IntelliDDR Multi Protocol Memory Controller -This controller has an optional ECC support in half-bus width (16-bit) -configuration. The ECC controller corrects one bit error and detects -two bit errors. +The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit +bus width configurations. + +The Zynq DDR ECC controller has an optional ECC support in half-bus width +(16-bit) configuration. + +These both ECC controllers correct single bit ECC errors and detect double bit +ECC errors. Required properties: - - compatible: Should be 'xlnx,zynq-ddrc-a05' - - reg: Base address and size of the controllers memory area + - compatible: One of: + - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller + - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller + - reg: Should contain DDR controller registers location and length. + +Required properties for "xlnx,zynqmp-ddrc-2.40a": + - interrupts: Property with a value describing the interrupt number. Example: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; + + mc: memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0x0 0xfd070000 0x0 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; + }; -- cgit v1.2.3 From 4202dd2cb2d8443980ba70a455726ff7fc69bcd8 Mon Sep 17 00:00:00 2001 From: Frank Rowand Date: Sun, 14 Oct 2018 20:22:19 -0700 Subject: of: Documentation: remove unmaintained todo file The todo.txt file was created by a previous maintainer and has never been updated by the current OPEN FIRMWARE AND FLATTENED DEVICE TREE maintainers. Remove the out of date file. Signed-off-by: Frank Rowand Signed-off-by: Rob Herring --- Documentation/devicetree/todo.txt | 10 ---------- 1 file changed, 10 deletions(-) delete mode 100644 Documentation/devicetree/todo.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/todo.txt b/Documentation/devicetree/todo.txt deleted file mode 100644 index b5139d1de811..000000000000 --- a/Documentation/devicetree/todo.txt +++ /dev/null @@ -1,10 +0,0 @@ -Todo list for devicetree: - -=== General structure === -- Switch from custom lists to (h)list_head for nodes and properties structure - -=== CONFIG_OF_DYNAMIC === -- Switch to RCU for tree updates and get rid of global spinlock -- Document node lifecycle for CONFIG_OF_DYNAMIC -- Always set ->full_name at of_attach_node() time -- pseries: Get rid of open-coded tree modification from arch/powerpc/platforms/pseries/dlpar.c -- cgit v1.2.3 From 3edf4b9f381efdb09299a5f928d4f35609d5f530 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Fri, 19 Oct 2018 09:49:06 +0200 Subject: dt-binding: mtd: physmap: Document the addr-gpios property Add documentation for the addr-gpios. This extension to the physmap binding allow creating flash devices that are paged using GPIOs. Cc: devicetree@vger.kernel.org Signed-off-by: Ricardo Ribalda Delgado Signed-off-by: Boris Brezillon Reviewed-by: Rob Herring Reviewed-by: Linus Walleij Acked-by: Linus Walleij --- Documentation/devicetree/bindings/mtd/mtd-physmap.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt index 232fa12e90ef..7df0dcaccb7d 100644 --- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt +++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt @@ -29,6 +29,8 @@ file systems on embedded devices. - use-advanced-sector-protection: boolean to enable support for the advanced sector protection (Spansion: PPB - Persistent Protection Bits) locking. + - addr-gpios : (optional) List of GPIO descriptors that will be used to + address the MSBs address lines. The order goes from LSB to MSB. For JEDEC compatible devices, the following additional properties are defined: -- cgit v1.2.3 From 505a2fd80b4dcd9e89bcf426ba4314ea339911e8 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 4 Jun 2018 11:36:13 +0200 Subject: arm64: dts: rockchip: add Gru Scarlet devicetrees Gru-Scarlet is a tablet device using ChomeOS, dual-dsi display and Wacom touchscreen with stylus. There exist two variants in the market using different displays that are differentiated via their sku-id. The bootloader on them also determines the correct devicetree to load via the sku-id. So add a common scarlet dtsi and two minimal board devicetrees for the two display variants. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/rockchip.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 0cc71236d639..7ce7382fedd8 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -152,6 +152,40 @@ Rockchip platforms device tree bindings - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", "google,veyron", "rockchip,rk3288"; +- Google Scarlet - with display from Kingdisplay + Required root node properties: + - compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15", + "google,scarlet-rev14-sku7", "google,scarlet-rev14", + "google,scarlet-rev13-sku7", "google,scarlet-rev13", + "google,scarlet-rev12-sku7", "google,scarlet-rev12", + "google,scarlet-rev11-sku7", "google,scarlet-rev11", + "google,scarlet-rev10-sku7", "google,scarlet-rev10", + "google,scarlet-rev9-sku7", "google,scarlet-rev9", + "google,scarlet-rev8-sku7", "google,scarlet-rev8", + "google,scarlet-rev7-sku7", "google,scarlet-rev7", + "google,scarlet-rev6-sku7", "google,scarlet-rev6", + "google,scarlet-rev5-sku7", "google,scarlet-rev5", + "google,scarlet-rev4-sku7", "google,scarlet-rev4", + "google,scarlet-rev3-sku7", "google,scarlet-rev3", + "google,scarlet", "google,gru", "rockchip,rk3399"; + +- Google Scarlet - with display from Innolux + Required root node properties: + - compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", + "google,scarlet-rev14-sku6", "google,scarlet-rev14", + "google,scarlet-rev13-sku6", "google,scarlet-rev13", + "google,scarlet-rev12-sku6", "google,scarlet-rev12", + "google,scarlet-rev11-sku6", "google,scarlet-rev11", + "google,scarlet-rev10-sku6", "google,scarlet-rev10", + "google,scarlet-rev9-sku6", "google,scarlet-rev9", + "google,scarlet-rev8-sku6", "google,scarlet-rev8", + "google,scarlet-rev7-sku6", "google,scarlet-rev7", + "google,scarlet-rev6-sku6", "google,scarlet-rev6", + "google,scarlet-rev5-sku6", "google,scarlet-rev5", + "google,scarlet-rev4-sku6", "google,scarlet-rev4", + "google,scarlet", "google,gru", "rockchip,rk3399"; + + - Google Speedy (Asus C201 Chromebook): Required root node properties: - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", -- cgit v1.2.3 From cf26edd840dc65b122a0f5e22d2d81ad05eccb2d Mon Sep 17 00:00:00 2001 From: Nickhu Date: Thu, 25 Oct 2018 10:24:17 +0800 Subject: nds32: Add document for NDS32 PMU. The document for how to add NDS32 PMU in devicetree. Signed-off-by: Nickhu Reviewed-by: Rob Herring Acked-by: Greentime Hu Signed-off-by: Greentime Hu --- Documentation/devicetree/bindings/perf/nds32v3-pmu.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/nds32v3-pmu.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/perf/nds32v3-pmu.txt b/Documentation/devicetree/bindings/perf/nds32v3-pmu.txt new file mode 100644 index 000000000000..1bd15785b4ae --- /dev/null +++ b/Documentation/devicetree/bindings/perf/nds32v3-pmu.txt @@ -0,0 +1,17 @@ +* NDS32 Performance Monitor Units + +NDS32 core have a PMU for counting cpu and cache events like cache misses. +The NDS32 PMU representation in the device tree should be done as under: + +Required properties: + +- compatible : + "andestech,nds32v3-pmu" + +- interrupts : The interrupt number for NDS32 PMU is 13. + +Example: +pmu{ + compatible = "andestech,nds32v3-pmu"; + interrupts = <13>; +} -- cgit v1.2.3 From 9dab12c7a66db483f980a5a9203e1754c8e0cb20 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Fri, 5 Oct 2018 18:50:11 -0400 Subject: media: imx214: device tree binding Document bindings for imx214 camera sensor [Sakari Ailus: Move MAINTAINERS entry here, fix DT binding filename] Cc: devicetree@vger.kernel.org Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Laurent Pinchart Reviewed-by: Rob Herring Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/i2c/sony,imx214.txt | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/sony,imx214.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx214.txt b/Documentation/devicetree/bindings/media/i2c/sony,imx214.txt new file mode 100644 index 000000000000..f11f28a5fda4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx214.txt @@ -0,0 +1,53 @@ +* Sony 1/3.06-Inch 13.13Mp CMOS Digital Image Sensor + +The Sony imx214 is a 1/3.06-inch CMOS active pixel digital image sensor with +an active array size of 4224H x 3200V. It is programmable through an I2C +interface. +Image data is sent through MIPI CSI-2, through 2 or 4 lanes at a maximum +throughput of 1.2Gbps/lane. + + +Required Properties: +- compatible: Shall be "sony,imx214". +- reg: I2C bus address of the device. Depending on how the sensor is wired, + it shall be <0x10> or <0x1a>; +- enable-gpios: GPIO descriptor for the enable pin. +- vdddo-supply: Chip digital IO regulator (1.8V). +- vdda-supply: Chip analog regulator (2.7V). +- vddd-supply: Chip digital core regulator (1.12V). +- clocks: Reference to the xclk clock. +- clock-frequency: Frequency of the xclk clock. + +Optional Properties: +- flash-leds: See ../video-interfaces.txt +- lens-focus: See ../video-interfaces.txt + +The imx214 device node shall contain one 'port' child node with +an 'endpoint' subnode. For further reading on port node refer to +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Required Properties on endpoint: +- data-lanes: check ../video-interfaces.txt +- link-frequencies: check ../video-interfaces.txt +- remote-endpoint: check ../video-interfaces.txt + +Example: + + camera-sensor@1a { + compatible = "sony,imx214"; + reg = <0x1a>; + vdddo-supply = <&pm8994_lvs1>; + vddd-supply = <&camera_vddd_1v12>; + vdda-supply = <&pm8994_l17>; + lens-focus = <&ad5820>; + enable-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>; + clocks = <&mmcc CAMSS_MCLK0_CLK>; + clock-frequency = <24000000>; + port { + imx214_ep: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <480000000>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; -- cgit v1.2.3 From bd7ff187fac33c2fd221aa4073215d38d9c6b6ed Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 6 Nov 2018 05:20:25 +0000 Subject: ASoC: rsnd: tidyup Document for DT binding It has duplicated DT example code on Document. This patch tidyup these. Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/renesas,rsnd.txt | 214 ++++++++++----------- 1 file changed, 98 insertions(+), 116 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index d92b705e7917..8986764508db 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -39,15 +39,7 @@ This is example of Playback: [MEM] -> [SRC2] -> [DVC0] -> [SSIU0/SSI0] -> [codec] Capture: [MEM] <- [DVC1] <- [SRC3] <- [SSIU1/SSI1] <- [codec] - &rcar_sound { - ... - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src2 &dvc0>; - capture = <&ssi1 &src3 &dvc1>; - }; - }; - }; +see "Example: simple sound card" You can use below. ${LINUX}/arch/arm/boot/dts/r8a7790.dts can be good example. @@ -83,29 +75,8 @@ SRC can convert [xx]Hz to [yy]Hz. Then, it has below 2 modes ** Asynchronous mode ------------------ -You need to use "simple-scu-audio-card" sound card for it. -example) - - sound { - compatible = "simple-scu-audio-card"; - ... - /* - * SRC Asynchronous mode setting - * Playback: - * All input data will be converted to 48kHz - * Capture: - * Inputed 48kHz data will be converted to - * system specified Hz - */ - simple-audio-card,convert-rate = <48000>; - ... - simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - simple-audio-card,codec { - ... - }; - }; +You need to use "simple-scu-audio-card" or "audio-graph-scu-card" for it. +see "Example: simple sound card for Asynchronous mode" ------------------ ** Synchronous mode @@ -141,26 +112,8 @@ For more detail information, see below ${LINUX}/sound/soc/sh/rcar/ctu.c - comment of header -You need to use "simple-scu-audio-card" sound card for it. -example) - - sound { - compatible = "simple-scu-audio-card"; - ... - /* - * CTU setting - * All input data will be converted to 2ch - * as output data - */ - simple-audio-card,convert-channels = <2>; - ... - simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - simple-audio-card,codec { - ... - }; - }; +You need to use "simple-scu-audio-card" or "audio-graph-scu-card" for it. +see "Example: simple sound card for channel convert" Ex) Exchange output channel Input -> Output @@ -190,42 +143,13 @@ and these sounds will be merged by MIX. aplay -D plughw:0,0 xxxx.wav & aplay -D plughw:0,1 yyyy.wav -You need to use "simple-scu-audio-card" sound card for it. +You need to use "simple-scu-audio-card" or "audio-graph-scu-card" for it. Ex) [MEM] -> [SRC1] -> [CTU02] -+-> [MIX0] -> [DVC0] -> [SSI0] | [MEM] -> [SRC2] -> [CTU03] -+ - sound { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "simple-scu-audio-card"; - ... - simple-audio-card,cpu@0 { - reg = <0>; - sound-dai = <&rcar_sound 0>; - }; - simple-audio-card,cpu@1 { - reg = <1>; - sound-dai = <&rcar_sound 1>; - }; - simple-audio-card,codec { - ... - }; - }; - - &rcar_sound { - ... - rcar_sound,dai { - dai0 { - playback = <&src1 &ctu02 &mix0 &dvc0 &ssi0>; - }; - dai1 { - playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>; - }; - }; - }; +see "Example: simple sound card for MIXer" ============================================= * DVC (Digital Volume and Mute Function) @@ -304,14 +228,7 @@ This is example if SSI1 want to share WS pin with SSI0 You can use Multi-SSI. This is example of SSI0/SSI1/SSI2 (= for 6ch) - &rcar_sound { - ... - rcar_sound,dai { - dai0 { - playback = <&ssi0 &ssi1 &ssi2 &src0 &dvc0>; - }; - }; - }; +see "Example: simple sound card for Multi channel" ** TDM-SSI @@ -319,19 +236,7 @@ You can use TDM with SSI. This is example of TDM 6ch. Driver can automatically switches TDM <-> stereo mode in this case. - rsnd_tdm: sound { - compatible = "simple-audio-card"; - ... - simple-audio-card,cpu { - /* system can use TDM 6ch */ - dai-tdm-slot-num = <6>; - sound-dai = <&rcar_sound>; - }; - simple-audio-card,codec { - ... - }; - }; - +see "Example: simple sound card for TDM" ============================================= Required properties: @@ -647,25 +552,102 @@ Example: simple sound card }; ============================================= -Example: simple sound card for TDM +Example: simple sound card for Asynchronous mode ============================================= - rsnd_tdm: sound { - compatible = "simple-audio-card"; +sound { + compatible = "simple-scu-audio-card"; + ... + /* + * SRC Asynchronous mode setting + * Playback: + * All input data will be converted to 48kHz + * Capture: + * Inputed 48kHz data will be converted to + * system specified Hz + */ + simple-audio-card,convert-rate = <48000>; + ... + simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + simple-audio-card,codec { + ... + }; +}; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; +============================================= +Example: simple sound card for channel convert +============================================= - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - dai-tdm-slot-num = <6>; - }; +sound { + compatible = "simple-scu-audio-card"; + ... + /* + * CTU setting + * All input data will be converted to 2ch + * as output data + */ + simple-audio-card,convert-channels = <2>; + ... + simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + simple-audio-card,codec { + ... + }; +}; - sndcodec: simple-audio-card,codec { - sound-dai = <&xxx>; +============================================= +Example: simple sound card for MIXer +============================================= + +sound { + compatible = "simple-scu-audio-card"; + ... + simple-audio-card,cpu@0 { + sound-dai = <&rcar_sound 0>; + }; + simple-audio-card,cpu@1 { + sound-dai = <&rcar_sound 1>; + }; + simple-audio-card,codec { + ... + }; +}; + +&rcar_sound { + ... + rcar_sound,dai { + dai0 { + playback = <&src1 &ctu02 &mix0 &dvc0 &ssi0>; + }; + dai1 { + playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>; }; }; +}; + +============================================= +Example: simple sound card for TDM +============================================= + +rsnd_tdm: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + dai-tdm-slot-num = <6>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&xxx>; + }; +}; ============================================= Example: simple sound card for Multi channel -- cgit v1.2.3 From da48a6eb82ea2eaa26464f863f0f39908727bfdb Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 6 Nov 2018 05:20:56 +0000 Subject: ASoC: rsnd: add SSIU BUSIF support for Document Gen2 has BUSIF0-3, Gen3 has BUSIF0-7 on some SSIU. Current driver is assuming it is using BUSIF0 as default. Thus, SSI is attaching SSIU (with BUSIF0) by using rsnd_ssiu_attach(). But, TDM split mode also needs other BUSIF to use it. This patch adds missing SSIU BUSIFx support. BUSIF is handled by SSIU instead of SSI anymore. Thus, its settings no longer needed on SSI node on DT. This patch removes its settings from Document, but driver is still keeping compatibility. Thus, old DT style is still working. But, to avoid confusing, it doesn't indicate old compatibility things on Document. New SoC should have SSIU on DT from this patch. 1) old style DT is still supported (= no rcar_sound,ssiu node on DT) 2) If ssiu is not indicated on playback/capture, BUSIF0 will be used as default playback = <&ssi3>; /* ssiu30 will be selected */ 3) you can select own ssiu playback = <&ssi32 &ssi3>; /* ssiu32 will be selected */ Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/renesas,rsnd.txt | 87 +++++++++++----------- 1 file changed, 43 insertions(+), 44 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index 8986764508db..6ed1a3658ffd 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -181,15 +181,12 @@ Volume Ramp * SSIU (Serial Sound Interface Unit) ============================================= -There is no DT settings for SSIU, because SSIU will be automatically -selected via SSI. SSIU can avoid some under/over run error, because it has some buffer. But you can't use it if SSI was PIO mode. -In DMA mode, you can select not to use SSIU by using "no-busif" on DT. +In DMA mode, you can select not to use SSIU by using "no-busif" via SSI. - &ssi0 { - no-busif; - }; +SSIU handles BUSIF which will be used for TDM Split mode. +This driver is assuming that audio-graph card will be used. ============================================= * SSI (Serial Sound Interface) @@ -268,6 +265,9 @@ Required properties: - rcar_sound,ssi : Should contain SSI feature. The number of SSI subnode should be same as HW. see below for detail. +- rcar_sound,ssiu : Should contain SSIU feature. + The number of SSIU subnode should be same as HW. + see below for detail. - rcar_sound,src : Should contain SRC feature. The number of SRC subnode should be same as HW. see below for detail. @@ -437,56 +437,55 @@ rcar_sound: sound@ec500000 { }; }; + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + + ... + + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + }; + rcar_sound,ssi { ssi0: ssi-0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; }; ssi1: ssi-1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; }; + + ... + ssi8: ssi-8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; }; ssi9: ssi-9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; }; }; -- cgit v1.2.3 From cf704dc83fd6600758e98ac71769eaeb00dfc770 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 6 Nov 2018 05:21:22 +0000 Subject: ASoC: rsnd: add TDM Split mode support for Document This patch adds TDM Split mode support. rsnd driver is assuming audio-graph-scu-card is used for Sound Card. Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/renesas,rsnd.txt | 91 ++++++++++++++++++++++ 1 file changed, 91 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index 6ed1a3658ffd..453e8ec2ac78 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -188,6 +188,25 @@ In DMA mode, you can select not to use SSIU by using "no-busif" via SSI. SSIU handles BUSIF which will be used for TDM Split mode. This driver is assuming that audio-graph card will be used. +TDM Split mode merges 4 sounds. You can see 4 sound interface on system, +and these sounds will be merged SSIU/SSI. + + aplay -D plughw:0,0 xxxx.wav & + aplay -D plughw:0,1 xxxx.wav & + aplay -D plughw:0,2 xxxx.wav & + aplay -D plughw:0,3 xxxx.wav + + 2ch 8ch + [MEM] -> [SSIU 30] -+-> [SSIU 3] --> [Codec] + 2ch | + [MEM] -> [SSIU 31] -+ + 2ch | + [MEM] -> [SSIU 32] -+ + 2ch | + [MEM] -> [SSIU 33] -+ + +see "Example: simple sound card for TDM Split" + ============================================= * SSI (Serial Sound Interface) ============================================= @@ -648,6 +667,78 @@ rsnd_tdm: sound { }; }; +============================================= +Example: simple sound card for TDM Split +============================================= + +sound_card: sound { + compatible = "audio-graph-scu-card"; + prefix = "xxxx"; + routing = "xxxx Playback", "DAI0 Playback", + "xxxx Playback", "DAI1 Playback", + "xxxx Playback", "DAI2 Playback", + "xxxx Playback", "DAI3 Playback"; + convert-channels = <8>; /* TDM Split */ + + dais = <&rsnd_port0 /* playback ch1/ch2 */ + &rsnd_port1 /* playback ch3/ch4 */ + &rsnd_port2 /* playback ch5/ch6 */ + &rsnd_port3 /* playback ch7/ch8 */ + >; +}; + +audio-codec { + ... + port { + codec_0: endpoint@1 { + remote-endpoint = <&rsnd_ep0>; + }; + codec_1: endpoint@2 { + remote-endpoint = <&rsnd_ep1>; + }; + codec_2: endpoint@3 { + remote-endpoint = <&rsnd_ep2>; + }; + codec_3: endpoint@4 { + remote-endpoint = <&rsnd_ep3>; + }; + }; +}; + +&rcar_sound { + ... + ports { + rsnd_port0: port@0 { + rsnd_ep0: endpoint { + remote-endpoint = <&codec_0>; + ... + playback = <&ssiu30 &ssi3>; + }; + }; + rsnd_port1: port@1 { + rsnd_ep1: endpoint { + remote-endpoint = <&codec_1>; + ... + playback = <&ssiu31 &ssi3>; + }; + }; + rsnd_port2: port@2 { + rsnd_ep2: endpoint { + remote-endpoint = <&codec_2>; + ... + playback = <&ssiu32 &ssi3>; + }; + }; + rsnd_port3: port@3 { + rsnd_ep3: endpoint { + remote-endpoint = <&codec_3>; + ... + playback = <&ssiu33 &ssi3>; + }; + }; + }; +}; + ============================================= Example: simple sound card for Multi channel ============================================= -- cgit v1.2.3 From eaeee28db2893dc56a29751f19210dc8ce8247c3 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 3 Nov 2018 00:00:02 -0700 Subject: clk: qcom: smd: Add support for QCS404 rpm clocks Add rpm smd clocks, PMIC and bus clocks which are required on QCS404 for clients to vote on. Signed-off-by: Taniya Das Signed-off-by: Anu Ramanathan [bjorn: Dropped cxo, voter clocks and static initialization] Signed-off-by: Bjorn Andersson Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,rpmcc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index 4491d1c104aa..87b4949e9bc8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -16,6 +16,7 @@ Required properties : "qcom,rpmcc-msm8974", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" "qcom,rpmcc-msm8996", "qcom,rpmcc" + "qcom,rpmcc-qcs404", "qcom,rpmcc" - #clock-cells : shall contain 1 -- cgit v1.2.3 From a2aabe5f3c57fabefe369b636db3df86874218be Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 17 Sep 2018 09:22:22 +0100 Subject: dt-bindings: soc: Document "brcm,bcm2836-vchiq" "brcm,bcm2836-vchiq" should be used on BCM2836 and BCM2837 to ensure correct operation. Signed-off-by: Phil Elwell Acked-by: Stefan Wahren Signed-off-by: Stefan Wahren --- Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt index 8dd7b3a7de65..f331316183f6 100644 --- a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt +++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt @@ -2,7 +2,8 @@ Broadcom VCHIQ firmware services Required properties: -- compatible: Should be "brcm,bcm2835-vchiq" +- compatible: Should be "brcm,bcm2835-vchiq" on BCM2835, otherwise + "brcm,bcm2836-vchiq". - reg: Physical base address and length of the doorbell register pair - interrupts: The interrupt number See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt -- cgit v1.2.3 From da0b7c7766ea96d057094ecd05bcc1b3fec7e538 Mon Sep 17 00:00:00 2001 From: Badhri Jagan Sridharan Date: Mon, 1 Oct 2018 12:44:59 -0700 Subject: dt-bindings: connector: Add self-powered property >From USB_PD_R3_0 7.1.5 Response to Hard Resets Device operation during and after a Hard Reset is defined as follows: Self-powered devices Should Not disconnect from USB during a Hard Reset (see Section 9.1.2). Bus powered devices will disconnect from USB during a Hard Reset due to the loss of their power source. Therefore it is necessary to know whether the port belongs to a device which is self powered or bus powered. This change adds "self-powered" flag to the connector class which present indicates that the port belongs to a device that is self powered. Else it is bus powered usb device. Signed-off-by: Badhri Jagan Sridharan Reviewed-by: Rob Herring ------- Changes is v3: - Rebase on top of usb-next - no change w.r.t to this patch. Same as previous versions. No v2 version as the patch was introduced there. Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/connector/usb-connector.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/connector/usb-connector.txt b/Documentation/devicetree/bindings/connector/usb-connector.txt index d90e17e2428b..a9a2f2fc44f2 100644 --- a/Documentation/devicetree/bindings/connector/usb-connector.txt +++ b/Documentation/devicetree/bindings/connector/usb-connector.txt @@ -14,6 +14,8 @@ Optional properties: - label: symbolic name for the connector, - type: size of the connector, should be specified in case of USB-A, USB-B non-fullsize connectors: "mini", "micro". +- self-powered: Set this property if the usb device that has its own power + source. Optional properties for usb-c-connector: - power-role: should be one of "source", "sink" or "dual"(DRP) if typec -- cgit v1.2.3 From b1d9d6cb30fe6bd1b844ae98a372471f17c4fdc4 Mon Sep 17 00:00:00 2001 From: Peng Hao Date: Tue, 6 Nov 2018 22:57:15 +0800 Subject: dt-bindings: misc/pvpanic: add document for pvpanic-mmio Add dt-bindings document for "qemu:pvpanic-mmio". Acked-by: Mark Rutland Signed-off-by: Peng Hao Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/misc/pvpanic-mmio.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/pvpanic-mmio.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/misc/pvpanic-mmio.txt b/Documentation/devicetree/bindings/misc/pvpanic-mmio.txt new file mode 100644 index 000000000000..985e90736780 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/pvpanic-mmio.txt @@ -0,0 +1,29 @@ +* QEMU PVPANIC MMIO Configuration bindings + +QEMU's emulation / virtualization targets provide the following PVPANIC +MMIO Configuration interface on the "virt" machine. +type: + +- a read-write, 16-bit wide data register. + +QEMU exposes the data register to guests as memory mapped registers. + +Required properties: + +- compatible: "qemu,pvpanic-mmio". +- reg: the MMIO region used by the device. + * Bytes 0x0 Write panic event to the reg when guest OS panics. + * Bytes 0x1 Reserved. + +Example: + +/ { + #size-cells = <0x2>; + #address-cells = <0x2>; + + pvpanic-mmio@9060000 { + compatible = "qemu,pvpanic-mmio"; + reg = <0x0 0x9060000 0x0 0x2>; + }; +}; + -- cgit v1.2.3 From a24626d72915fef2b38bb8467b3714f17efae6c0 Mon Sep 17 00:00:00 2001 From: Piotr Bugalski Date: Mon, 5 Nov 2018 11:36:25 +0100 Subject: dt-bindings: spi: QuadSPI driver for Atmel SAMA5D2 Atmel SAMA5D2 QuadSPI driver was moved from mtd to spi subsystem, this change is just moving DT-binding documentation. Suggested-by: Boris Brezillon Signed-off-by: Piotr Bugalski Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- .../devicetree/bindings/mtd/atmel-quadspi.txt | 31 ---------------------- .../devicetree/bindings/spi/atmel-quadspi.txt | 31 ++++++++++++++++++++++ 2 files changed, 31 insertions(+), 31 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/atmel-quadspi.txt create mode 100644 Documentation/devicetree/bindings/spi/atmel-quadspi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt b/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt deleted file mode 100644 index b93c1e2f25dd..000000000000 --- a/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Atmel Quad Serial Peripheral Interface (QSPI) - -Required properties: -- compatible: Should be "atmel,sama5d2-qspi". -- reg: Should contain the locations and lengths of the base registers - and the mapped memory. -- reg-names: Should contain the resource reg names: - - qspi_base: configuration register address space - - qspi_mmap: memory mapped address space -- interrupts: Should contain the interrupt for the device. -- clocks: The phandle of the clock needed by the QSPI controller. -- #address-cells: Should be <1>. -- #size-cells: Should be <0>. - -Example: - -spi@f0020000 { - compatible = "atmel,sama5d2-qspi"; - reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>; - reg-names = "qspi_base", "qspi_mmap"; - interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&spi0_clk>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_default>; - - m25p80@0 { - ... - }; -}; diff --git a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt new file mode 100644 index 000000000000..b93c1e2f25dd --- /dev/null +++ b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt @@ -0,0 +1,31 @@ +* Atmel Quad Serial Peripheral Interface (QSPI) + +Required properties: +- compatible: Should be "atmel,sama5d2-qspi". +- reg: Should contain the locations and lengths of the base registers + and the mapped memory. +- reg-names: Should contain the resource reg names: + - qspi_base: configuration register address space + - qspi_mmap: memory mapped address space +- interrupts: Should contain the interrupt for the device. +- clocks: The phandle of the clock needed by the QSPI controller. +- #address-cells: Should be <1>. +- #size-cells: Should be <0>. + +Example: + +spi@f0020000 { + compatible = "atmel,sama5d2-qspi"; + reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&spi0_clk>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0_default>; + + m25p80@0 { + ... + }; +}; -- cgit v1.2.3 From abc61f47a70f7c8331f00eff1ccb6557a9d4c224 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Wed, 7 Nov 2018 16:09:25 +0530 Subject: spi: omap-spi: Add compatible for AM654 SoC AM654 SoC has same McSPI IP as OMAP2+ platforms. Add new compatible to support McSPI on AM654 SoC. Signed-off-by: Vignesh R Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/omap-spi.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt b/Documentation/devicetree/bindings/spi/omap-spi.txt index 2ba5f9c023ac..487208c256c0 100644 --- a/Documentation/devicetree/bindings/spi/omap-spi.txt +++ b/Documentation/devicetree/bindings/spi/omap-spi.txt @@ -2,6 +2,7 @@ OMAP2+ McSPI device Required properties: - compatible : + - "ti,am654-mcspi" for AM654. - "ti,omap2-mcspi" for OMAP2 & OMAP3. - "ti,omap4-mcspi" for OMAP4+. - ti,spi-num-cs : Number of chipselect supported by the instance. -- cgit v1.2.3 From df80e0478972260bf285c5ed33f99b2424fba2af Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 1 Nov 2018 12:35:02 +0000 Subject: spi: rspi: Add r8a77470 to the compatible list Add r8a77470 to the list of examples with soctypes. No driver change is needed as "renesas,qspi" will activate the right code within the corresponding driver. Signed-off-by: Fabrizio Castro Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-rspi.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-rspi.txt b/Documentation/devicetree/bindings/spi/spi-rspi.txt index fc97ad64fbf2..421722b93992 100644 --- a/Documentation/devicetree/bindings/spi/spi-rspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-rspi.txt @@ -15,6 +15,7 @@ Required properties: - "renesas,qspi-r8a7743" (RZ/G1M) - "renesas,qspi-r8a7744" (RZ/G1N) - "renesas,qspi-r8a7745" (RZ/G1E) + - "renesas,qspi-r8a77470" (RZ/G1C) - "renesas,qspi-r8a7790" (R-Car H2) - "renesas,qspi-r8a7791" (R-Car M2-W) - "renesas,qspi-r8a7792" (R-Car V2H) -- cgit v1.2.3 From ad348c3f55962c86adf9c8cb3712825fb7db5336 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 28 Sep 2018 15:11:46 +0100 Subject: dt-bindings: usb: xhci-tegra: Add power-domain details Add details for power-domains to the Tegra xHCI bindings so that generic power-domains can be used for inconjunction with the xHCI driver. Signed-off-by: Jon Hunter Acked-by: Thierry Reding Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt index 3eee9e505400..4156c3e181c5 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt @@ -59,6 +59,14 @@ For Tegra210: - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V. - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V. - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V. +- power-domains: A list of PM domain specifiers that reference each power-domain + used by the xHCI controller. This list must comprise of a specifier for the + XUSBA and XUSBC power-domains. See ../power/power_domain.txt and + ../arm/tegra/nvidia,tegra20-pmc.txt for details. +- power-domain-names: A list of names that represent each of the specifiers in + the 'power-domains' property. Must include 'xusb_ss' and 'xusb_host' which + represent the power-domains XUSBA and XUSBC, respectively. See + ../power/power_domain.txt for details. Optional properties: -------------------- -- cgit v1.2.3 From a6cb8ef03cb0f03e3567f91ab9aeb2f0f6337810 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 21 Oct 2018 21:30:45 +0300 Subject: dt: bindings: tegra20-emc: Document interrupt property EMC has a dedicated interrupt that is used to notify about completion of HW operations. Document the interrupt property. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Acked-by: Peter De Schrijver Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt index 4c33b29dc660..a6fe401d0d48 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt @@ -10,6 +10,7 @@ Properties: and chosen using the ramcode board selector. If omitted, only one set of tables can be present and said tables will be used irrespective of ram-code configuration. +- interrupts : Should contain EMC General interrupt. Child device nodes describe the memory settings for different configurations and clock rates. @@ -20,6 +21,7 @@ Example: #size-cells = < 0 >; compatible = "nvidia,tegra20-emc"; reg = <0x7000f4000 0x200>; + interrupts = <0 78 0x04>; } -- cgit v1.2.3 From 28016aa1652e64e143b88baacbb13f121894f260 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 21 Oct 2018 21:30:46 +0300 Subject: dt: bindings: tegra20-emc: Document clock property Embedded memory controller has a corresponding clock, document the clock property. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt index a6fe401d0d48..add95367640b 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt @@ -11,6 +11,7 @@ Properties: set of tables can be present and said tables will be used irrespective of ram-code configuration. - interrupts : Should contain EMC General interrupt. +- clocks : Should contain EMC clock. Child device nodes describe the memory settings for different configurations and clock rates. @@ -22,6 +23,7 @@ Example: compatible = "nvidia,tegra20-emc"; reg = <0x7000f4000 0x200>; interrupts = <0 78 0x04>; + clocks = <&tegra_car TEGRA20_CLK_EMC>; } -- cgit v1.2.3 From 94ba4a5f16710eaa3a675761a7900bb9f79715db Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 21 Oct 2018 21:30:47 +0300 Subject: dt: bindings: Move tegra20-emc binding to memory-controllers directory Move tegra20-emc binding to the memory-controllers directory for consistency with the other Tegra memory bindings. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/arm/tegra/nvidia,tegra20-emc.txt | 104 --------------------- .../memory-controllers/nvidia,tegra20-emc.txt | 104 +++++++++++++++++++++ 2 files changed, 104 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt deleted file mode 100644 index add95367640b..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ /dev/null @@ -1,104 +0,0 @@ -Embedded Memory Controller - -Properties: -- name : Should be emc -- #address-cells : Should be 1 -- #size-cells : Should be 0 -- compatible : Should contain "nvidia,tegra20-emc". -- reg : Offset and length of the register set for the device -- nvidia,use-ram-code : If present, the sub-nodes will be addressed - and chosen using the ramcode board selector. If omitted, only one - set of tables can be present and said tables will be used - irrespective of ram-code configuration. -- interrupts : Should contain EMC General interrupt. -- clocks : Should contain EMC clock. - -Child device nodes describe the memory settings for different configurations and clock rates. - -Example: - - memory-controller@7000f400 { - #address-cells = < 1 >; - #size-cells = < 0 >; - compatible = "nvidia,tegra20-emc"; - reg = <0x7000f4000 0x200>; - interrupts = <0 78 0x04>; - clocks = <&tegra_car TEGRA20_CLK_EMC>; - } - - -Embedded Memory Controller ram-code table - -If the emc node has the nvidia,use-ram-code property present, then the -next level of nodes below the emc table are used to specify which settings -apply for which ram-code settings. - -If the emc node lacks the nvidia,use-ram-code property, this level is omitted -and the tables are stored directly under the emc node (see below). - -Properties: - -- name : Should be emc-tables -- nvidia,ram-code : the binary representation of the ram-code board strappings - for which this node (and children) are valid. - - - -Embedded Memory Controller configuration table - -This is a table containing the EMC register settings for the various -operating speeds of the memory controller. They are always located as -subnodes of the emc controller node. - -There are two ways of specifying which tables to use: - -* The simplest is if there is just one set of tables in the device tree, - and they will always be used (based on which frequency is used). - This is the preferred method, especially when firmware can fill in - this information based on the specific system information and just - pass it on to the kernel. - -* The slightly more complex one is when more than one memory configuration - might exist on the system. The Tegra20 platform handles this during - early boot by selecting one out of possible 4 memory settings based - on a 2-pin "ram code" bootstrap setting on the board. The values of - these strappings can be read through a register in the SoC, and thus - used to select which tables to use. - -Properties: -- name : Should be emc-table -- compatible : Should contain "nvidia,tegra20-emc-table". -- reg : either an opaque enumerator to tell different tables apart, or - the valid frequency for which the table should be used (in kHz). -- clock-frequency : the clock frequency for the EMC at which this - table should be used (in kHz). -- nvidia,emc-registers : a 46 word array of EMC registers to be programmed - for operation at the 'clock-frequency' setting. - The order and contents of the registers are: - RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, - WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, - PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, - TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, - ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, - ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, - CFG_CLKTRIM_1, CFG_CLKTRIM_2 - - emc-table@166000 { - reg = <166000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 166000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; - - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 333000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt new file mode 100644 index 000000000000..add95367640b --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -0,0 +1,104 @@ +Embedded Memory Controller + +Properties: +- name : Should be emc +- #address-cells : Should be 1 +- #size-cells : Should be 0 +- compatible : Should contain "nvidia,tegra20-emc". +- reg : Offset and length of the register set for the device +- nvidia,use-ram-code : If present, the sub-nodes will be addressed + and chosen using the ramcode board selector. If omitted, only one + set of tables can be present and said tables will be used + irrespective of ram-code configuration. +- interrupts : Should contain EMC General interrupt. +- clocks : Should contain EMC clock. + +Child device nodes describe the memory settings for different configurations and clock rates. + +Example: + + memory-controller@7000f400 { + #address-cells = < 1 >; + #size-cells = < 0 >; + compatible = "nvidia,tegra20-emc"; + reg = <0x7000f4000 0x200>; + interrupts = <0 78 0x04>; + clocks = <&tegra_car TEGRA20_CLK_EMC>; + } + + +Embedded Memory Controller ram-code table + +If the emc node has the nvidia,use-ram-code property present, then the +next level of nodes below the emc table are used to specify which settings +apply for which ram-code settings. + +If the emc node lacks the nvidia,use-ram-code property, this level is omitted +and the tables are stored directly under the emc node (see below). + +Properties: + +- name : Should be emc-tables +- nvidia,ram-code : the binary representation of the ram-code board strappings + for which this node (and children) are valid. + + + +Embedded Memory Controller configuration table + +This is a table containing the EMC register settings for the various +operating speeds of the memory controller. They are always located as +subnodes of the emc controller node. + +There are two ways of specifying which tables to use: + +* The simplest is if there is just one set of tables in the device tree, + and they will always be used (based on which frequency is used). + This is the preferred method, especially when firmware can fill in + this information based on the specific system information and just + pass it on to the kernel. + +* The slightly more complex one is when more than one memory configuration + might exist on the system. The Tegra20 platform handles this during + early boot by selecting one out of possible 4 memory settings based + on a 2-pin "ram code" bootstrap setting on the board. The values of + these strappings can be read through a register in the SoC, and thus + used to select which tables to use. + +Properties: +- name : Should be emc-table +- compatible : Should contain "nvidia,tegra20-emc-table". +- reg : either an opaque enumerator to tell different tables apart, or + the valid frequency for which the table should be used (in kHz). +- clock-frequency : the clock frequency for the EMC at which this + table should be used (in kHz). +- nvidia,emc-registers : a 46 word array of EMC registers to be programmed + for operation at the 'clock-frequency' setting. + The order and contents of the registers are: + RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, + WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, + PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, + TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, + ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, + ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, + CFG_CLKTRIM_1, CFG_CLKTRIM_2 + + emc-table@166000 { + reg = <166000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 166000 >; + nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 >; + }; + + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 333000 >; + nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 >; + }; -- cgit v1.2.3 From 31fc9763f9d752b75711156ef6a066f6ea264be5 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 17 Aug 2018 15:31:05 +0100 Subject: dt-bindings: iommu: ipmmu-vmsa: Add r8a774a1 support Document RZ/G2M (R8A774A1) SoC bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Rob Herring Reviewed-by: Simon Horman Signed-off-by: Joerg Roedel --- Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt index 377ee639d103..e285c8ad1b39 100644 --- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt @@ -14,6 +14,7 @@ Required Properties: - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU. - "renesas,ipmmu-r8a7744" for the R8A7744 (RZ/G1N) IPMMU. - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU. + - "renesas,ipmmu-r8a774a1" for the R8A774A1 (RZ/G2M) IPMMU. - "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU. - "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU. - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU. -- cgit v1.2.3 From d3b687c58ad9343532b4a20e541934eb1b557453 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Fri, 5 Oct 2018 18:36:32 +0300 Subject: regulator: Change regulator-coupled-max-spread property Redefine binding for regulator-coupled-max-spread property in a way that max-spread values are defined per regulator couple instead of defining single max-spread for the whole group of coupled regulators. With that change the following regulators coupling configuration will be possible: regA: regulatorA { regulator-coupled-with = <®B ®C>; regulator-coupled-max-spread = <100000 300000>; }; regB: regulatorB { regulator-coupled-with = <®A ®C>; regulator-coupled-max-spread = <100000 200000>; }; regC: regulatorC { regulator-coupled-with = <®A ®B>; regulator-coupled-max-spread = <300000 200000>; }; Signed-off-by: Dmitry Osipenko Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/regulator.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index a7cd36877bfe..9b525b657fca 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt @@ -76,8 +76,9 @@ Optional properties: - regulator-coupled-with: Regulators with which the regulator is coupled. The linkage is 2-way - all coupled regulators should be linked with each other. A regulator should not be coupled with its supplier. -- regulator-coupled-max-spread: Max spread between voltages of coupled regulators - in microvolts. +- regulator-coupled-max-spread: Array of maximum spread between voltages of + coupled regulators in microvolts, each value in the array relates to the + corresponding couple specified by the regulator-coupled-with property. Deprecated properties: - regulator-compatible: If a regulator chip contains multiple -- cgit v1.2.3 From a2dfe7c7dfb65c814cfa2777b46e687db1820cc4 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Fri, 5 Oct 2018 18:36:34 +0300 Subject: regulator: Document new regulator-max-step-microvolt property Certain hardware may require supply voltage to be changed in steps. Define new property that allow to describe such hardware. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/regulator.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index 9b525b657fca..0c3a243c95df 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt @@ -79,6 +79,8 @@ Optional properties: - regulator-coupled-max-spread: Array of maximum spread between voltages of coupled regulators in microvolts, each value in the array relates to the corresponding couple specified by the regulator-coupled-with property. +- regulator-max-step-microvolt: Maximum difference between current and target + voltages that can be changed safely in a single step. Deprecated properties: - regulator-compatible: If a regulator chip contains multiple -- cgit v1.2.3 From d422912a8f0da30c4c6b2f482e5cfc0b85cd3119 Mon Sep 17 00:00:00 2001 From: Gilad Ben-Yossef Date: Mon, 29 Oct 2018 09:50:13 +0000 Subject: dt-bindings: crypto: ccree: add ccree 713 Add device tree bindings associating Arm TrustZone CryptoCell 713 with the ccree driver. Signed-off-by: Gilad Ben-Yossef Reviewed-by: Rob Herring Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/crypto/arm-cryptocell.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt index 999fb2a810f6..0ac06ec05272 100644 --- a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt +++ b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt @@ -1,8 +1,11 @@ Arm TrustZone CryptoCell cryptographic engine Required properties: -- compatible: Should be one of: "arm,cryptocell-712-ree", - "arm,cryptocell-710-ree" or "arm,cryptocell-630p-ree". +- compatible: Should be one of - + "arm,cryptocell-713-ree" + "arm,cryptocell-712-ree" + "arm,cryptocell-710-ree" + "arm,cryptocell-630p-ree" - reg: Base physical address of the engine and length of memory mapped region. - interrupts: Interrupt number for the device. -- cgit v1.2.3 From 0934eec7bce20324136f013c049088ebf00c3d3f Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Fri, 2 Nov 2018 09:12:58 +0000 Subject: dt-bindings: pinctrl: imx7ulp: back to imx legacy binding for consistency We already had an earlier conclusion that all new i.MX Socs will keep using the legacy i.MX Pinctrl bindings instead of generic pin config. However, MX7ULP generic pin config binding support has already been in tree before that time. Per SoC maintainers' suggestions, in order to get a better consistency for all i.MX devices, we'd like to go back to imx legacy binding for MX7ULP as well. Cc: Linus Walleij Cc: Shawn Guo Cc: Stefan Agner Cc: Sascha Hauer Cc: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng Acked-by: Fabio Estevam Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt | 66 ++++++++++------------ 1 file changed, 29 insertions(+), 37 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt index 44ad670ae11e..bfa3703a7446 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt @@ -7,55 +7,47 @@ Note: This binding doc is only for the IOMUXC1 support in A7 Domain and it only supports generic pin config. -Please also refer pinctrl-bindings.txt in this directory for generic pinctrl -binding. - -=== Pin Controller Node === +Please refer to fsl,imx-pinctrl.txt in this directory for common binding +part and usage. Required properties: -- compatible: "fsl,imx7ulp-iomuxc1" -- reg: Should contain the base physical address and size of the iomuxc - registers. - -=== Pin Configuration Node === -- pinmux: One integers array, represents a group of pins mux setting. - The format is pinmux = , PIN_FUNC_ID is a pin working on - a specific function. - - NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux - and config register as follows: - - - Refer to imx7ulp-pinfunc.h in in device tree source folder for all - available imx7ulp PIN_FUNC_ID. - -Optional Properties: -- drive-strength Integer. Controls Drive Strength - 0: Standard - 1: Hi Driver -- drive-push-pull Bool. Enable Pin Push-pull -- drive-open-drain Bool. Enable Pin Open-drian -- slew-rate: Integer. Controls Slew Rate - 0: Standard - 1: Slow -- bias-disable: Bool. Pull disabled -- bias-pull-down: Bool. Pull down on pin -- bias-pull-up: Bool. Pull up on pin +- compatible: "fsl,imx7ulp-iomuxc1". +- fsl,pins: Each entry consists of 5 integers which represents the mux + and config setting for one pin. The first 4 integers + are specified + using a PIN_FUNC_ID macro, which can be found in + imx7ulp-pinfunc.h in the device tree source folder. + The last integer CONFIG is the pad setting value like + pull-up on this pin. + + Please refer to i.MX7ULP Reference Manual for detailed + CONFIG settings. + +CONFIG bits definition: +PAD_CTL_OBE (1 << 17) +PAD_CTL_IBE (1 << 16) +PAD_CTL_LK (1 << 16) +PAD_CTL_DSE_HI (1 << 6) +PAD_CTL_DSE_STD (0 << 6) +PAD_CTL_ODE (1 << 5) +PAD_CTL_PUSH_PULL (0 << 5) +PAD_CTL_SRE_SLOW (1 << 2) +PAD_CTL_SRE_STD (0 << 2) +PAD_CTL_PE (1 << 0) Examples: #include "imx7ulp-pinfunc.h" /* Pin Controller Node */ -iomuxc1: iomuxc@40ac0000 { +iomuxc1: pinctrl@40ac0000 { compatible = "fsl,imx7ulp-iomuxc1"; reg = <0x40ac0000 0x1000>; /* Pin Configuration Node */ pinctrl_lpuart4: lpuart4grp { - pinmux = < - IMX7ULP_PAD_PTC3__LPUART4_RX - IMX7ULP_PAD_PTC2__LPUART4_TX + fsl,pins = < + IMX7ULP_PAD_PTC3__LPUART4_RX 0x1 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x1 >; - bias-pull-up; }; }; -- cgit v1.2.3 From 9e1e8a75708031937a0f92567c19760c92658410 Mon Sep 17 00:00:00 2001 From: Subhash Jadavani Date: Tue, 16 Oct 2018 14:29:41 +0530 Subject: scsi: ufs: set the device reference clock setting UFS host supplies the reference clock to UFS device and UFS device specification allows host to provide one of the 4 frequencies (19.2 MHz, 26 MHz, 38.4 MHz, 52 MHz) for reference clock. Host should set the device reference clock frequency setting in the device based on what frequency it is supplying to UFS device. Signed-off-by: Subhash Jadavani Signed-off-by: Can Guo Signed-off-by: Sayali Lokhande Reviewed-by: Evan Green Acked-by: Rob Herring Signed-off-by: Martin K. Petersen --- Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index 2df00524bd21..8cf59452c675 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -33,6 +33,12 @@ Optional properties: - clocks : List of phandle and clock specifier pairs - clock-names : List of clock input name strings sorted in the same order as the clocks property. + "ref_clk" indicates reference clock frequency. + UFS host supplies reference clock to UFS device and UFS device + specification allows host to provide one of the 4 frequencies (19.2 MHz, + 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is + parsed and used to update the reference clock setting in device. + Defaults to 26 MHz(as per specification) if not specified by host. - freq-table-hz : Array of operating frequencies stored in the same order as the clocks property. If this property is not defined or a value in the array is "0" then it is assumed -- cgit v1.2.3 From 85408f830e704fdc2353dbf4454df01949f51257 Mon Sep 17 00:00:00 2001 From: Janek Kotas Date: Thu, 20 Sep 2018 13:08:22 +0000 Subject: scsi: dt-bindings: ufs: Add bindings for Cadence UFS This patch adds a DT binding documentation for Cadence UFS Host Controller. Signed-off-by: Jan Kotas Reviewed-by: Rob Herring Signed-off-by: Martin K. Petersen --- .../devicetree/bindings/ufs/cdns,ufshc.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt new file mode 100644 index 000000000000..a04a4989ec7f --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt @@ -0,0 +1,31 @@ +* Cadence Universal Flash Storage (UFS) Controller + +UFS nodes are defined to describe on-chip UFS host controllers. +Each UFS controller instance should have its own node. +Please see the ufshcd-pltfrm.txt for a list of all available properties. + +Required properties: +- compatible : Compatible list, contains the following controller: + "cdns,ufshc" + complemented with the JEDEC version: + "jedec,ufs-2.0" + +- reg : Address and length of the UFS register set. +- interrupts : One interrupt mapping. +- freq-table-hz : Clock frequency table. + See the ufshcd-pltfrm.txt for details. +- clocks : List of phandle and clock specifier pairs. +- clock-names : List of clock input name strings sorted in the same + order as the clocks property. "core_clk" is mandatory. + Depending on a type of a PHY, + the "phy_clk" clock can also be added, if needed. + +Example: + ufs@fd030000 { + compatible = "cdns,ufshc", "jedec,ufs-2.0"; + reg = <0xfd030000 0x10000>; + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; + freq-table-hz = <0 0>, <0 0>; + clocks = <&ufs_core_clk>, <&ufs_phy_clk>; + clock-names = "core_clk", "phy_clk"; + }; -- cgit v1.2.3 From 275d924b4b0673dc26c68fed0c3f357a225c2799 Mon Sep 17 00:00:00 2001 From: Songjun Wu Date: Tue, 16 Oct 2018 17:19:15 +0800 Subject: dt-bindings: serial: lantiq: Add optional properties for CCF Clocks and clock-names are updated in device tree binding. Reviewed-by: Rob Herring Signed-off-by: Songjun Wu Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/lantiq_asc.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/Documentation/devicetree/bindings/serial/lantiq_asc.txt index 3acbd309ab9d..40e81a5818f6 100644 --- a/Documentation/devicetree/bindings/serial/lantiq_asc.txt +++ b/Documentation/devicetree/bindings/serial/lantiq_asc.txt @@ -6,8 +6,23 @@ Required properties: - interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier depends on the interrupt-parent interrupt controller. +Optional properties: +- clocks: Should contain frequency clock and gate clock +- clock-names: Should be "freq" and "asc" + Example: +asc0: serial@16600000 { + compatible = "lantiq,asc"; + reg = <0x16600000 0x100000>; + interrupt-parent = <&gic>; + interrupts = , + , + ; + clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>; + clock-names = "freq", "asc"; +}; + asc1: serial@e100c00 { compatible = "lantiq,asc"; reg = <0xE100C00 0x400>; -- cgit v1.2.3 From 56a6cd3196c6617697b46c3861dfd06579ef43d2 Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Mon, 5 Nov 2018 15:39:06 +0800 Subject: dt-bindings: power: Introduce one property to present the battery internal resistance The internal resistance of a battery is not a constant in its life cycle, this varies over the age of the battery or temperature and so on. But we just want use one constant battery internal resistance to estimate the battery capacity. Thus this patch introduces one property to present the battery factory internal resistance for battery information. Signed-off-by: Baolin Wang Reviewed-by: Linus Walleij Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/supply/battery.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/battery.txt b/Documentation/devicetree/bindings/power/supply/battery.txt index f4d3b4a10b43..938d02785da2 100644 --- a/Documentation/devicetree/bindings/power/supply/battery.txt +++ b/Documentation/devicetree/bindings/power/supply/battery.txt @@ -22,6 +22,7 @@ Optional Properties: - charge-term-current-microamp: current for charge termination phase - constant-charge-current-max-microamp: maximum constant input current - constant-charge-voltage-max-microvolt: maximum constant input voltage + - factory-internal-resistance-micro-ohms: battery factory internal resistance Battery properties are named, where possible, for the corresponding elements in enum power_supply_property, defined in @@ -42,6 +43,7 @@ Example: charge-term-current-microamp = <128000>; constant-charge-current-max-microamp = <900000>; constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <250000>; }; charger: charger@11 { -- cgit v1.2.3 From 428527b3e6e1531dcde5c47f0553a9833e1054c8 Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Mon, 5 Nov 2018 15:39:08 +0800 Subject: dt-bindings: power: Introduce properties to present the battery OCV capacity table Some battery driver will use the open circuit voltage (OCV) value to look up the corresponding battery capacity percent in one certain degree Celsius. Thus this patch provides some battery properties to present the OCV table temperatures and OCV capacity table values. Suggested-by: Sebastian Reichel Signed-off-by: Baolin Wang Reviewed-by: Linus Walleij Reviewed-by: Rob Herring Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/power/supply/battery.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/battery.txt b/Documentation/devicetree/bindings/power/supply/battery.txt index 938d02785da2..89871ab8c704 100644 --- a/Documentation/devicetree/bindings/power/supply/battery.txt +++ b/Documentation/devicetree/bindings/power/supply/battery.txt @@ -23,6 +23,17 @@ Optional Properties: - constant-charge-current-max-microamp: maximum constant input current - constant-charge-voltage-max-microvolt: maximum constant input voltage - factory-internal-resistance-micro-ohms: battery factory internal resistance + - ocv-capacity-table-0: An array providing the open circuit voltage (OCV) + of the battery and corresponding battery capacity percent, which is used + to look up battery capacity according to current OCV value. And the open + circuit voltage unit is microvolt. + - ocv-capacity-table-1: Same as ocv-capacity-table-0 + ...... + - ocv-capacity-table-n: Same as ocv-capacity-table-0 + - ocv-capacity-celsius: An array containing the temperature in degree Celsius, + for each of the battery capacity lookup table. The first temperature value + specifies the OCV table 0, and the second temperature value specifies the + OCV table 1, and so on. Battery properties are named, where possible, for the corresponding elements in enum power_supply_property, defined in @@ -44,6 +55,10 @@ Example: constant-charge-current-max-microamp = <900000>; constant-charge-voltage-max-microvolt = <4200000>; factory-internal-resistance-micro-ohms = <250000>; + ocv-capacity-celsius = <(-10) 0 10>; + ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>, ...; + ocv-capacity-table-1 = <4200000 100>, <4185000 95>, <4113000 90>, ...; + ocv-capacity-table-2 = <4250000 100>, <4200000 95>, <4185000 90>, ...; }; charger: charger@11 { -- cgit v1.2.3 From 0d5f2e6e9c792d557a2a17c484b1a191c7cd9d6e Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Mon, 5 Nov 2018 15:39:10 +0800 Subject: dt-bindings: power: Add Spreadtrum SC27XX fuel gauge unit documentation This patch adds the binding documentation for Spreadtrum SC27XX series PMICs fuel gauge unit device, which is used to calculate the battery capacity. Signed-off-by: Baolin Wang Reviewed-by: Linus Walleij Reviewed-by: Rob Herring Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/power/supply/sc27xx-fg.txt | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt b/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt new file mode 100644 index 000000000000..98a24004131f --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt @@ -0,0 +1,52 @@ +Spreadtrum SC27XX PMICs Fuel Gauge Unit Power Supply Bindings + +Required properties: +- compatible: Should be one of the following: + "sprd,sc2720-fgu", + "sprd,sc2721-fgu", + "sprd,sc2723-fgu", + "sprd,sc2730-fgu", + "sprd,sc2731-fgu". +- reg: The address offset of fuel gauge unit. +- battery-detect-gpios: GPIO for battery detection. +- io-channels: Specify the IIO ADC channel to get temperature. +- io-channel-names: Should be "bat-temp". +- monitored-battery: Phandle of battery characteristics devicetree node. + See Documentation/devicetree/bindings/power/supply/battery.txt + +Example: + + bat: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <1900000>; + constant-charge-voltage-max-microvolt = <4350000>; + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>, + <4022000 85>, <3983000 80>, <3949000 75>, + <3917000 70>, <3889000 65>, <3864000 60>, + <3835000 55>, <3805000 50>, <3787000 45>, + <3777000 40>, <3773000 35>, <3770000 30>, + <3765000 25>, <3752000 20>, <3724000 15>, + <3680000 10>, <3605000 5>, <3400000 0>; + ...... + }; + + sc2731_pmic: pmic@0 { + compatible = "sprd,sc2731"; + reg = <0>; + spi-max-frequency = <26000000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + fgu@a00 { + compatible = "sprd,sc2731-fgu"; + reg = <0xa00>; + battery-detect-gpios = <&pmic_eic 9 GPIO_ACTIVE_HIGH>; + io-channels = <&pmic_adc 5>; + io-channel-names = "bat-temp"; + monitored-battery = <&bat>; + }; + }; -- cgit v1.2.3 From 6a1abe4cbca755253b52b7fa65e6a6f2b87561fb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 25 Oct 2018 15:53:37 +0100 Subject: dt-bindings: dmaengine: usb-dmac: Add binding for r8a77470 This patch adds usb high-speed dmac binding for r8a77470 (RZ/G1C) SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt index 1743017bd948..a1e7b8142715 100644 --- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt @@ -6,6 +6,7 @@ Required Properties: - "renesas,r8a7743-usb-dmac" (RZ/G1M) - "renesas,r8a7744-usb-dmac" (RZ/G1N) - "renesas,r8a7745-usb-dmac" (RZ/G1E) + - "renesas,r8a77470-usb-dmac" (RZ/G1C) - "renesas,r8a7790-usb-dmac" (R-Car H2) - "renesas,r8a7791-usb-dmac" (R-Car M2-W) - "renesas,r8a7793-usb-dmac" (R-Car M2-N) -- cgit v1.2.3 From 03bd40033d66820ea8777d094160becb8bb569c2 Mon Sep 17 00:00:00 2001 From: Martin Kelly Date: Thu, 25 Oct 2018 19:38:12 -0700 Subject: dt-bindings: iio: magn: add LSM9DS1 bindings Add DT binding documentation for the LSM9DS1 magnetometer. Signed-off-by: Martin Kelly Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/st-sensors.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt index 6f626f73417e..07f1767c7ee6 100644 --- a/Documentation/devicetree/bindings/iio/st-sensors.txt +++ b/Documentation/devicetree/bindings/iio/st-sensors.txt @@ -67,6 +67,7 @@ Magnetometers: - st,lsm303dlm-magn - st,lis3mdl-magn - st,lis2mdl +- st,lsm9ds1-magn Pressure sensors: - st,lps001wp-press -- cgit v1.2.3 From fdbd710b35f2d58a51575c764d191101d46d271a Mon Sep 17 00:00:00 2001 From: Charles-Antoine Couret Date: Sun, 28 Oct 2018 17:24:02 +0100 Subject: dt-bindings: iio: dac: Add ti,dac7311 device tree bindings in documentation Description how to invoke ti-dac7311 driver from device tree file. Signed-off-by: Charles-Antoine Couret Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/dac/ti,dac7311.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/dac/ti,dac7311.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/dac/ti,dac7311.txt b/Documentation/devicetree/bindings/iio/dac/ti,dac7311.txt new file mode 100644 index 000000000000..e5a507db5e01 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/ti,dac7311.txt @@ -0,0 +1,23 @@ +TI DAC7311 device tree bindings + +Required properties: +- compatible: must be set to: + * "ti,dac7311" + * "ti,dac6311" + * "ti,dac5311" +- reg: spi chip select number for the device +- vref-supply: The regulator supply for ADC reference voltage + +Optional properties: +- spi-max-frequency: Max SPI frequency to use + +Example: + + spi_master { + dac@0 { + compatible = "ti,dac7311"; + reg = <0>; /* CS0 */ + spi-max-frequency = <1000000>; + vref-supply = <&vdd_supply>; + }; + }; -- cgit v1.2.3 From 27be1f6408baa0ac629f3273433f61051357a60a Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 4 Nov 2018 00:10:23 +0100 Subject: dt-bindings: iio: adc: meson-saradc: add temperature sensor support The 32-bit Meson8 SoC can use the SAR ADC to read the chip temperature. This requires setting the correct TSC (temperature sensor coefficient), which is programmed into the eFuse during the manufacturing process. Meson8b and Meson8m2 are not supported yet because they have a 5-bit TSC and only the first four bits are stored inside the SAR ADC registers. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt index 54b823f3a453..325090e43ce6 100644 --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt @@ -22,6 +22,12 @@ Required properties: - vref-supply: the regulator supply for the ADC reference voltage - #io-channel-cells: must be 1, see ../iio-bindings.txt +Optional properties: +- nvmem-cells: phandle to the temperature_calib eFuse cells +- nvmem-cell-names: if present (to enable the temperature sensor + calibration) this must contain "temperature_calib" + + Example: saradc: adc@8680 { compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; -- cgit v1.2.3 From 54820b4a6627e87afc0425c8b4ce338d3dbdbb80 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Fri, 21 Jul 2017 12:08:59 +0200 Subject: dt-bindings: i3c: Document core bindings A new I3C subsystem has been added and a generic description has been created to represent the I3C bus and the devices connected on it. Document this generic representation. Cc: Rob Herring Signed-off-by: Boris Brezillon Reviewed-by: Rob Herring Acked-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/i3c/i3c.txt | 138 ++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/i3c.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i3c/i3c.txt b/Documentation/devicetree/bindings/i3c/i3c.txt new file mode 100644 index 000000000000..ab729a0a86ae --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/i3c.txt @@ -0,0 +1,138 @@ +Generic device tree bindings for I3C busses +=========================================== + +This document describes generic bindings that should be used to describe I3C +busses in a device tree. + +Required properties +------------------- + +- #address-cells - should be <3>. Read more about addresses below. +- #size-cells - should be <0>. +- compatible - name of the I3C master controller driving the I3C bus + +For other required properties e.g. to describe register sets, +clocks, etc. check the binding documentation of the specific driver. +The node describing an I3C bus should be named i3c-master. + +Optional properties +------------------- + +These properties may not be supported by all I3C master drivers. Each I3C +master bindings should specify which of them are supported. + +- i3c-scl-hz: frequency of the SCL signal used for I3C transfers. + When undefined the core sets it to 12.5MHz. + +- i2c-scl-hz: frequency of the SCL signal used for I2C transfers. + When undefined, the core looks at LVR (Legacy Virtual Register) + values of I2C devices described in the device tree to determine + the maximum I2C frequency. + +I2C devices +=========== + +Each I2C device connected to the bus should be described in a subnode. All +properties described in Documentation/devicetree/bindings/i2c/i2c.txt are +valid here, but several new properties have been added. + +New constraint on existing properties: +-------------------------------------- +- reg: contains 3 cells + + first cell : still encoding the I2C address + + + second cell: shall be 0 + + + third cell: shall encode the I3C LVR (Legacy Virtual Register) + bit[31:8]: unused/ignored + bit[7:5]: I2C device index. Possible values + * 0: I2C device has a 50 ns spike filter + * 1: I2C device does not have a 50 ns spike filter but supports high + frequency on SCL + * 2: I2C device does not have a 50 ns spike filter and is not tolerant + to high frequencies + * 3-7: reserved + + bit[4]: tell whether the device operates in FM (Fast Mode) or FM+ mode + * 0: FM+ mode + * 1: FM mode + + bit[3:0]: device type + * 0-15: reserved + +The I2C node unit-address should always match the first cell of the reg +property: @. + +I3C devices +=========== + +All I3C devices are supposed to support DAA (Dynamic Address Assignment), and +are thus discoverable. So, by default, I3C devices do not have to be described +in the device tree. +This being said, one might want to attach extra resources to these devices, +and those resources may have to be described in the device tree, which in turn +means we have to describe I3C devices. + +Another use case for describing an I3C device in the device tree is when this +I3C device has a static I2C address and we want to assign it a specific I3C +dynamic address before the DAA takes place (so that other devices on the bus +can't take this dynamic address). + +The I3C device should be names @,, +where device-type is describing the type of device connected on the bus +(gpio-controller, sensor, ...). + +Required properties +------------------- +- reg: contains 3 cells + + first cell : encodes the static I2C address. Should be 0 if the device does + not have one (0 is not a valid I2C address). + + + second and third cells: should encode the ProvisionalID. The second cell + contains the manufacturer ID left-shifted by 1. + The third cell contains ORing of the part ID + left-shifted by 16, the instance ID left-shifted + by 12 and the extra information. This encoding is + following the PID definition provided by the I3C + specification. + +Optional properties +------------------- +- assigned-address: dynamic address to be assigned to this device. This + property is only valid if the I3C device has a static + address (first cell of the reg property != 0). + + +Example: + + i3c-master@d040000 { + compatible = "cdns,i3c-master"; + clocks = <&coreclock>, <&i3csysclock>; + clock-names = "pclk", "sysclk"; + interrupts = <3 0>; + reg = <0x0d040000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + i2c-scl-hz = <100000>; + + /* I2C device. */ + nunchuk: nunchuk@52 { + compatible = "nintendo,nunchuk"; + reg = <0x52 0x0 0x10>; + }; + + /* I3C device with a static I2C address. */ + thermal_sensor: sensor@68,39200144004 { + reg = <0x68 0x392 0x144004>; + assigned-address = <0xa>; + }; + + /* + * I3C device without a static I2C address but requiring + * resources described in the DT. + */ + sensor@0,39200154004 { + reg = <0x0 0x392 0x154004>; + clocks = <&clock_provider 0>; + }; + }; -- cgit v1.2.3 From e0be6a68b5410f3b401eb9f191da6f83b06793f1 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 10 Nov 2018 21:01:26 +0100 Subject: mtd: partitions: Add RedBoot FIS DT bindings This adds device tree bindings for the RedBoot FIS partition format. Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Linus Walleij Signed-off-by: Boris Brezillon --- .../bindings/mtd/partitions/redboot-fis.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/partitions/redboot-fis.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/partitions/redboot-fis.txt b/Documentation/devicetree/bindings/mtd/partitions/redboot-fis.txt new file mode 100644 index 000000000000..fd0ebe4e3415 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/partitions/redboot-fis.txt @@ -0,0 +1,27 @@ +RedBoot FLASH Image System (FIS) Partitions +=========================================== + +The FLASH Image System (FIS) directory is a flash description +format closely associated with the RedBoot boot loader. + +It uses one single flash eraseblock in the flash to store an index of +all images in the flash. + +This block size will vary depending on flash but is typically +32 KB in size. + +Required properties: +- compatible : (required) must be "redboot-fis" +- fis-index-block : (required) a index to the eraseblock containing + the FIS directory on this device. On a flash memory with 32KB + eraseblocks, 0 means the first eraseblock at 0x00000000, 1 means the + second eraseblock at 0x00008000 and so on. + +Example: + +flash@0 { + partitions { + compatible = "redboot-fis"; + fis-index-block = <0>; + }; +}; -- cgit v1.2.3 From 2b80b98b722bc8f174275e1bcad2122bd9dacee2 Mon Sep 17 00:00:00 2001 From: Maxime Jourdan Date: Mon, 5 Nov 2018 11:45:07 +0100 Subject: dt-bindings: display: amlogic, meson-vpu: Add optional canvas provider node Allows using the new canvas provider module if present. Signed-off-by: Maxime Jourdan Reviewed-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/20181105104508.23090-2-mjourdan@baylibre.com --- Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt index 057b81335775..c65fd7a7467c 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt +++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt @@ -67,6 +67,8 @@ Required properties: Optional properties: - power-domains: Optional phandle to associated power domain as described in the file ../power/power_domain.txt +- amlogic,canvas: phandle to canvas provider node as described in the file + ../soc/amlogic/amlogic,canvas.txt Required nodes: -- cgit v1.2.3 From 5279e96ff8033500b6008be5925ae2d20f42c434 Mon Sep 17 00:00:00 2001 From: "Andrei.Stefanescu@microchip.com" Date: Tue, 13 Nov 2018 14:47:33 +0000 Subject: regulator: dt-bindings: add regulator-state-standby bindings For state-mem and state-disk regulators can have various parameters applied such as enabled/disabled, current mode, voltage etc. This patch adds documentation on how to set these parameters in the device tree for the standby state. Signed-off-by: Andrei Stefanescu Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/regulator.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index a7cd36877bfe..ca96f70bd2de 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt @@ -33,13 +33,16 @@ Optional properties: decreases of any level. This is useful for regulators with exponential voltage changes. - regulator-soft-start: Enable soft start so that voltage ramps slowly +- regulator-state-standby sub-root node for Standby mode + : equivalent with standby Linux sleep state, which provides energy savings + with a relatively quick transition back time. - regulator-state-mem sub-root node for Suspend-to-RAM mode : suspend to memory, the device goes to sleep, but all data stored in memory, only some external interrupt can wake the device. - regulator-state-disk sub-root node for Suspend-to-DISK mode : suspend to disk, this state operates similarly to Suspend-to-RAM, but includes a final step of writing memory contents to disk. -- regulator-state-[mem/disk] node has following common properties: +- regulator-state-[mem/disk/standby] node has following common properties: - regulator-on-in-suspend: regulator should be on in suspend state. - regulator-off-in-suspend: regulator should be off in suspend state. - regulator-suspend-min-microvolt: minimum voltage may be set in -- cgit v1.2.3 From aa66478aa538f839a96c836bba0bbc12ef2666f0 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Tue, 13 Nov 2018 11:22:23 +0100 Subject: spi: pxa2xx: dt-bindings: Add spi-slave property This is used to indicate that the chip attached to this controller is a SPI master. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring Acked-by: Pavel Machek Reviewed-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-pxa2xx.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt index 0335a9bd2e8a..89b2832283e3 100644 --- a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt +++ b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt @@ -11,6 +11,7 @@ Required properties: Optional properties: - cs-gpios: list of GPIO chip selects. See the SPI bus bindings, Documentation/devicetree/bindings/spi/spi-bus.txt +- spi-slave: Empty property indicating the SPI controller is used in slave mode. Child nodes represent devices on the SPI bus See ../spi/spi-bus.txt -- cgit v1.2.3 From 8ae13d0b0d4bb4af99bec8c50152f0c8f5cbcc06 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Tue, 13 Nov 2018 11:22:26 +0100 Subject: spi: pxa2xx: dt-bindings: Add ready GPIO signal This this is used to let the SPI master know that our FIFO is filled and we're ready to service a transfer. Only useful in slave mode. A signal like this is used by an embedded controller on a OLPC XO 1.75 machine, that happens to be a SPI master. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek Reviewed-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-pxa2xx.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt index 89b2832283e3..e30e0c2a4bce 100644 --- a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt +++ b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt @@ -12,6 +12,8 @@ Optional properties: - cs-gpios: list of GPIO chip selects. See the SPI bus bindings, Documentation/devicetree/bindings/spi/spi-bus.txt - spi-slave: Empty property indicating the SPI controller is used in slave mode. +- ready-gpios: GPIO used to signal a SPI master that the FIFO is filled + and we're ready to service a transfer. Only useful in slave mode. Child nodes represent devices on the SPI bus See ../spi/spi-bus.txt -- cgit v1.2.3 From 4ad26864df53b265976c4a3ae61b1e6cad92fe40 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Mon, 12 Nov 2018 18:42:31 +0200 Subject: dt-binding: spi: add NPCM PSPI controller documentation Added device tree binding documentation for Nuvoton BMC NPCM Peripheral SPI controller. Signed-off-by: Tomer Maimon Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/nuvoton,npcm-pspi.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt new file mode 100644 index 000000000000..99606b22e5c2 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt @@ -0,0 +1,35 @@ +Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver + +Nuvoton NPCM7xx SOC support two PSPI channels. + +Required properties: + - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC + - #address-cells : should be 1. see spi-bus.txt + - #size-cells : should be 0. see spi-bus.txt + - specifies physical base address and size of the register. + - interrupts : contain PSPI interrupt. + - clocks : phandle of PSPI reference clock. + - clock-names: Should be "clk_apb5". + - pinctrl-names : a pinctrl state named "default" must be defined. + - pinctrl-0 : phandle referencing pin configuration of the device. + - cs-gpios: Specifies the gpio pins to be used for chipselects. + See: Documentation/devicetree/bindings/spi/spi-bus.txt + +Optional properties: +- clock-frequency : Input clock frequency to the PSPI block in Hz. + Default is 25000000 Hz. + +Example: + +spi0: spi@f0200000 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0xf0200000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi1_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; +}; -- cgit v1.2.3 From d357b3134c9a7b1b78f5bfb2cd92423b91407cda Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Thu, 1 Nov 2018 15:20:02 +0000 Subject: dt-bindings: fsl: scu: update power domain binding Update the power domain binding with #power-domain-cells 1 format. The first cell can be a global SCU power domain and the 2nd cell the device ID. With this approach, we may remove all the sub power domain nodes from device tree which can relief the device tree a lot. Cc: Shawn Guo Cc: Sascha Hauer Reviewed-by: Rob Herring Reviewed-by: Ulf Hansson Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/freescale/fsl,scu.txt | 37 +++++----------------- 1 file changed, 8 insertions(+), 29 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 46d0af1f0872..c20f38e56544 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -58,19 +58,11 @@ This binding for the SCU power domain providers uses the generic power domain binding[2]. Required properties: -- compatible: Should be "fsl,scu-pd". -- #address-cells: Should be 1. -- #size-cells: Should be 0. - -Required properties for power domain sub nodes: -- #power-domain-cells: Must be 0. - -Optional Properties: -- reg: Resource ID of this power domain. - No exist means uncontrollable by user. +- compatible: Should be "fsl,imx8qxp-scu-pd". +- #power-domain-cells: Must be 1. Contains the Resource ID used by + SCU commands. See detailed Resource ID list from: - include/dt-bindings/power/imx-rsrc.h -- power-domains: phandle pointing to the parent power domain. + include/dt-bindings/firmware/imx/rsrc.h Clock bindings based on SCU Message Protocol ------------------------------------------------------------ @@ -152,22 +144,9 @@ firmware { ... }; - imx8qx-pm { - compatible = "fsl,scu-pd"; - #address-cells = <1>; - #size-cells = <0>; - - pd_dma: dma-power-domain { - #power-domain-cells = <0>; - - pd_dma_lpuart0: dma-lpuart0@57 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - ... - }; - ... + pd: imx8qx-pd { + compatible = "fsl,imx8qxp-scu-pd"; + #power-domain-cells = <1>; }; }; }; @@ -179,5 +158,5 @@ serial@5a060000 { clocks = <&clk IMX8QXP_UART0_CLK>, <&clk IMX8QXP_UART0_IPG_CLK>; clock-names = "per", "ipg"; - power-domains = <&pd_dma_lpuart0>; + power-domains = <&pd IMX_SC_R_UART_0>; }; -- cgit v1.2.3 From b59b94f76e7fa257e92d8e8b0c79755493356861 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 12 Nov 2018 14:11:25 -0800 Subject: dt-bindings: iio: vadc: Add unit address to ADC channel node in example The node has a reg property, therefore its name should include a unit address. Also change the name from 'usb_id_nopull' to 'adc-chan', which is the preferred name for ADC channel nodes. Include headers for constants used in the example. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt index b3c86f4ac7cd..c81993f8d8c3 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt @@ -140,6 +140,10 @@ VADC_GND_REF and VADC_VDD_VADC. Example: +#include +#include +/* ... */ + /* VADC node */ pmic_vadc: vadc@3100 { compatible = "qcom,spmi-vadc"; @@ -151,7 +155,7 @@ Example: io-channel-ranges; /* Channel node */ - usb_id_nopull { + adc-chan@VADC_LR_MUX10_USB_ID { reg = ; qcom,decimation = <512>; qcom,ratiometric; -- cgit v1.2.3 From e55b892e1848e220f5248583b99bdcde63fe8f05 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Oct 2018 13:35:13 +0100 Subject: dt-bindings: timer: meson6_timer: document all interrupts The meson6_timer IP block supports four timers - each of them has it's own interrupt line. Update the documentation to reflect that all four interrupts should be passed. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt index a092053f7902..dbdda92cffb7 100644 --- a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt +++ b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt @@ -4,12 +4,15 @@ Required properties: - compatible : should be "amlogic,meson6-timer" - reg : Specifies base physical address and size of the registers. -- interrupts : The interrupt of the first timer +- interrupts : The four interrupts, one for each timer event Example: timer@c1109940 { compatible = "amlogic,meson6-timer"; reg = <0xc1109940 0x14>; - interrupts = <0 10 1>; + interrupts = , + , + , + ; }; -- cgit v1.2.3 From be215b92703bd730fe3968ae8ee1de2e22ba5b1d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Oct 2018 13:35:14 +0100 Subject: dt-bindings: timer: meson6_timer: document the clock inputs The Meson Timer IP has two clock inputs: - pclk which is used as "system clock" timebase of Timer E - xtal which is used for the 1us, 10us, 100us and 1ms timebases of Timer A, B, C, D and E The IP block has four internal dividers (XTAL is running at 24MHz): - "xtal div 24" for 1us resolution - "xtal div 240" for 10us resolution - "xtal div 2400" for 100us resolution - "xtal div 24000" for 1ms resolution Suggested-by: Jianxin Pan Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt index dbdda92cffb7..a9da22bda912 100644 --- a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt +++ b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt @@ -5,6 +5,8 @@ Required properties: - compatible : should be "amlogic,meson6-timer" - reg : Specifies base physical address and size of the registers. - interrupts : The four interrupts, one for each timer event +- clocks : phandles to the pclk (system clock) and XTAL clocks +- clock-names : must contain "pclk" and "xtal" Example: @@ -15,4 +17,6 @@ timer@c1109940 { , , ; + clocks = <&xtal>, <&clk81>; + clock-names = "xtal", "pclk"; }; -- cgit v1.2.3 From 95d2f00657ad4c2c3eacd8a871a7aa022c3fe7d9 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 7 Nov 2018 23:18:41 +0530 Subject: dt-bindings: pinctrl: Add devicetree bindings for MT6797 SoC Pinctrl Add devicetree bindings for Mediatek MT6797 SoC Pin Controller. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pinctrl-mt6797.txt | 83 ++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt new file mode 100644 index 000000000000..bd83401e6179 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt @@ -0,0 +1,83 @@ +* MediaTek MT6797 Pin Controller + +The MediaTek's MT6797 Pin controller is used to control SoC pins. + +Required properties: +- compatible: Value should be one of the following. + "mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl. +- reg: Should contain address and size for gpio, iocfgl, iocfgb, + iocfgr and iocfgt register bases. +- reg-names: An array of strings describing the "reg" entries. Must + contain "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt". +- gpio-controller: Marks the device node as a gpio controller. +- #gpio-cells: Should be two. The first cell is the gpio pin number + and the second cell is used for optional parameters. + +Optional properties: +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be two. +- interrupts : The interrupt outputs from the controller. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices. + +Subnode format +A pinctrl node should contain at least one subnodes representing the +pinctrl groups available on the machine. Each subnode will list the +pins it needs, and how they should be configured, with regard to muxer +configuration, pullups, drive strength, input enable/disable and input schmitt. + + node { + pinmux = ; + GENERIC_PINCONFIG; + }; + +Required properties: +- pinmux: Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in dt-bindings/pinctrl/-pinfunc.h directly. + +Optional properties: +- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable, + bias-pull, bias-pull-down, input-enable, input-schmitt-enable, + input-schmitt-disable, output-enable output-low, output-high, + drive-strength, and slew-rate are valid. + + Valid arguments for 'slew-rate' are '0' for no slew rate controlled and + '1' for slower slew rate respectively. Valid arguments for 'drive-strength' + is limited, such as 2, 4, 8, 12, or 16 in mA. + + Some optional vendor properties as defined are valid to specify in a + pinconf subnode: + - mediatek,tdsel: An integer describing the steps for output level shifter + duty cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 15. + - mediatek,rdsel: An integer describing the steps for input level shifter + duty cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 63. + - mediatek,pull-up-adv: An integer describing the code R1R0 as 0, 1, 2 + or 3 for the advanced pull-up resistors. + - mediatek,pull-down-adv: An integer describing the code R1R0 as 0, 1, 2, + or 3 for the advanced pull-down resistors. + +Examples: + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6797-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x10002000 0 0x400>, + <0 0x10002400 0 0x400>, + <0 0x10002800 0 0x400>, + <0 0x10002C00 0 0x400>; + reg-names = "gpio", "iocfgl", "iocfgb", + "iocfgr", "iocfgt"; + gpio-controller; + #gpio-cells = <2>; + + uart1_pins_a: uart1 { + pins1 { + pinmux = , + ; + }; + }; + }; -- cgit v1.2.3 From fc381bb235a4ae1a2c7af1e55a90447553457a1a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 1 Nov 2018 22:32:55 +0100 Subject: drm/panel: Augment the TPO TPG110 bindings The TPO TPG110 bindings were using the DPI bindings (popular in the fbdev subsystem) but this misses the finer points learned in the DRM subsystem. We need to augment the bindings for proper DRM integration: the timings are expressed by the hardware, not put into the device tree. I.e. this hardware is self-describing and can report the resolutions and timings needed. It should not be described in the device tree. Further the device was incorrectly modeled with GPIO lines instead of an SPI child, even though the device was using SPI. No known deployments of the device using device tree exist, so it should be fine to augment the bindings. Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Linus Walleij Link: https://patchwork.freedesktop.org/patch/msgid/20181101213256.12097-1-linus.walleij@linaro.org --- .../bindings/display/panel/tpo,tpg110.txt | 81 ++++++++++++++-------- 1 file changed, 52 insertions(+), 29 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt b/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt index f5e3c6f2095a..40f3d7c713bb 100644 --- a/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt +++ b/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt @@ -1,47 +1,70 @@ TPO TPG110 Panel ================ -This binding builds on the DPI bindings, adding a few properties -as a superset of a DPI. See panel-dpi.txt for the required DPI -bindings. +This panel driver is a component that acts as an intermediary +between an RGB output and a variety of panels. The panel +driver is strapped up in electronics to the desired resolution +and other properties, and has a control interface over 3WIRE +SPI. By talking to the TPG110 over SPI, the strapped properties +can be discovered and the hardware is therefore mostly +self-describing. + + +--------+ +SPI -> | TPO | -> physical display +RGB -> | TPG110 | + +--------+ + +If some electrical strap or alternate resolution is desired, +this can be set up by taking software control of the display +over the SPI interface. The interface can also adjust +for properties of the display such as gamma correction and +certain electrical driving levels. + +The TPG110 does not know the physical dimensions of the panel +connected, so this needs to be specified in the device tree. + +It requires a GPIO line for control of its reset line. + +The serial protocol has line names that resemble I2C but the +protocol is not I2C but 3WIRE SPI. Required properties: -- compatible : "tpo,tpg110" +- compatible : one of: + "ste,nomadik-nhk15-display", "tpo,tpg110" + "tpo,tpg110" - grestb-gpios : panel reset GPIO -- scen-gpios : serial control enable GPIO -- scl-gpios : serial control clock line GPIO -- sda-gpios : serial control data line GPIO +- width-mm : see display/panel/panel-common.txt +- height-mm : see display/panel/panel-common.txt + +The device needs to be a child of an SPI bus, see +spi/spi-bus.txt. The SPI child must set the following +properties: +- spi-3wire +- spi-max-frequency = <3000000>; +as these are characteristics of this device. -Required nodes: -- Video port for DPI input, see panel-dpi.txt -- Panel timing for DPI setup, see panel-dpi.txt +The device node can contain one 'port' child node with one child +'endpoint' node, according to the bindings defined in +media/video-interfaces.txt. This node should describe panel's video bus. Example ------- -panel { - compatible = "tpo,tpg110", "panel-dpi"; - grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; - scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; +panel: display@0 { + compatible = "tpo,tpg110"; + reg = <0>; + spi-3wire; + /* 320 ns min period ~= 3 MHz */ + spi-max-frequency = <3000000>; + /* Width and height from data sheet */ + width-mm = <116>; + height-mm = <87>; + grestb-gpios = <&foo_gpio 5 GPIO_ACTIVE_LOW>; backlight = <&bl>; port { nomadik_clcd_panel: endpoint { - remote-endpoint = <&nomadik_clcd_pads>; + remote-endpoint = <&foo>; }; }; - - panel-timing { - clock-frequency = <33200000>; - hactive = <800>; - hback-porch = <216>; - hfront-porch = <40>; - hsync-len = <1>; - vactive = <480>; - vback-porch = <35>; - vfront-porch = <10>; - vsync-len = <1>; - }; }; -- cgit v1.2.3 From 8076de2244c6c1bf703c844134bfa13110b16349 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Date: Wed, 14 Nov 2018 13:16:42 +0100 Subject: ASoC: dt-bindings: add bindings for AK4118 transceiver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the bindings for AK4118 S/PDIF transceiver Signed-off-by: Clément Péron Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/ak4118.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/ak4118.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/ak4118.txt b/Documentation/devicetree/bindings/sound/ak4118.txt new file mode 100644 index 000000000000..6e11a2f7404c --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ak4118.txt @@ -0,0 +1,22 @@ +AK4118 S/PDIF transceiver + +This device supports I2C mode. + +Required properties: + +- compatible : "asahi-kasei,ak4118" +- reg : The I2C address of the device for I2C +- reset-gpios: A GPIO specifier for the reset pin +- irq-gpios: A GPIO specifier for the IRQ pin + +Example: + +&i2c { + ak4118: ak4118@13 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak4118"; + reg = <0x13>; + reset-gpios = <&gpio 0 GPIO_ACTIVE_LOW> + irq-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; +}; -- cgit v1.2.3 From fd7de6370cb62b147185834d60069568a21acacd Mon Sep 17 00:00:00 2001 From: Kirill Marinushkin Date: Thu, 15 Nov 2018 08:12:53 +0100 Subject: ASoC: Add documentation for pcm3060 property out-single-ended Output of pcm3060 codec may be configured as single-ended or differential Signed-off-by: Kirill Marinushkin Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/pcm3060.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/pcm3060.txt b/Documentation/devicetree/bindings/sound/pcm3060.txt index 90fcb8523099..97de66932d44 100644 --- a/Documentation/devicetree/bindings/sound/pcm3060.txt +++ b/Documentation/devicetree/bindings/sound/pcm3060.txt @@ -9,9 +9,15 @@ Required properties: - reg : the I2C address of the device for I2C, the chip select number for SPI. +Optional properties: + +- ti,out-single-ended: "true" if output is single-ended; + "false" or not specified if output is differential. + Examples: pcm3060: pcm3060@46 { compatible = "ti,pcm3060"; reg = <0x46>; + ti,out-single-ended = "true"; }; -- cgit v1.2.3 From 2c63a833e4500b341a62bf97e67488909ae12086 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 15 Nov 2018 14:46:53 -0800 Subject: bus: ti-sysc: Add mcasp optional clocks flag We have OPT_CLKS_NEEDED in legacy platform data, but it's missing from the ti-sysc driver for device tree based configuration. In order to pass OPT_CLKS_NEEDED quirk flag we need to update omap4 module data and add a new compatible for dra7 as the module layout is different from sysc_regbits_omap4_mcasp. Fixes: 70a65240efb1 ("bus: ti-sysc: Add register bits for interconnect target modules") Cc: Mark Rutland Cc: Rob Herring Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/bus/ti-sysc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt index 91dc2333af01..85a23f551f02 100644 --- a/Documentation/devicetree/bindings/bus/ti-sysc.txt +++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt @@ -35,6 +35,7 @@ Required standard properties: "ti,sysc-omap3-sham" "ti,sysc-omap-aes" "ti,sysc-mcasp" + "ti,sysc-dra7-mcasp" "ti,sysc-usb-host-fs" "ti,sysc-dra7-mcan" -- cgit v1.2.3 From 70db8b79e561a2965927a08ccdb06c796834a1b7 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Wed, 7 Nov 2018 15:33:31 +0000 Subject: dt-bindings: crypto: Mention clocks for mxs-dcp Explicit clock enabling is required on 6sll and 6ull so mention that standard clock bindings are used. Signed-off-by: Leonard Crestez Reviewed-by: Fabio Estevam Reviewed-by: Rob Herring Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/crypto/fsl-dcp.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/crypto/fsl-dcp.txt b/Documentation/devicetree/bindings/crypto/fsl-dcp.txt index 76a0b4e80e83..4e4d387e38a5 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-dcp.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-dcp.txt @@ -6,6 +6,8 @@ Required properties: - interrupts : Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ must be supplied, optionally Secure IRQ can be present, but is currently not implemented and not used. +- clocks : Clock reference (only required on some SOCs: 6ull and 6sll). +- clock-names : Must be "dcp". Example: -- cgit v1.2.3 From 74a257a0b5f0118b183a3be4b35530a30e30de48 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Wed, 7 Nov 2018 18:08:21 +0100 Subject: iio: light: Add device tree binding for vishay vcnl4035 Adding device tree binding for vcnl4035 and vendor prefix for Vishay Intertechnology Signed-off-by: Parthiban Nallathambi Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/light/vcnl4035.txt | 18 ++++++++++++++++++ Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 2 files changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/light/vcnl4035.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/light/vcnl4035.txt b/Documentation/devicetree/bindings/iio/light/vcnl4035.txt new file mode 100644 index 000000000000..c07c7f052556 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/light/vcnl4035.txt @@ -0,0 +1,18 @@ +VISHAY VCNL4035 - Ambient Light and proximity sensor + +Link to datasheet: https://www.vishay.com/docs/84251/vcnl4035x01.pdf + +Required properties: + + -compatible: should be "vishay,vcnl4035" + -reg: I2C address of the sensor, should be 0x60 + -interrupts: interrupt mapping for GPIO IRQ (level active low) + +Example: + +light-sensor@60 { + compatible = "vishay,vcnl4035"; + reg = <0x60>; + interrupt-parent = <&gpio4>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +}; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 2c3fc512e746..300b3afbc1b8 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -409,6 +409,7 @@ vamrs Vamrs Ltd. variscite Variscite Ltd. via VIA Technologies, Inc. virtio Virtual I/O Device Specification, developed by the OASIS consortium +vishay Vishay Intertechnology, Inc vitesse Vitesse Semiconductor Corporation vivante Vivante Corporation vocore VoCore Studio -- cgit v1.2.3 From 49b623732e4af1853186ecf859e2c371228074af Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 7 Nov 2018 16:45:21 +0100 Subject: iio: st-accel: add support for lis3de This commit add support for STMicroelectronics lis3de accelerometer. Datasheet for this device can be found here: https://www.st.com/resource/en/datasheet/lis3de.pdf Signed-off-by: Heiko Stuebner Acked-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/st-sensors.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt index 07f1767c7ee6..ddcb95509599 100644 --- a/Documentation/devicetree/bindings/iio/st-sensors.txt +++ b/Documentation/devicetree/bindings/iio/st-sensors.txt @@ -48,6 +48,7 @@ Accelerometers: - st,lis3l02dq - st,lis2dw12 - st,lis3dhh +- st,lis3de Gyroscopes: - st,l3g4200d-gyro -- cgit v1.2.3 From cad4d0a3d0ffe764d22432ef772e6c05e8ca21d3 Mon Sep 17 00:00:00 2001 From: Song Qiang Date: Thu, 8 Nov 2018 17:27:47 +0800 Subject: dt-bindings: Add PNI to the vendor prefixes Signed-off-by: Song Qiang Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 300b3afbc1b8..1c2cd460cc3d 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -297,6 +297,7 @@ pine64 Pine64 pixcir PIXCIR MICROELECTRONICS Co., Ltd plathome Plat'Home Co., Ltd. plda PLDA +pni PNI Sensor Corporation portwell Portwell Inc. poslab Poslab Technology Co., Ltd. powervr PowerVR (deprecated, use img) -- cgit v1.2.3 From 9a8d64fa97206eb68ec741b5c52436f32286b7fd Mon Sep 17 00:00:00 2001 From: Song Qiang Date: Thu, 8 Nov 2018 17:27:48 +0800 Subject: iio: magnetometer: Add DT support for PNI RM3100 Signed-off-by: Song Qiang Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- .../bindings/iio/magnetometer/pni,rm3100.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/magnetometer/pni,rm3100.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/magnetometer/pni,rm3100.txt b/Documentation/devicetree/bindings/iio/magnetometer/pni,rm3100.txt new file mode 100644 index 000000000000..497c932e9e39 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/magnetometer/pni,rm3100.txt @@ -0,0 +1,20 @@ +* PNI RM3100 3-axis magnetometer sensor + +Required properties: + +- compatible : should be "pni,rm3100" +- reg : the I2C address or SPI chip select number of the sensor. + +Optional properties: + +- interrupts: data ready (DRDY) from the chip. + The interrupts can be triggered on level high. + +Example: + +rm3100: rm3100@20 { + compatible = "pni,rm3100"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +}; -- cgit v1.2.3 From 1d6b36752bb31c4407ec8e995b361ffdc15fb86d Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Sun, 11 Nov 2018 15:15:36 +0100 Subject: dt-bindings: iio: imu: st_lsm6dsx: add support to i2c pullup resistors Signed-off-by: Lorenzo Bianconi Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt index 879322ad50fd..69d53d98d0f0 100644 --- a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt +++ b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt @@ -13,6 +13,7 @@ Required properties: Optional properties: - st,drdy-int-pin: the pin on the package that will be used to signal "data ready" (valid values: 1 or 2). +- st,pullups : enable/disable internal i2c controller pullup resistors. - drive-open-drain: the interrupt/data ready line will be configured as open drain, which is useful if several sensors share the same interrupt line. This is a boolean property. -- cgit v1.2.3 From f0001f587731603d2eccf5577ea74f12aa9a477c Mon Sep 17 00:00:00 2001 From: Alan Douglas Date: Mon, 12 Nov 2018 16:42:01 +0000 Subject: dt-bindings: phy: Document cadence Sierra PHY bindings Add DT binding documentation for Sierra PHY. The PHY supports a number of different protocols, including PCIe and USB. The PHY lanes may be configured as single or multi-lane links. Each link is treated as a separate sub-node. For example, if there are 4 lanes in total the first 2 might be configured as a multi-lane PCIe link while the other two are single lane USB links, and in this case there would be 3 sub-nodes. There are two resets for the PHY block (one for APB register access, one for the PHY link) and separate resets for each link. For multi-lane links, the reset corresponds to the reset line on the master lane, the resets on other lanes have no effect. Signed-off-by: Alan Douglas Signed-off-by: Rob Herring --- .../devicetree/bindings/phy/phy-cadence-sierra.txt | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt new file mode 100644 index 000000000000..6e1b47bfce43 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt @@ -0,0 +1,67 @@ +Cadence Sierra PHY +----------------------- + +Required properties: +- compatible: cdns,sierra-phy-t0 +- clocks: Must contain an entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must be "phy_clk" +- resets: Must contain an entry for each in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include "sierra_reset" and "sierra_apb". + "sierra_reset" must control the reset line to the PHY. + "sierra_apb" must control the reset line to the APB PHY + interface. +- reg: register range for the PHY. +- #address-cells: Must be 1 +- #size-cells: Must be 0 + +Optional properties: +- cdns,autoconf: A boolean property whose presence indicates that the + PHY registers will be configured by hardware. If not + present, all sub-node optional properties must be + provided. + +Sub-nodes: + Each group of PHY lanes with a single master lane should be represented as + a sub-node. Note that the actual configuration of each lane is determined by + hardware strapping, and must match the configuration specified here. + +Sub-node required properties: +- #phy-cells: Generic PHY binding; must be 0. +- reg: The master lane number. This is the lowest numbered lane + in the lane group. +- resets: Must contain one entry which controls the reset line for the + master lane of the sub-node. + See ../reset/reset.txt for details. + +Sub-node optional properties: +- cdns,num-lanes: Number of lanes in this group. From 1 to 4. The + group is made up of consecutive lanes. +- cdns,phy-type: Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on + configuration of lanes. + +Example: + pcie_phy4: pcie-phy@fd240000 { + compatible = "cdns,sierra-phy-t0"; + reg = <0x0 0xfd240000 0x0 0x40000>; + resets = <&phyrst 0>, <&phyrst 1>; + reset-names = "sierra_reset", "sierra_apb"; + clocks = <&phyclock>; + clock-names = "phy_clk"; + #address-cells = <1>; + #size-cells = <0>; + pcie0_phy0: pcie-phy@0 { + reg = <0>; + resets = <&phyrst 2>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + }; + pcie0_phy1: pcie-phy@2 { + reg = <2>; + resets = <&phyrst 4>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + }; -- cgit v1.2.3 From 570d54fe24634e87a48193dfc04a2486371cacea Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Wed, 7 Nov 2018 15:10:16 +0800 Subject: dt-bindings: rng: update bindings for MT7629 SoC This updates bindings for MT7629 RNG driver. Signed-off-by: Ryder Lee Acked-by: Sean Wang Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/rng/mtk-rng.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.txt b/Documentation/devicetree/bindings/rng/mtk-rng.txt index 366b99bff8cd..2bc89f133701 100644 --- a/Documentation/devicetree/bindings/rng/mtk-rng.txt +++ b/Documentation/devicetree/bindings/rng/mtk-rng.txt @@ -1,9 +1,10 @@ Device-Tree bindings for Mediatek random number generator -found in Mediatek SoC family +found in MediaTek SoC family Required properties: - compatible : Should be "mediatek,mt7622-rng", "mediatek,mt7623-rng" : for MT7622 + "mediatek,mt7629-rng", "mediatek,mt7623-rng" : for MT7629 "mediatek,mt7623-rng" : for MT7623 - clocks : list of clock specifiers, corresponding to entries in clock-names property; -- cgit v1.2.3 From 276aa6d38e619d2bd61fbac71388a4da680e7ed5 Mon Sep 17 00:00:00 2001 From: Cheng-Yi Chiang Date: Fri, 16 Nov 2018 10:12:43 +0800 Subject: ASoC: rt5663: Add documentation for power supply support rt5663 codec driver will support setting CPVDD and AVDD power supply from device tree. Signed-off-by: Cheng-Yi Chiang Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/rt5663.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/rt5663.txt b/Documentation/devicetree/bindings/sound/rt5663.txt index 23386446c63d..2a55e9133408 100644 --- a/Documentation/devicetree/bindings/sound/rt5663.txt +++ b/Documentation/devicetree/bindings/sound/rt5663.txt @@ -10,6 +10,10 @@ Required properties: - interrupts : The CODEC's interrupt output. +- avdd-supply: Power supply for AVDD, providing 1.8V. + +- cpvdd-supply: Power supply for CPVDD, providing 3.5V. + Optional properties: - "realtek,dc_offset_l_manual" @@ -51,4 +55,6 @@ rt5663: codec@12 { compatible = "realtek,rt5663"; reg = <0x12>; interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <&pp1800_a_alc5662>; + cpvdd-supply = <&pp3500_a_alc5662>; }; -- cgit v1.2.3 From 90c430d32c5fa08363b3db402df1b937901dd5b3 Mon Sep 17 00:00:00 2001 From: Stefan Popa Date: Tue, 13 Nov 2018 13:21:01 +0200 Subject: dt-bindings: iio: adc: Add common ADCs properties to a separate file There are several ADC drivers that depend on the same device tree bindings. Rather than continue to duplicate the properties, this patch adds a common adc binding document that can be referenced. For beginning, only two properties are documented. Signed-off-by: Stefan Popa Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/adc.txt | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/adc.txt b/Documentation/devicetree/bindings/iio/adc/adc.txt new file mode 100644 index 000000000000..5bbaa330a250 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adc.txt @@ -0,0 +1,23 @@ +Common ADCs properties + +Optional properties for child nodes: +- bipolar : Boolean, if set the channel is used in bipolar mode. +- diff-channels : Differential channels muxed for this ADC. The first value + specifies the positive input pin, the second value the negative + input pin. + +Example: + adc@0 { + compatible = "some,adc"; + ... + channel@0 { + bipolar; + diff-channels = <0 1>; + ... + }; + + channel@1 { + diff-channels = <2 3>; + ... + }; + }; -- cgit v1.2.3 From 9f84a1bdd38ad449a725efbe8b5773efdee463d5 Mon Sep 17 00:00:00 2001 From: Stefan Popa Date: Tue, 13 Nov 2018 13:22:18 +0200 Subject: dt-bindings: iio: adc: Add docs for ad7124 Add support for Analog Devices AD7124 4-channels and 8-channels ADC. Signed-off-by: Stefan Popa Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/adi,ad7124.txt | 75 ++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad7124.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.txt b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.txt new file mode 100644 index 000000000000..416273dce569 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.txt @@ -0,0 +1,75 @@ +Analog Devices AD7124 ADC device driver + +Required properties for the AD7124: + - compatible: Must be one of "adi,ad7124-4" or "adi,ad7124-8" + - reg: SPI chip select number for the device + - spi-max-frequency: Max SPI frequency to use + see: Documentation/devicetree/bindings/spi/spi-bus.txt + - clocks: phandle to the master clock (mclk) + see: Documentation/devicetree/bindings/clock/clock-bindings.txt + - clock-names: Must be "mclk". + - interrupts: IRQ line for the ADC + see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + + Required properties: + * #address-cells: Must be 1. + * #size-cells: Must be 0. + + Subnode(s) represent the external channels which are connected to the ADC. + Each subnode represents one channel and has the following properties: + Required properties: + * reg: The channel number. It can have up to 4 channels on ad7124-4 + and 8 channels on ad7124-8, numbered from 0 to 15. + * diff-channels: see: Documentation/devicetree/bindings/iio/adc/adc.txt + + Optional properties: + * bipolar: see: Documentation/devicetree/bindings/iio/adc/adc.txt + * adi,reference-select: Select the reference source to use when + converting on the the specific channel. Valid values are: + 0: REFIN1(+)/REFIN1(−). + 1: REFIN2(+)/REFIN2(−). + 3: AVDD + If this field is left empty, internal reference is selected. + +Optional properties: + - refin1-supply: refin1 supply can be used as reference for conversion. + - refin2-supply: refin2 supply can be used as reference for conversion. + - avdd-supply: avdd supply can be used as reference for conversion. + +Example: + adc@0 { + compatible = "adi,ad7124-4"; + reg = <0>; + spi-max-frequency = <5000000>; + interrupts = <25 2>; + interrupt-parent = <&gpio>; + refin1-supply = <&adc_vref>; + clocks = <&ad7124_mclk>; + clock-names = "mclk"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + diff-channels = <0 1>; + adi,reference-select = <0>; + }; + + channel@1 { + reg = <1>; + bipolar; + diff-channels = <2 3>; + adi,reference-select = <0>; + }; + + channel@2 { + reg = <2>; + diff-channels = <4 5>; + }; + + channel@3 { + reg = <3>; + diff-channels = <6 7>; + }; + }; -- cgit v1.2.3 From 8a49f9db47af69f736dc119c5dbd20227abd22ff Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 18 Nov 2018 22:23:53 +0100 Subject: dt-bindings: vendor-prefix: add prefix for IC Plus Corp. IC Plus Corp. has various Ethernet related products such as Ethernet transceivers, Ethernet controllers, Ethernet switches, etc. Signed-off-by: Martin Blumenstingl Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 4b1a2a8fcc16..cc6b2c0d3b49 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -170,6 +170,7 @@ holtek Holtek Semiconductor, Inc. hwacom HwaCom Systems Inc. i2se I2SE GmbH ibm International Business Machines (IBM) +icplus IC Plus Corp. idt Integrated Device Technologies, Inc. ifi Ingenieurburo Fur Ic-Technologie (I/F/I) ilitek ILI Technology Corporation (ILITEK) -- cgit v1.2.3 From fdc13a9effd5359ae00705708c8c846b1cb2b69c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 18 Nov 2018 22:23:54 +0100 Subject: dt-bindings: net: phy: add bindings for the IC Plus Corp. IP101A/G PHYs The IP101A and IP101G series both have various models. Depending on the board implementation we need a special property for the IP101GR (32-pin LQFP package) PHY: pin 21 ("RXER/INTR_32") outputs the "receive error" signal by default (LOW means "normal operation", HIGH means that there's either a decoding error of the received signal or that the PHY is receiving LPI). This pin can also be switched to INTR32 mode, where the interrupt signal is routed to this pin. The other PHYs don't need this special handling because they have more pins available so the interrupt function gets a dedicated pin. This adds two properties to either select the "receive error" or "interrupt" function of pin 21. Not specifying any function means that the default set by the bootloader is used. This is required because the IP101GR cannot be differentiated between other IP101 PHYs as the PHY identification registers on all of these is 0x02430c54. The IP101G (sold as die only, without package) may suffer from the same issue depending on how it's integrated into a multi chip package by another manufacturer. If only the RXER/INTR_32 pin is routed then the users of the die-only variant may also have to explicitly configure the mode of hte RXER/INTR_32 pin. This is the reason why no "is-ip101gr" property was added. I have no evidence though which would confirm this theory - so the binding itself is independent of that. Signed-off-by: Martin Blumenstingl Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- .../devicetree/bindings/net/icplus-ip101ag.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/icplus-ip101ag.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/icplus-ip101ag.txt b/Documentation/devicetree/bindings/net/icplus-ip101ag.txt new file mode 100644 index 000000000000..a784592bbb15 --- /dev/null +++ b/Documentation/devicetree/bindings/net/icplus-ip101ag.txt @@ -0,0 +1,19 @@ +IC Plus Corp. IP101A / IP101G Ethernet PHYs + +There are different models of the IP101G Ethernet PHY: +- IP101GR (32-pin QFN package) +- IP101G (die only, no package) +- IP101GA (48-pin LQFP package) + +There are different models of the IP101A Ethernet PHY (which is the +predecessor of the IP101G): +- IP101A (48-pin LQFP package) +- IP101AH (48-pin LQFP package) + +Optional properties for the IP101GR (32-pin QFN package): + +- icplus,select-rx-error: + pin 21 ("RXER/INTR_32") will output the receive error status. + interrupts are not routed outside the PHY in this mode. +- icplus,select-interrupt: + pin 21 ("RXER/INTR_32") will output the interrupt signal. -- cgit v1.2.3 From c43f666af0cc8e668575e83e3d528847448ae72e Mon Sep 17 00:00:00 2001 From: Benjamin Gaignard Date: Tue, 13 Nov 2018 10:51:40 +0100 Subject: dt-bindings: pinctrl: stm32: Document hwlocks properties Add hwlocks as optional property Signed-off-by: Benjamin Gaignard Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index ef4f2ff4a1aa..48df30a36b01 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -56,6 +56,7 @@ Optional properties: More details in Documentation/devicetree/bindings/gpio/gpio.txt. - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line used to select GPIOs as interrupts). + - hwlocks: reference to a phandle of a hardware spinlock provider node. Example 1: #include -- cgit v1.2.3 From a8d8ee437ea0bf21f840f33ca87f8e1641727aae Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 19 Nov 2018 00:56:16 +0300 Subject: regulator: Change regulator-coupled-max-spread property Redefine binding for regulator-coupled-max-spread property in a way that max-spread values are defined per regulator couple instead of defining single max-spread for the whole group of coupled regulators. With that change the following regulators coupling configuration will be possible: regA: regulatorA { regulator-coupled-with = <®B ®C>; regulator-coupled-max-spread = <100000 300000>; }; regB: regulatorB { regulator-coupled-with = <®A ®C>; regulator-coupled-max-spread = <100000 200000>; }; regC: regulatorC { regulator-coupled-with = <®A ®B>; regulator-coupled-max-spread = <300000 200000>; }; Note that the regulator-coupled-max-spread property does not have any users yet, hence it's okay to change the binding. Signed-off-by: Dmitry Osipenko Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/regulator.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index ca96f70bd2de..e3a7a7a0316b 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt @@ -79,8 +79,9 @@ Optional properties: - regulator-coupled-with: Regulators with which the regulator is coupled. The linkage is 2-way - all coupled regulators should be linked with each other. A regulator should not be coupled with its supplier. -- regulator-coupled-max-spread: Max spread between voltages of coupled regulators - in microvolts. +- regulator-coupled-max-spread: Array of maximum spread between voltages of + coupled regulators in microvolts, each value in the array relates to the + corresponding couple specified by the regulator-coupled-with property. Deprecated properties: - regulator-compatible: If a regulator chip contains multiple -- cgit v1.2.3 From ba54e3005de16c948165ef14f1f196f14830e4b9 Mon Sep 17 00:00:00 2001 From: Saravanan Sekar Date: Thu, 15 Nov 2018 13:47:46 +0100 Subject: dt-bindings: pinctrl: Add bindings for Actions Semi S700 SoC Add pinctrl and pio bindings for Actions Semi S700 SoC. Signed-off-by: Parthiban Nallathambi Signed-off-by: Saravanan Sekar Reviewed-by: Rob Herring Acked-by: Manivannan Sadhasivam Signed-off-by: Linus Walleij --- .../bindings/pinctrl/actions,s700-pinctrl.txt | 170 +++++++++++++++++++++ 1 file changed, 170 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt new file mode 100644 index 000000000000..d13ff82f8518 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt @@ -0,0 +1,170 @@ +Actions Semi S700 Pin Controller + +This binding describes the pin controller found in the S700 SoC. + +Required Properties: + +- compatible: Should be "actions,s700-pinctrl" +- reg: Should contain the register base address and size of + the pin controller. +- clocks: phandle of the clock feeding the pin controller +- gpio-controller: Marks the device node as a GPIO controller. +- gpio-ranges: Specifies the mapping between gpio controller and + pin-controller pins. +- #gpio-cells: Should be two. The first cell is the gpio pin number + and the second cell is used for optional parameters. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt. Shall be set to 2. The first cell + defines the interrupt number, the second encodes + the trigger flags described in + bindings/interrupt-controller/interrupts.txt +- interrupts: The interrupt outputs from the controller. There is one GPIO + interrupt per GPIO bank. The number of interrupts listed depends + on the number of GPIO banks on the SoC. The interrupts must be + ordered by bank, starting with bank 0. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +Pinmux functions are available only for the pin groups while pinconf +parameters are available for both pin groups and individual pins. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +Required Properties: + +- pins: An array of strings, each string containing the name of a pin. + These pins are used for selecting the pull control and schmitt + trigger parameters. The following are the list of pins + available: + + eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer, + eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk, + eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, + i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, + pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2, + ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp, + lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap, + lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, + lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, + lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, + dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, + sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, + sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx, + uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, + uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk, + i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1, + csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3, + sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2, + dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb, + dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0, + dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2, + dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3 + +- groups: An array of strings, each string containing the name of a pin + group. These pin groups are used for selecting the pinmux + functions. + rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp, + rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp, + rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp, + i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp, + i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, + ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, + dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp, + lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp, + dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp, + uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, + sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, + uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp, + i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp, + pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp, + nand_ceb2_mfp, nand_ceb3_mfp + + These pin groups are used for selecting the drive strength + parameters. + + sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv, + rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv, + smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv, + pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv, + dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv, + uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv, + sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv + +- function: An array of strings, each string containing the name of the + pinmux functions. These functions can only be selected by + the corresponding pin groups. The following are the list of + pinmux functions available: + + nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1, + uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, + pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0, + sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30, + clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0 + +Optional Properties: + +- bias-pull-down: No arguments. The specified pins should be configured as + pull down. +- bias-pull-up: No arguments. The specified pins should be configured as + pull up. +- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified + pins +- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified + pins +- drive-strength: Integer. Selects the drive strength for the specified + pins in mA. + Valid values are: + <2> + <4> + <8> + <12> + +Example: + + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s700-pinctrl"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + clocks = <&cmu CLK_GPIO>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 136>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + ; + + uart3-default: uart3-default { + pinmux { + groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp"; + function = "uart3"; + }; + pinconf { + groups = "uart3_all_drv"; + drive-strength = <2>; + }; + }; + }; -- cgit v1.2.3 From 757bd6d536deeed200926d1d47cfd1a6369e9af6 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Mon, 12 Nov 2018 09:45:06 +0800 Subject: dt-bindings: pinctrl: update bindings for MT7629 SoC This updates bindings for MT7629 pinctrl driver. Signed-off-by: Ryder Lee Reviewed-by: Sean Wang Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pinctrl-mt7622.txt | 131 +++++++++++++++++++++ 1 file changed, 131 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt index 3b695131c51b..7a7aca1ed705 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt @@ -3,6 +3,7 @@ Required properties for the root node: - compatible: Should be one of the following "mediatek,mt7622-pinctrl" for MT7622 SoC + "mediatek,mt7629-pinctrl" for MT7629 SoC - reg: offset and length of the pinctrl space - gpio-controller: Marks the device node as a GPIO controller. @@ -324,6 +325,136 @@ group. "uart4_2_rts_cts" "uart" 95, 96 "watchdog" "watchdog" 78 + +== Valid values for pins, function and groups on MT7629 == + + Pin #: Valid values for pins + ----------------------------- + PIN 0: "TOP_5G_CLK" + PIN 1: "TOP_5G_DATA" + PIN 2: "WF0_5G_HB0" + PIN 3: "WF0_5G_HB1" + PIN 4: "WF0_5G_HB2" + PIN 5: "WF0_5G_HB3" + PIN 6: "WF0_5G_HB4" + PIN 7: "WF0_5G_HB5" + PIN 8: "WF0_5G_HB6" + PIN 9: "XO_REQ" + PIN 10: "TOP_RST_N" + PIN 11: "SYS_WATCHDOG" + PIN 12: "EPHY_LED0_N_JTDO" + PIN 13: "EPHY_LED1_N_JTDI" + PIN 14: "EPHY_LED2_N_JTMS" + PIN 15: "EPHY_LED3_N_JTCLK" + PIN 16: "EPHY_LED4_N_JTRST_N" + PIN 17: "WF2G_LED_N" + PIN 18: "WF5G_LED_N" + PIN 19: "I2C_SDA" + PIN 20: "I2C_SCL" + PIN 21: "GPIO_9" + PIN 22: "GPIO_10" + PIN 23: "GPIO_11" + PIN 24: "GPIO_12" + PIN 25: "UART1_TXD" + PIN 26: "UART1_RXD" + PIN 27: "UART1_CTS" + PIN 28: "UART1_RTS" + PIN 29: "UART2_TXD" + PIN 30: "UART2_RXD" + PIN 31: "UART2_CTS" + PIN 32: "UART2_RTS" + PIN 33: "MDI_TP_P1" + PIN 34: "MDI_TN_P1" + PIN 35: "MDI_RP_P1" + PIN 36: "MDI_RN_P1" + PIN 37: "MDI_RP_P2" + PIN 38: "MDI_RN_P2" + PIN 39: "MDI_TP_P2" + PIN 40: "MDI_TN_P2" + PIN 41: "MDI_TP_P3" + PIN 42: "MDI_TN_P3" + PIN 43: "MDI_RP_P3" + PIN 44: "MDI_RN_P3" + PIN 45: "MDI_RP_P4" + PIN 46: "MDI_RN_P4" + PIN 47: "MDI_TP_P4" + PIN 48: "MDI_TN_P4" + PIN 49: "SMI_MDC" + PIN 50: "SMI_MDIO" + PIN 51: "PCIE_PERESET_N" + PIN 52: "PWM_0" + PIN 53: "GPIO_0" + PIN 54: "GPIO_1" + PIN 55: "GPIO_2" + PIN 56: "GPIO_3" + PIN 57: "GPIO_4" + PIN 58: "GPIO_5" + PIN 59: "GPIO_6" + PIN 60: "GPIO_7" + PIN 61: "GPIO_8" + PIN 62: "SPI_CLK" + PIN 63: "SPI_CS" + PIN 64: "SPI_MOSI" + PIN 65: "SPI_MISO" + PIN 66: "SPI_WP" + PIN 67: "SPI_HOLD" + PIN 68: "UART0_TXD" + PIN 69: "UART0_RXD" + PIN 70: "TOP_2G_CLK" + PIN 71: "TOP_2G_DATA" + PIN 72: "WF0_2G_HB0" + PIN 73: "WF0_2G_HB1" + PIN 74: "WF0_2G_HB2" + PIN 75: "WF0_2G_HB3" + PIN 76: "WF0_2G_HB4" + PIN 77: "WF0_2G_HB5" + PIN 78: "WF0_2G_HB6" + +Valid values for function are: + "eth", "i2c", "led", "flash", "pcie", "pwm", "spi", "uart", + "watchdog", "wifi" + +Valid values for groups are: + Valid value function pins (in pin#) + ---------------------------------------------------------------- + "mdc_mdio" "eth" 23, 24 + "i2c_0" "i2c" 19, 20 + "i2c_1" "i2c" 53, 54 + "ephy_leds" "led" 12, 13, 14, 15, 16, + 17, 18 + "ephy0_led" "led" 12 + "ephy1_led" "led" 13 + "ephy2_led" "led" 14 + "ephy3_led" "led" 15 + "ephy4_led" "led" 16 + "wf2g_led" "led" 17 + "wf5g_led" "led" 18 + "snfi" "flash" 62, 63, 64, 65, 66, 67 + "spi_nor" "flash" 62, 63, 64, 65, 66, 67 + "pcie_pereset" "pcie" 51 + "pcie_wake" "pcie" 55 + "pcie_clkreq" "pcie" 56 + "pwm_0" "pwm" 52 + "pwm_1" "pwm" 61 + "spi_0" "spi" 21, 22, 23, 24 + "spi_1" "spi" 62, 63, 64, 65 + "spi_wp" "spi" 66 + "spi_hold" "spi" 67 + "uart0_txd_rxd" "uart" 68, 69 + "uart1_0_txd_rxd" "uart" 25, 26 + "uart1_0_cts_rts" "uart" 27, 28 + "uart1_1_txd_rxd" "uart" 53, 54 + "uart1_1_cts_rts" "uart" 55, 56 + "uart2_0_txd_rxd" "uart" 29, 30 + "uart2_0_cts_rts" "uart" 31, 32 + "uart2_1_txd_rxd" "uart" 57, 58 + "uart2_1_cts_rts" "uart" 59, 60 + "watchdog" "watchdog" 11 + "wf0_2g" "wifi" 70, 71, 72, 73, 74, + 75, 76, 77, 78 + "wf0_5g" "wifi" 0, 1, 2, 3, 4, 5, 6, + 7, 8, 9, 10 + Example: pio: pinctrl@10211000 { -- cgit v1.2.3 From bebaa63f5c4070be025f29d182d2d43aa443b510 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 14 Nov 2018 09:58:36 +0530 Subject: dt-bindings: gpu: mali-utgard: Add compatible for A64 Mali Allwinner A64 has Mali-400MP2, so document the relevant compatible as "allwinner,sun50i-a64-mali" along with reset line. Signed-off-by: Jagan Teki Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 63cd91176a68..3f128e4f95c6 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -11,6 +11,7 @@ Required properties: + allwinner,sun4i-a10-mali + allwinner,sun7i-a20-mali + allwinner,sun8i-h3-mali + + allwinner,sun50i-a64-mali + allwinner,sun50i-h5-mali + amlogic,meson-gxbb-mali + amlogic,meson-gxl-mali @@ -73,6 +74,10 @@ to specify one more vendor-specific compatible, among: Required properties: * resets: phandle to the reset line for the GPU + - allwinner,sun50i-a64-mali + Required properties: + * resets: phandle to the reset line for the GPU + - allwinner,sun50i-h5-mali Required properties: * resets: phandle to the reset line for the GPU -- cgit v1.2.3 From e24b6b513e747727ee56b77ad46f04dff36cee53 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Mon, 8 Oct 2018 18:06:20 +0000 Subject: dt-bindings: imx6q-pcie: Add multi-pd bindings for imx6sx The PCIe and PCIE_PHY blocks are in different power domains on imx6sx and this needs to be described using multi-pd bindings. This was not required until now because the power-domain of the PCIe block (DISPLAY) was always on. Signed-off-by: Leonard Crestez [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index f37494d5a7be..d514c1f2365f 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -41,7 +41,9 @@ Optional properties: Additional required properties for imx6sx-pcie: - clock names: Must include the following additional entries: - "pcie_inbound_axi" -- power-domains: Must be set to a phandle pointing to the PCIE_PHY power domain +- power-domains: Must be set to phandles pointing to the DISPLAY and + PCIE_PHY power domains +- power-domain-names: Must be "pcie", "pcie_phy" Additional required properties for imx7d-pcie: - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain -- cgit v1.2.3 From 9e6d9c9b737326d880e52ebe5a845f4afde378ea Mon Sep 17 00:00:00 2001 From: Charles Keepax Date: Tue, 20 Nov 2018 14:16:28 +0000 Subject: regulator: lochnagar: Add initial binding documentation Lochnagar is an evaluation and development board for Cirrus Logic Smart CODEC and Amp devices. It allows the connection of most Cirrus Logic devices on mini-cards, as well as allowing connection of various application processor systems to provide a full evaluation platform. This driver supports the board controller chip on the Lochnagar board. Signed-off-by: Charles Keepax Signed-off-by: Mark Brown --- .../bindings/regulator/cirrus,lochnagar.txt | 82 ++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/cirrus,lochnagar.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/cirrus,lochnagar.txt b/Documentation/devicetree/bindings/regulator/cirrus,lochnagar.txt new file mode 100644 index 000000000000..91974e6ee251 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/cirrus,lochnagar.txt @@ -0,0 +1,82 @@ +Cirrus Logic Lochnagar Audio Development Board + +Lochnagar is an evaluation and development board for Cirrus Logic +Smart CODEC and Amp devices. It allows the connection of most Cirrus +Logic devices on mini-cards, as well as allowing connection of +various application processor systems to provide a full evaluation +platform. Audio system topology, clocking and power can all be +controlled through the Lochnagar, allowing the device under test +to be used in a variety of possible use cases. + +This binding document describes the binding for the regulator portion +of the driver. + +Also see these documents for generic binding information: + [1] Regulator: ../regulator/regulator.txt + +This binding must be part of the Lochnagar MFD binding: + [2] ../mfd/cirrus,lochnagar.txt + +Optional sub-nodes: + + - VDDCORE : Initialisation data for the VDDCORE regulator, which + supplies the CODECs digital core if it has no build regulator for that + purpose. + Required Properties: + - compatible : One of the following strings: + "cirrus,lochnagar2-vddcore" + - SYSVDD-supply: Primary power supply for the Lochnagar. + + - MICVDD : Initialisation data for the MICVDD regulator, which + supplies the CODECs MICVDD. + Required Properties: + - compatible : One of the following strings: + "cirrus,lochnagar2-micvdd" + - SYSVDD-supply: Primary power supply for the Lochnagar. + + - MIC1VDD, MIC2VDD : Initialisation data for the MICxVDD supplies. + Required Properties: + - compatible : One of the following strings: + "cirrus,lochnagar2-mic1vdd", "cirrus,lochnagar2-mic2vdd" + Optional Properties: + - cirrus,micbias-input : A property selecting which of the CODEC + minicard micbias outputs should be used, valid values are 1 - 4. + - MICBIAS1-supply, MICBIAS2-supply: Regulator supplies for the + MICxVDD outputs, supplying the digital microphones, normally + supplied from the attached CODEC. + + - VDD1V8 : Recommended fixed regulator for the VDD1V8 regulator, which supplies the + CODECs analog and 1.8V digital supplies. + Required Properties: + - compatible : Should be set to "regulator-fixed" + - regulator-min-microvolt : Should be set to 1.8V + - regulator-max-microvolt : Should be set to 1.8V + - regulator-boot-on + - regulator-always-on + - vin-supply : Should be set to same supply as SYSVDD + +Example: + +lochnagar { + lochnagar-micvdd: MICVDD { + compatible = "cirrus,lochnagar2-micvdd"; + + SYSVDD-supply = <&wallvdd>; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + lochnagar-vdd1v8: VDD1V8 { + compatible = "regulator-fixed"; + + regulator-name = "VDD1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + + vin-supply = <&wallvdd>; + }; +}; + -- cgit v1.2.3 From 806654a9667c6f60a65f1a4a4406082b5de51233 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 19 Nov 2018 11:02:45 +0000 Subject: Documentation: Use "while" instead of "whilst" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Whilst making an unrelated change to some Documentation, Linus sayeth: | Afaik, even in Britain, "whilst" is unusual and considered more | formal, and "while" is the common word. | | [...] | | Can we just admit that we work with computers, and we don't need to | use þe eald Englisc spelling of words that most of the world never | uses? dictionary.com refers to the word as "Chiefly British", which is probably an undesirable attribute for technical documentation. Replace all occurrences under Documentation/ with "while". Cc: David Howells Cc: Liam Girdwood Cc: Chris Wilson Cc: Michael Halcrow Cc: Jonathan Corbet Reported-by: Linus Torvalds Signed-off-by: Will Deacon Signed-off-by: Jonathan Corbet --- Documentation/devicetree/bindings/arm/idle-states.txt | 2 +- Documentation/devicetree/bindings/pci/host-generic-pci.txt | 2 +- Documentation/devicetree/bindings/serial/rs485.txt | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt index 2c73847499ab..8f0937db55c5 100644 --- a/Documentation/devicetree/bindings/arm/idle-states.txt +++ b/Documentation/devicetree/bindings/arm/idle-states.txt @@ -142,7 +142,7 @@ characterised by the following graph: The graph is split in two parts delimited by time 1ms on the X-axis. The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope -and denotes the energy costs incurred whilst entering and leaving the idle +and denotes the energy costs incurred while entering and leaving the idle state. The graph curve in the area delimited by X-axis values = {x | x > 1ms } has shallower slope and essentially represents the energy consumption of the idle diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt b/Documentation/devicetree/bindings/pci/host-generic-pci.txt index 3f1d3fca62bb..614b594f4e72 100644 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.txt @@ -56,7 +56,7 @@ For CAM, this 24-bit offset is: cfg_offset(bus, device, function, register) = bus << 16 | device << 11 | function << 8 | register -Whilst ECAM extends this by 4 bits to accommodate 4k of function space: +While ECAM extends this by 4 bits to accommodate 4k of function space: cfg_offset(bus, device, function, register) = bus << 20 | device << 15 | function << 12 | register diff --git a/Documentation/devicetree/bindings/serial/rs485.txt b/Documentation/devicetree/bindings/serial/rs485.txt index b7c29f74ebb2..b92592dff6dd 100644 --- a/Documentation/devicetree/bindings/serial/rs485.txt +++ b/Documentation/devicetree/bindings/serial/rs485.txt @@ -16,7 +16,7 @@ Optional properties: - linux,rs485-enabled-at-boot-time: empty property telling to enable the rs485 feature at boot time. It can be disabled later with proper ioctl. - rs485-rx-during-tx: empty property that enables the receiving of data even - whilst sending data. + while sending data. RS485 example for Atmel USART: usart0: serial@fff8c000 { -- cgit v1.2.3 From f6c2d6026afe2f1e611bdec270e1f42af0a42f06 Mon Sep 17 00:00:00 2001 From: Hiroyuki Yokoyama Date: Wed, 21 Nov 2018 01:06:43 +0000 Subject: ASoC: rsnd: Add device tree support for r8a77995 Simply document new compat strings. There appears to be no need for a driver updates. Signed-off-by: Hiroyuki Yokoyama Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index 453e8ec2ac78..47dc8190f0a7 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -277,6 +277,7 @@ Required properties: - "renesas,rcar_sound-r8a7796" (R-Car M3-W) - "renesas,rcar_sound-r8a77965" (R-Car M3-N) - "renesas,rcar_sound-r8a77990" (R-Car E3) + - "renesas,rcar_sound-r8a77995" (R-Car D3) - reg : Should contain the register physical address. required register is SRU/ADG/SSI if generation1 -- cgit v1.2.3 From 8cc77e014917c65f05a61503bf67d8a2daa0ed90 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 21 Nov 2018 23:44:47 +0800 Subject: Documentation: ARM: sunxi: Add Allwinner SoC T3. Add Allwinner SoC T3 document and fix format. Signed-off-by: Hao Zhang Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index e4beec3d9ad3..94b9c12df96d 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -14,7 +14,8 @@ using one of the following compatible strings: allwinner,sun8i-a83t allwinner,sun8i-h2-plus allwinner,sun8i-h3 - allwinner-sun8i-r40 + allwinner,sun8i-r40 + allwinner,sun8i-t3 allwinner,sun8i-v3s allwinner,sun9i-a80 allwinner,sun50i-a64 -- cgit v1.2.3 From 73852e56827f5cb5db9d6e8dd8191fc2f2e8f424 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 19 Nov 2018 14:34:02 +0200 Subject: rtc: dt-binding: abx80x: fix resistance scale The abracon,tc-resistor property value is in kOhm. Signed-off-by: Baruch Siach Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/abracon,abx80x.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt b/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt index be789685a1c2..18b892d010d8 100644 --- a/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt +++ b/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt @@ -27,4 +27,4 @@ and valid to enable charging: - "abracon,tc-diode": should be "standard" (0.6V) or "schottky" (0.3V) - "abracon,tc-resistor": should be <0>, <3>, <6> or <11>. 0 disables the output - resistor, the other values are in ohm. + resistor, the other values are in kOhm. -- cgit v1.2.3 From 94693b7b83c0a326965d4e59cf7767b253803712 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Thu, 15 Nov 2018 11:15:28 -0500 Subject: dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO Add device tree binding documentation and header file for Renesas R7S9210 (RZ/A2) SoCs. Signed-off-by: Chris Brandt Reviewed-by: Rob Herring Reviewed-by: Jacopo Mondi Signed-off-by: Geert Uytterhoeven --- .../bindings/pinctrl/renesas,rza2-pinctrl.txt | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt new file mode 100644 index 000000000000..a63ccd476cda --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt @@ -0,0 +1,87 @@ +Renesas RZ/A2 combined Pin and GPIO controller + +The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller. +Pin multiplexing and GPIO configuration is performed on a per-pin basis. +Each port features up to 8 pins, each of them configurable for GPIO +function (port mode) or in alternate function mode. +Up to 8 different alternate function modes exist for each single pin. + +Pin controller node +------------------- + +Required properties: + - compatible: shall be: + - "renesas,r7s9210-pinctrl": for RZ/A2M + - reg + Address base and length of the memory area where the pin controller + hardware is mapped to. + - gpio-controller + This pin controller also controls pins as GPIO + - #gpio-cells + Must be 2 + - gpio-ranges + Expresses the total number of GPIO ports/pins in this SoC + +Example: Pin controller node for RZ/A2M SoC (r7s9210) + + pinctrl: pin-controller@fcffe000 { + compatible = "renesas,r7s9210-pinctrl"; + reg = <0xfcffe000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 176>; + }; + +Sub-nodes +--------- + +The child nodes of the pin controller designate pins to be used for +specific peripheral functions or as GPIO. + +- Pin multiplexing sub-nodes: + A pin multiplexing sub-node describes how to configure a set of + (or a single) pin in some desired alternate function mode. + The values for the pinmux properties are a combination of port name, pin + number and the desired function index. Use the RZA2_PINMUX macro located + in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these. + For assigning GPIO pins, use the macro RZA2_PIN also in r7s9210-pinctrl.h + to express the desired port pin. + + Required properties: + - pinmux: + integer array representing pin number and pin multiplexing configuration. + When a pin has to be configured in alternate function mode, use this + property to identify the pin by its global index, and provide its + alternate function configuration number along with it. + When multiple pins are required to be configured as part of the same + alternate function they shall be specified as members of the same + argument list of a single "pinmux" property. + Helper macros to ease assembling the pin index from its position + (port where it sits on and pin number) and alternate function identifier + are provided by the pin controller header file at: + + Integers values in "pinmux" argument list are assembled as: + ((PORT * 8 + PIN) | MUX_FUNC << 16) + + Example: Board specific pins configuration + + &pinctrl { + /* Serial Console */ + scif4_pins: serial4 { + pinmux = , /* TxD4 */ + ; /* RxD4 */ + }; + }; + + Example: Assigning a GPIO: + + leds { + status = "okay"; + compatible = "gpio-leds"; + + led0 { + /* P6_0 */ + gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>; + }; + }; -- cgit v1.2.3 From d959c40f370e9c072a575db08415c7e258796424 Mon Sep 17 00:00:00 2001 From: Yong Deng Date: Tue, 30 Oct 2018 04:12:23 -0400 Subject: media: dt-bindings: media: Add Allwinner V3s Camera Sensor Interface (CSI) Add binding documentation for Allwinner V3s CSI. Acked-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Yong Deng Reviewed-by: Laurent Pinchart Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/sun6i-csi.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/sun6i-csi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt new file mode 100644 index 000000000000..443e18c181b3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt @@ -0,0 +1,56 @@ +Allwinner V3s Camera Sensor Interface +------------------------------------- + +Allwinner V3s SoC features a CSI module(CSI1) with parallel interface. + +Required properties: + - compatible: value must be "allwinner,sun8i-v3s-csi" + - reg: base address and size of the memory-mapped region. + - interrupts: interrupt associated to this IP + - clocks: phandles to the clocks feeding the CSI + * bus: the CSI interface clock + * mod: the CSI module clock + * ram: the CSI DRAM clock + - clock-names: the clock names mentioned above + - resets: phandles to the reset line driving the CSI + +The CSI node should contain one 'port' child node with one child 'endpoint' +node, according to the bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Endpoint node properties for CSI +--------------------------------- +See the video-interfaces.txt for a detailed description of these properties. +- remote-endpoint : (required) a phandle to the bus receiver's endpoint + node +- bus-width: : (required) must be 8, 10, 12 or 16 +- pclk-sample : (optional) (default: sample on falling edge) +- hsync-active : (required; parallel-only) +- vsync-active : (required; parallel-only) + +Example: + +csi1: csi@1cb4000 { + compatible = "allwinner,sun8i-v3s-csi"; + reg = <0x01cb4000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + + port { + /* Parallel bus endpoint */ + csi1_ep: endpoint { + remote-endpoint = <&adv7611_ep>; + bus-width = <16>; + + /* If hsync-active/vsync-active are missing, + embedded BT.656 sync is used */ + hsync-active = <0>; /* Active low */ + vsync-active = <0>; /* Active low */ + pclk-sample = <1>; /* Rising */ + }; + }; +}; -- cgit v1.2.3 From b7eadaa3a02a38cfbfcc8603366d426043f159d5 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 14 Nov 2018 09:59:31 -0500 Subject: media: dt-bindings: media: sun6i: Add A31 and H3 compatibles The H3 has a slightly different CSI controller (no BT656, no CCI) which looks a lot like the original A31 controller. Add a compatible for the A31, and more specific compatible the for the H3 to be used in combination for the A31. Reviewed-by: Rob Herring Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/sun6i-csi.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt index 443e18c181b3..d4ab34f2240c 100644 --- a/Documentation/devicetree/bindings/media/sun6i-csi.txt +++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt @@ -4,7 +4,10 @@ Allwinner V3s Camera Sensor Interface Allwinner V3s SoC features a CSI module(CSI1) with parallel interface. Required properties: - - compatible: value must be "allwinner,sun8i-v3s-csi" + - compatible: value must be one of: + * "allwinner,sun6i-a31-csi" + * "allwinner,sun8i-h3-csi", "allwinner,sun6i-a31-csi" + * "allwinner,sun8i-v3s-csi" - reg: base address and size of the memory-mapped region. - interrupts: interrupt associated to this IP - clocks: phandles to the clocks feeding the CSI -- cgit v1.2.3 From cc4e51b838605ba3f03522b24a1cdc8828e5a7fd Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 6 Nov 2018 05:54:22 -0500 Subject: media: dt-bindings: rcar-vin: Add R8A77990 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add compatible string for R-Car E3 R8A77990 to the list of SoCs supported by rcar-vin driver. Signed-off-by: Jacopo Mondi Reviewed-by: Rob Herring Reviewed-by: Simon Horman Reviewed-by: Laurent Pinchart Acked-by: Niklas Söderlund Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/rcar_vin.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt index d329a4e8ac58..7c878ca29f45 100644 --- a/Documentation/devicetree/bindings/media/rcar_vin.txt +++ b/Documentation/devicetree/bindings/media/rcar_vin.txt @@ -24,6 +24,7 @@ on Gen3 platforms to a CSI-2 receiver. - "renesas,vin-r8a7796" for the R8A7796 device - "renesas,vin-r8a77965" for the R8A77965 device - "renesas,vin-r8a77970" for the R8A77970 device + - "renesas,vin-r8a77990" for the R8A77990 device - "renesas,vin-r8a77995" for the R8A77995 device - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible device. -- cgit v1.2.3 From 72a8914ff0667f029bd80a51a14719e70a3c82a9 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 6 Nov 2018 05:54:24 -0500 Subject: media: dt-bindings: rcar-csi2: Add R8A77990 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add compatible string for R-Car E3 R8A77990 to the list of supported SoCs. Signed-off-by: Jacopo Mondi Reviewed-by: Rob Herring Reviewed-by: Simon Horman Reviewed-by: Laurent Pinchart Acked-by: Niklas Söderlund Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt b/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt index 2d385b65b275..282448911267 100644 --- a/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt +++ b/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt @@ -12,6 +12,7 @@ Mandatory properties - "renesas,r8a7796-csi2" for the R8A7796 device. - "renesas,r8a77965-csi2" for the R8A77965 device. - "renesas,r8a77970-csi2" for the R8A77970 device. + - "renesas,r8a77990-csi2" for the R8A77990 device. - reg: the register base and size for the device registers - interrupts: the interrupt for the device -- cgit v1.2.3 From fe5a2bbb6333e7dc9202eb6a1c574d356a528de6 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Wed, 17 Oct 2018 09:18:23 -0400 Subject: media: dt-bindings: media: Document bindings for venus firmware device Add devicetree binding documentation for firmware loader for video hardware running on qualcomm chip. Signed-off-by: Vikash Garodia Reviewed-by: Rob Herring Acked-by: Stanimir Varbanov Reviewed-by: Alexandre Courbot Tested-by: Alexandre Courbot Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/qcom,venus.txt | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/qcom,venus.txt b/Documentation/devicetree/bindings/media/qcom,venus.txt index 00d0d1bf7647..b602c4c025e7 100644 --- a/Documentation/devicetree/bindings/media/qcom,venus.txt +++ b/Documentation/devicetree/bindings/media/qcom,venus.txt @@ -53,7 +53,8 @@ * Subnodes The Venus video-codec node must contain two subnodes representing -video-decoder and video-encoder. +video-decoder and video-encoder, and one optional firmware subnode. +Firmware subnode is needed when the platform does not have TrustZone. Every of video-encoder or video-decoder subnode should have: @@ -79,6 +80,13 @@ Every of video-encoder or video-decoder subnode should have: power domain which is responsible for collapsing and restoring power to the subcore. +The firmware subnode must have: + +- iommus: + Usage: required + Value type: + Definition: A list of phandle and IOMMU specifier pairs. + * An Example video-codec@1d00000 { compatible = "qcom,msm8916-venus"; @@ -105,4 +113,8 @@ Every of video-encoder or video-decoder subnode should have: clock-names = "core"; power-domains = <&mmcc VENUS_CORE1_GDSC>; }; + + video-firmware { + iommus = <&apps_iommu 0x10b2 0x0>; + }; }; -- cgit v1.2.3 From aab2b5297668e86504d730bbc6c33f7b69023812 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 21 Sep 2018 19:08:27 +0100 Subject: dt-bindings: display: renesas: du: Document the r8a77470 bindings Document the RZ/G1C (r8a77470) SoC in R-Car DU bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart --- Documentation/devicetree/bindings/display/renesas,du.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt index 9de67be632d1..eaa34ef517a6 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.txt +++ b/Documentation/devicetree/bindings/display/renesas,du.txt @@ -5,6 +5,7 @@ Required Properties: - compatible: must be one of the following. - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU + - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU @@ -53,6 +54,7 @@ corresponding to each DU output. ----------------------------------------------------------------------------- R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - - R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - - + R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 - R8A7779 (R-Car H1) DPAD 0 DPAD 1 - - R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 - R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - - -- cgit v1.2.3 From 5eb08d995564c9f9d4818a84050f7716b73c86cc Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 21 Sep 2018 19:08:28 +0100 Subject: dt-bindings: display: renesas: du: Document the r8a7744 bindings Document the RZ/G1N (R8A7744) SoC in the R-Car DU bindings. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart --- Documentation/devicetree/bindings/display/renesas,du.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt index eaa34ef517a6..3c855d9f2719 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.txt +++ b/Documentation/devicetree/bindings/display/renesas,du.txt @@ -4,6 +4,7 @@ Required Properties: - compatible: must be one of the following. - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU + - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU @@ -53,6 +54,7 @@ corresponding to each DU output. Port0 Port1 Port2 Port3 ----------------------------------------------------------------------------- R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - - + R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - - R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - - R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 - R8A7779 (R-Car H1) DPAD 0 DPAD 1 - - -- cgit v1.2.3 From 828ff2adaac405a1a3a10ccf6b04e7ca3de59967 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 18 Oct 2018 02:56:18 +0300 Subject: dt-bindings: display: renesas: lvds: Document r8a77965 bindings The M3-N (r8a77965) includes one LVDS encoder. Extend the binding to support it. Signed-off-by: Laurent Pinchart Reviewed-by: Kieran Bingham --- Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt index 3aeb0ec06fd0..ba5469dd09f3 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt +++ b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt @@ -13,6 +13,7 @@ Required properties: - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders + - "renesas,r8a77965-lvds" for R8A77965 (R-Car M3-N) compatible LVDS encoders - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders - "renesas,r8a77980-lvds" for R8A77980 (R-Car V3H) compatible LVDS encoders - "renesas,r8a77990-lvds" for R8A77990 (R-Car E3) compatible LVDS encoders -- cgit v1.2.3 From 21dd30200e3d350fe420d23a2a00b17633a3d1a2 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 22 Nov 2018 18:23:18 +0800 Subject: ASoC: dt-bindings: sun50i-codec-analog: Add headphone amp regulator supply On the Allwinner A64 SoC, the audio codec has a built-in headphone amplifier. This amplifier has a power supply separate from the rest of the analog audio circuitry. Add a regulator supply property to handle this. Signed-off-by: Chen-Yu Tsai Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/sun50i-codec-analog.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/sun50i-codec-analog.txt b/Documentation/devicetree/bindings/sound/sun50i-codec-analog.txt index 4f8ad0e04d20..056a098495cc 100644 --- a/Documentation/devicetree/bindings/sound/sun50i-codec-analog.txt +++ b/Documentation/devicetree/bindings/sound/sun50i-codec-analog.txt @@ -4,9 +4,11 @@ Required properties: - compatible: must be one of the following compatibles: - "allwinner,sun50i-a64-codec-analog" - reg: must contain the registers location and length +- cpvdd-supply: Regulator supply for the headphone amplifier Example: codec_analog: codec-analog@1f015c0 { compatible = "allwinner,sun50i-a64-codec-analog"; reg = <0x01f015c0 0x4>; + cpvdd-supply = <®_eldo1>; }; -- cgit v1.2.3 From 8e84de031a11c4240f3654fd4c380542e358f5f6 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Thu, 22 Nov 2018 18:23:20 +0800 Subject: ASoC: dt-bindings: add regulator property to simple amplifier Amplifier may have associated regulator, so add a property for it. Signed-off-by: Vasily Khoruzhick Signed-off-by: Chen-Yu Tsai Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/simple-amplifier.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/simple-amplifier.txt b/Documentation/devicetree/bindings/sound/simple-amplifier.txt index 8647edae7af0..7182ac4f1e65 100644 --- a/Documentation/devicetree/bindings/sound/simple-amplifier.txt +++ b/Documentation/devicetree/bindings/sound/simple-amplifier.txt @@ -4,9 +4,14 @@ Required properties: - compatible : "dioo,dio2125" or "simple-audio-amplifier" - enable-gpios : the gpio connected to the enable pin of the simple amplifier +Optional properties: +- VCC-supply : power supply for the device, as covered + in Documentation/devicetree/bindings/regulator/regulator.txt + Example: amp: analog-amplifier { compatible = "simple-audio-amplifier"; + VCC-supply = <®ulator>; enable-gpios = <&gpio GPIOH_3 0>; }; -- cgit v1.2.3 From f94b0f7f9246013ac158ae3adf194c1bfa1d1847 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 22 Nov 2018 00:55:24 +0000 Subject: ASoC: simple-scu-card: tidyup "prefix" parsing on Doc simple-scu-card.c is supporting "prefix" which is used to avoid DAI naming conflict when CPU/Codec matching. But, sound card might have multi sub-devices, and each codec might need each prefix. Now, ASoC is supporting snd_soc_of_parse_node_prefix(), let's support it on audio-graph-scu-card, too. It is keeping existing DT style. It can't support each codec's prefix if sound card had multi sub-devices without this patch. Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/simple-scu-card.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/simple-scu-card.txt b/Documentation/devicetree/bindings/sound/simple-scu-card.txt index 32f8dbce5241..3a2f71616cda 100644 --- a/Documentation/devicetree/bindings/sound/simple-scu-card.txt +++ b/Documentation/devicetree/bindings/sound/simple-scu-card.txt @@ -75,7 +75,6 @@ sound { simple-audio-card,bitclock-master = <&dpcmcpu>; simple-audio-card,frame-master = <&dpcmcpu>; - simple-audio-card,prefix = "ak4642"; simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback", "ak4642 Playback", "DAI1 Playback"; @@ -88,6 +87,7 @@ sound { }; codec { + prefix = "ak4642"; sound-dai = <&ak4643>; clocks = <&audio_clock>; }; -- cgit v1.2.3 From 264d15035eac5e779788c435bafb5c8319ffed81 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 22 Nov 2018 00:55:54 +0000 Subject: ASoC: audio-graph-scu-card: tidyup "prefix" parsing on Doc audio-graph-scu-card.c is supporting "prefix" which is used to avoid DAI naming conflict when CPU/Codec matching. But, sound card might have multi sub-devices, and each codec might need each prefix. Now, ASoC is supporting snd_soc_of_parse_node_prefix(), let's support it on audio-graph-scu-card, too. It is keeping existing DT style. It can't support each codec's prefix if sound card had multi sub-devices without this patch. Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt b/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt index 441dd6f29df1..a3610888e121 100644 --- a/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt +++ b/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt @@ -77,7 +77,6 @@ Example 2. 2 CPU 1 Codec (Mixing) compatible = "audio-graph-scu-card"; label = "sound-card"; - prefix = "codec"; routing = "codec Playback", "DAI0 Playback", "codec Playback", "DAI1 Playback", "DAI0 Capture", "codec Capture"; @@ -90,6 +89,7 @@ Example 2. 2 CPU 1 Codec (Mixing) audio-codec { ... + audio-graph-card,prefix = "codec"; port { codec_endpoint0: endpoint { remote-endpoint = <&cpu_endpoint0>; -- cgit v1.2.3 From df976517733e34e9c12828357c19bafea5c90cf5 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 22 Nov 2018 00:56:41 +0000 Subject: ASoC: audio-graph-scu-card: tidyup "convert-rate/channels" parsing on Doc audio-graph-scu-card.c is supporting "convert-rate/channels" which is used for DPCM. But, sound card might have multi codecs, and each codec might need each convert-rate/channels. This patch supports each codec's convert-rate/channles support. top node convert-rate/channels will overwrite settings if exist. It can't support each codec's convert-rate/channels if sound card had multi codecs without this patch. Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt b/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt index a3610888e121..62d42768a00b 100644 --- a/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt +++ b/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt @@ -80,7 +80,6 @@ Example 2. 2 CPU 1 Codec (Mixing) routing = "codec Playback", "DAI0 Playback", "codec Playback", "DAI1 Playback", "DAI0 Capture", "codec Capture"; - convert-rate = <48000>; dais = <&cpu_port0 &cpu_port1>; @@ -90,6 +89,7 @@ Example 2. 2 CPU 1 Codec (Mixing) ... audio-graph-card,prefix = "codec"; + audio-graph-card,convert-rate = <48000>; port { codec_endpoint0: endpoint { remote-endpoint = <&cpu_endpoint0>; -- cgit v1.2.3 From 6c763077163d13901ed2d41a67c741a940b695ac Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Oct 2018 13:08:57 +0100 Subject: dt-bindings: clock: meson8b: use the registers from the HHI syscon The clock controller on Meson8/Meson8m2 and Meson8b is part of a register region called "HHI". This register area contains more functionality than just a clock controller: - the clock controller - some reset controller bits - temperature sensor calibration coefficient (only on Meson8b and Meson8m2 - one one out of five TSC bits is stored in the HHI registers) - HDMI controller The HHI register area may be accessed concurrently. Allow this by using a "system controller" as parent node. Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20181028120859.5735-2-martin.blumenstingl@googlemail.com --- .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt index b455c5aa9139..4d94091c1d2d 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt @@ -9,15 +9,13 @@ Required Properties: - "amlogic,meson8-clkc" for Meson8 (S802) SoCs - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs -- reg: it must be composed by two tuples: - 0) physical base address of the xtal register and length of memory - mapped region. - 1) physical base address of the clock controller and length of memory - mapped region. - - #clock-cells: should be 1. - #reset-cells: should be 1. +Parent node should have the following properties : +- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" +- reg: base address and size of the HHI system control register space. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be @@ -30,9 +28,8 @@ device tree sources). Example: Clock controller node: - clkc: clock-controller@c1104000 { + clkc: clock-controller { compatible = "amlogic,meson8b-clkc"; - reg = <0xc1108000 0x4>, <0xc1104000 0x460>; #clock-cells = <1>; #reset-cells = <1>; }; -- cgit v1.2.3 From eeea81474bc40402d8037e73ee1751db65f25176 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 12 Oct 2018 01:41:02 +0900 Subject: dt-bindings: dmaengine: add DT binding for UniPhier MIO DMAC The MIO DMAC (Media IO DMA Controller) is used in UniPhier LD4, Pro4, and sLD8 SoCs. Signed-off-by: Masahiro Yamada Reviewed-by: Rob Herring Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/uniphier-mio-dmac.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt b/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt new file mode 100644 index 000000000000..b12388dc7eac --- /dev/null +++ b/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt @@ -0,0 +1,25 @@ +UniPhier Media IO DMA controller + +This works as an external DMA engine for SD/eMMC controllers etc. +found in UniPhier LD4, Pro4, sLD8 SoCs. + +Required properties: +- compatible: should be "socionext,uniphier-mio-dmac". +- reg: offset and length of the register set for the device. +- interrupts: a list of interrupt specifiers associated with the DMA channels. +- clocks: a single clock specifier. +- #dma-cells: should be <1>. The single cell represents the channel index. + +Example: + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; + clocks = <&mio_clk 7>; + #dma-cells = <1>; + }; + +Note: +In the example above, "interrupts = <0 68 4>, <0 68 4>, ..." is not a typo. +The first two channels share a single interrupt line. -- cgit v1.2.3 From 9693f670895fe2b439f2c26c2c78e4bba671b1b2 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 15 Nov 2018 11:58:29 +0000 Subject: dmaengine: rcar-dmac: Document R8A774A1 bindings Renesas' RZ/G2M (R8A774A1) SoC has DMA controllers compatible with this driver, therefore document RZ/G2M specific bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Rob Herring Reviewed-by: Simon Horman Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt index a5a7c3f5a1e3..cdf32b2b77f9 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt @@ -1,6 +1,6 @@ * Renesas R-Car (RZ/G) DMA Controller Device Tree bindings -Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA +Renesas R-Car (Gen 2/3) and RZ/G SoCs have multiple multi-channel DMA controller instances named DMAC capable of serving multiple clients. Channels can be dedicated to specific clients or shared between a large number of clients. @@ -20,6 +20,7 @@ Required Properties: - "renesas,dmac-r8a7744" (RZ/G1N) - "renesas,dmac-r8a7745" (RZ/G1E) - "renesas,dmac-r8a77470" (RZ/G1C) + - "renesas,dmac-r8a774a1" (RZ/G2M) - "renesas,dmac-r8a7790" (R-Car H2) - "renesas,dmac-r8a7791" (R-Car M2-W) - "renesas,dmac-r8a7792" (R-Car V2H) -- cgit v1.2.3 From b9b4ed210380e51f5c5960dcbceedcc0bbe28408 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 15 Nov 2018 11:59:14 +0000 Subject: dt-bindings: dmaengine: usb-dmac: Add binding for r8a774a1 This patch adds binding for r8a774a1 (RZ/G2M). Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt index a1e7b8142715..5e2c7e84c43e 100644 --- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt @@ -7,6 +7,7 @@ Required Properties: - "renesas,r8a7744-usb-dmac" (RZ/G1N) - "renesas,r8a7745-usb-dmac" (RZ/G1E) - "renesas,r8a77470-usb-dmac" (RZ/G1C) + - "renesas,r8a774a1-usb-dmac" (RZ/G2M) - "renesas,r8a7790-usb-dmac" (R-Car H2) - "renesas,r8a7791-usb-dmac" (R-Car M2-W) - "renesas,r8a7793-usb-dmac" (R-Car M2-N) -- cgit v1.2.3 From 538098281ce884a51d2aa4ab445056a41741c6ad Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Sat, 17 Nov 2018 17:17:20 +0100 Subject: dt-bindings: dmaengine: dw-dmac: add protection control property This patch for the DesignWare AHB Central Direct Memory Access Controller adds the dma protection control property: "snps,dma-protection-control" as well as the properties specific values defines into a new include file: include/dt-bindings/dma/dw-dmac.h Note: The protection control signals are one-to-one mapped to the AHB HPROT[1:3] signals for this controller. The HPROT0 (Data Access) is always hardwired to 1. Reviewed-by: Andy Shevchenko Reviewed-by: Rob Herring Signed-off-by: Christian Lamparter Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/snps-dma.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt index 39e2b26be344..db757df7057d 100644 --- a/Documentation/devicetree/bindings/dma/snps-dma.txt +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt @@ -27,6 +27,10 @@ Optional properties: general purpose DMA channel allocator. False if not passed. - multi-block: Multi block transfers supported by hardware. Array property with one cell per channel. 0: not supported, 1 (default): supported. +- snps,dma-protection-control: AHB HPROT[3:1] protection setting. + The default value is 0 (for non-cacheable, non-buffered, + unprivileged data access). + Refer to include/dt-bindings/dma/dw-dmac.h for possible values. Example: -- cgit v1.2.3 From f71b3c99128bae93c1b4262fc4f639652bb04e1e Mon Sep 17 00:00:00 2001 From: Chris Coffey Date: Tue, 20 Nov 2018 14:17:12 +0000 Subject: dt-bindings: iio: potentiometer: Add Microchip MCP41xxx/42xxx This patch adds device tree documentation for the Microchip MCP41xxx/42xxx family of digital potentiometers. Signed-off-by: Chris Coffey Signed-off-by: Jonathan Cameron --- .../bindings/iio/potentiometer/mcp41010.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/potentiometer/mcp41010.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/potentiometer/mcp41010.txt b/Documentation/devicetree/bindings/iio/potentiometer/mcp41010.txt new file mode 100644 index 000000000000..566711b9950c --- /dev/null +++ b/Documentation/devicetree/bindings/iio/potentiometer/mcp41010.txt @@ -0,0 +1,28 @@ +* Microchip MCP41010/41050/41100/42010/42050/42100 Digital Potentiometer + +Datasheet publicly available at: +http://ww1.microchip.com/downloads/en/devicedoc/11195c.pdf + +The node for this driver must be a child node of a SPI controller, hence +all mandatory properties described in + + Documentation/devicetree/bindings/spi/spi-bus.txt + +must be specified. + +Required properties: + - compatible: Must be one of the following, depending on the + model: + "microchip,mcp41010" + "microchip,mcp41050" + "microchip,mcp41100" + "microchip,mcp42010" + "microchip,mcp42050" + "microchip,mcp42100" + +Example: +potentiometer@0 { + compatible = "microchip,mcp41010"; + reg = <0>; + spi-max-frequency = <500000>; +}; -- cgit v1.2.3 From bbeb6a6ded3bfa369d99160d9788c7a3fb2a52ae Mon Sep 17 00:00:00 2001 From: Mesih Kilinc Date: Sun, 25 Nov 2018 10:43:13 +0300 Subject: dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl Add compatible string for Allwinner suniv F1C100s SoC's pinctrl. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index 258a4648ab81..a7f713344867 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -29,6 +29,7 @@ Required properties: "allwinner,sun50i-h5-pinctrl" "allwinner,sun50i-h6-pinctrl" "allwinner,sun50i-h6-r-pinctrl" + "allwinner,suniv-f1c100s-pinctrl" "nextthing,gr8-pinctrl" - reg: Should contain the register physical address and length for the -- cgit v1.2.3 From 5455e156078bfcb72505f59b933c9ef726351e2b Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Wed, 7 Nov 2018 18:10:36 -0800 Subject: usb: dwc3: Add a property to disable USB2 LPM Add an option to disable USB2 LPM from host. There maybe cases where the user does not want to enable USB2 LPM (e.g. USB2 LPM is broken). Signed-off-by: Thinh Nguyen Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/dwc3.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 636630fb92d7..7e33e53e7c29 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -37,6 +37,7 @@ Optional properties: - phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy" or "usb3-phy". - resets: a single pair of phandle and reset specifier + - snps,usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable - snps,disable_scramble_quirk: true when SW should disable data scrambling. Only really useful for FPGA builds. -- cgit v1.2.3 From dd74b96c74806da7a0e8cc794328950a2a7cb833 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Wed, 14 Nov 2018 22:56:48 -0800 Subject: usb: dwc3: Add disabling of start_transfer failure quirk DWC_usb31 peripheral v1.70a-ea06 and prior needs a SW workaround for isoc START TRANSFER command failure. However, some affected versions may have RTL patches to fix this without a SW workaround. Add this quirk to disable the SW workaround when it is not needed. Synopsys STAR 9001202023: Wrong microframe number for isochronous IN endpoints. Signed-off-by: Thinh Nguyen Reviewed-by: Rob Herring Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 7e33e53e7c29..8e5265e9f658 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -39,6 +39,9 @@ Optional properties: - resets: a single pair of phandle and reset specifier - snps,usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable + - snps,dis-start-transfer-quirk: when set, disable isoc START TRANSFER command + failure SW work-around for DWC_usb31 version 1.70a-ea06 + and prior. - snps,disable_scramble_quirk: true when SW should disable data scrambling. Only really useful for FPGA builds. - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled -- cgit v1.2.3 From 89444dad60de0a94d87ee2a6a9d9b73122e86344 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 20 Nov 2018 13:45:21 +0800 Subject: dt-bindings: pinctrl: fix qcom-pmic-gpio for pms405 Rather than gpio1-gpio11 for pms405, there are 12 GPIOs for pms405. But gpio1, gpio9 and gpio10 are not available. Fix the bindings doc to make it correct for pms405. Fixes: ed80f6eb799a ("dt-bindings: pinctrl: qcom-pmic-gpio: Add pms405 support") Signed-off-by: Shawn Guo Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index ab4000eab07d..759aa1732e48 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -92,7 +92,7 @@ to specify in a pin configuration subnode: gpio1-gpio26 for pm8998 gpio1-gpio22 for pma8084 gpio1-gpio10 for pmi8994 - gpio1-gpio11 for pms405 + gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10) - function: Usage: required -- cgit v1.2.3 From 7c0d404fac4b9a7167002dfe0850781cbcd3a942 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 20 Nov 2018 11:17:09 +0000 Subject: gpio: dwapb: Correct the DT node name in the example The sub-nodes should not be called gpio-controller, but simply gpio. Signed-off-by: Phil Edworthy Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt index 7276b50c3506..839dd32ffe11 100644 --- a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt @@ -43,7 +43,7 @@ gpio: gpio@20000 { #address-cells = <1>; #size-cells = <0>; - porta: gpio-controller@0 { + porta: gpio@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; @@ -55,7 +55,7 @@ gpio: gpio@20000 { interrupts = <0>; }; - portb: gpio-controller@1 { + portb: gpio@1 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; -- cgit v1.2.3 From 7121779fec95ce106ed3a7948d265809bd4e849b Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 26 Nov 2018 01:17:01 +0000 Subject: ASoC: rsnd: tidyup for SSIU subnode commit da48a6eb82ea2 ("ASoC: rsnd: add SSIU BUSIF support for Document") updated Documentation for SSIU, but 1) we want to keep old/deprecated DMA description, 2) it is missing SSIU subnode properties. This patch tidyup these Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index 47dc8190f0a7..4d19d2bd6286 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -327,8 +327,13 @@ SSI subnode properties: - no-busif : BUSIF is not ussed when [mem -> SSI] via DMA case - dma : Should contain Audio DMAC entry - dma-names : SSI case "rx" (=playback), "tx" (=capture) + Deprecated: see SSIU subnode properties SSIU case "rxu" (=playback), "txu" (=capture) +SSIU subnode properties: +- dma : Should contain Audio DMAC entry +- dma-names : "rx" (=playback), "tx" (=capture) + SRC subnode properties: - dma : Should contain Audio DMAC entry - dma-names : "rx" (=playback), "tx" (=capture) -- cgit v1.2.3 From 4b5d90f408f82549b5d02f95e5892a5e1545c4b4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 19 Oct 2018 19:30:17 +0900 Subject: dt-bindings: uniphier: add bindings for UniPhier SoC family Document the list of SoCs and boards of UniPhier platform. Signed-off-by: Masahiro Yamada Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/socionext/uniphier.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/uniphier.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/socionext/uniphier.txt b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt new file mode 100644 index 000000000000..b3ed1033740e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt @@ -0,0 +1,47 @@ +Socionext UniPhier SoC family +----------------------------- + +Required properties in the root node: + - compatible: should contain board and SoC compatible strings + +SoC and board compatible strings: + (sorted chronologically) + + - LD4 SoC: "socionext,uniphier-ld4" + - Reference Board: "socionext,uniphier-ld4-ref" + + - Pro4 SoC: "socionext,uniphier-pro4" + - Reference Board: "socionext,uniphier-pro4-ref" + - Ace Board: "socionext,uniphier-pro4-ace" + - Sanji Board: "socionext,uniphier-pro4-sanji" + + - sLD8 SoC: "socionext,uniphier-sld8" + - Reference Board: "socionext,uniphier-sld8-ref" + + - PXs2 SoC: "socionext,uniphier-pxs2" + - Gentil Board: "socionext,uniphier-pxs2-gentil" + - Vodka Board: "socionext,uniphier-pxs2-vodka" + + - LD6b SoC: "socionext,uniphier-ld6b" + - Reference Board: "socionext,uniphier-ld6b-ref" + + - LD11 SoC: "socionext,uniphier-ld11" + - Reference Board: "socionext,uniphier-ld11-ref" + - Global Board: "socionext,uniphier-ld11-global" + + - LD20 SoC: "socionext,uniphier-ld20" + - Reference Board: "socionext,uniphier-ld20-ref" + - Global Board: "socionext,uniphier-ld20-global" + + - PXs3 SoC: "socionext,uniphier-pxs3" + - Reference Board: "socionext,uniphier-pxs3-ref" + +Example: + +/dts-v1/; + +/ { + compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20"; + + ... +}; -- cgit v1.2.3 From 1c36155a802b6192f3ad532da76a12ad7e2b8158 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 19 Oct 2018 19:30:18 +0900 Subject: dt-bindings: uniphier: move cache-uniphier.txt to vendor directory Now, the Socionext vendor directory is available at Documentation/devicetree/bindings/arm/socionext/ Move cache-uniphier.txt over to it. Signed-off-by: Masahiro Yamada Reviewed-by: Rob Herring --- .../bindings/arm/socionext/cache-uniphier.txt | 60 ++++++++++++++++++++++ .../bindings/arm/uniphier/cache-uniphier.txt | 60 ---------------------- 2 files changed, 60 insertions(+), 60 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt delete mode 100644 Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt new file mode 100644 index 000000000000..d27a646f48a9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt @@ -0,0 +1,60 @@ +UniPhier outer cache controller + +UniPhier SoCs are integrated with a full-custom outer cache controller system. +All of them have a level 2 cache controller, and some have a level 3 cache +controller as well. + +Required properties: +- compatible: should be "socionext,uniphier-system-cache" +- reg: offsets and lengths of the register sets for the device. It should + contain 3 regions: control register, revision register, operation register, + in this order. +- cache-unified: specifies the cache is a unified cache. +- cache-size: specifies the size in bytes of the cache +- cache-sets: specifies the number of associativity sets of the cache +- cache-line-size: specifies the line size in bytes +- cache-level: specifies the level in the cache hierarchy. The value should + be 2 for L2 cache, 3 for L3 cache, etc. + +Optional properties: +- next-level-cache: phandle to the next level cache if present. The next level + cache should be also compatible with "socionext,uniphier-system-cache". + +The L2 cache must exist to use the L3 cache; the cache hierarchy must be +indicated correctly with "next-level-cache" properties. + +Example 1 (system with L2): + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + cache-unified; + cache-size = <0x80000>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + +Example 2 (system with L2 and L3): + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, + <0x506c0000 0x400>; + cache-unified; + cache-size = <0x200000>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + l3: l3-cache@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, + <0x506c8000 0x400>; + cache-unified; + cache-size = <0x400000>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; diff --git a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt deleted file mode 100644 index d27a646f48a9..000000000000 --- a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt +++ /dev/null @@ -1,60 +0,0 @@ -UniPhier outer cache controller - -UniPhier SoCs are integrated with a full-custom outer cache controller system. -All of them have a level 2 cache controller, and some have a level 3 cache -controller as well. - -Required properties: -- compatible: should be "socionext,uniphier-system-cache" -- reg: offsets and lengths of the register sets for the device. It should - contain 3 regions: control register, revision register, operation register, - in this order. -- cache-unified: specifies the cache is a unified cache. -- cache-size: specifies the size in bytes of the cache -- cache-sets: specifies the number of associativity sets of the cache -- cache-line-size: specifies the line size in bytes -- cache-level: specifies the level in the cache hierarchy. The value should - be 2 for L2 cache, 3 for L3 cache, etc. - -Optional properties: -- next-level-cache: phandle to the next level cache if present. The next level - cache should be also compatible with "socionext,uniphier-system-cache". - -The L2 cache must exist to use the L3 cache; the cache hierarchy must be -indicated correctly with "next-level-cache" properties. - -Example 1 (system with L2): - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - cache-unified; - cache-size = <0x80000>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - -Example 2 (system with L2 and L3): - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, - <0x506c0000 0x400>; - cache-unified; - cache-size = <0x200000>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, - <0x506c8000 0x400>; - cache-unified; - cache-size = <0x400000>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; -- cgit v1.2.3 From a2c1c192656b701939b9028646b8a8bb90edd911 Mon Sep 17 00:00:00 2001 From: Richard Gong Date: Tue, 13 Nov 2018 12:13:59 -0600 Subject: dt-bindings, firmware: add Intel Stratix10 service layer binding Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong Signed-off-by: Alan Tull Reviewed-by: Rob Herring Acked-by: Moritz Fischer Signed-off-by: Greg Kroah-Hartman --- .../bindings/firmware/intel,stratix10-svc.txt | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt new file mode 100644 index 000000000000..1fa66065acc6 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt @@ -0,0 +1,57 @@ +Intel Service Layer Driver for Stratix10 SoC +============================================ +Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard +processor system (HPS) and Secure Device Manager (SDM). When the FPGA is +configured from HPS, there needs to be a way for HPS to notify SDM the +location and size of the configuration data. Then SDM will get the +configuration data from that location and perform the FPGA configuration. + +To meet the whole system security needs and support virtual machine requesting +communication with SDM, only the secure world of software (EL3, Exception +Layer 3) can interface with SDM. All software entities running on other +exception layers must channel through the EL3 software whenever it needs +service from SDM. + +Intel Stratix10 service layer driver, running at privileged exception level +(EL1, Exception Layer 1), interfaces with the service providers and provides +the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer +driver also manages secure monitor call (SMC) to communicate with secure monitor +code running in EL3. + +Required properties: +------------------- +The svc node has the following mandatory properties, must be located under +the firmware node. + +- compatible: "intel,stratix10-svc" +- method: smc or hvc + smc - Secure Monitor Call + hvc - Hypervisor Call +- memory-region: + phandle to the reserved memory node. See + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + for details + +Example: +------- + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x0 0x0 0x1000000>; + alignment = <0x1000>; + no-map; + }; + }; + + firmware { + svc { + compatible = "intel,stratix10-svc"; + method = "smc"; + memory-region = <&service_reserved>; + }; + }; -- cgit v1.2.3 From 59e328039f47356c63c43c8617aba29a3afcc109 Mon Sep 17 00:00:00 2001 From: Alan Tull Date: Tue, 13 Nov 2018 12:14:02 -0600 Subject: dt-bindings: fpga: add Stratix10 SoC FPGA manager binding Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager. Signed-off-by: Alan Tull Signed-off-by: Richard Gong Reviewed-by: Rob Herring Acked-by: Moritz Fischer Signed-off-by: Greg Kroah-Hartman --- .../bindings/fpga/intel-stratix10-soc-fpga-mgr.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt new file mode 100644 index 000000000000..6e03f79287fb --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt @@ -0,0 +1,17 @@ +Intel Stratix10 SoC FPGA Manager + +Required properties: +The fpga_mgr node has the following mandatory property, must be located under +firmware/svc node. + +- compatible : should contain "intel,stratix10-soc-fpga-mgr" + +Example: + + firmware { + svc { + fpga_mgr: fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; + }; + }; -- cgit v1.2.3 From a1880d38674b1b7e120a231151298b2eb530b645 Mon Sep 17 00:00:00 2001 From: Leilk Liu Date: Tue, 27 Nov 2018 10:29:50 +0800 Subject: spi: mediatek: Add bindings for mediatek MT7629 soc platform This patch adds a DT binding documentation for the MT7629 soc. Signed-off-by: Leilk Liu Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt index 7940940b43e6..69c356767cf8 100644 --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt +++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt @@ -6,6 +6,7 @@ Required properties: - mediatek,mt2712-spi: for mt2712 platforms - mediatek,mt6589-spi: for mt6589 platforms - mediatek,mt7622-spi: for mt7622 platforms + - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms - mediatek,mt8135-spi: for mt8135 platforms - mediatek,mt8173-spi: for mt8173 platforms - mediatek,mt8183-spi: for mt8183 platforms -- cgit v1.2.3 From 9d9aa7ec7baf62640cd4e1a869746b2356731e93 Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Mon, 19 Nov 2018 12:03:31 +0100 Subject: dt-bindings: i2c-stm32: SYSCFG Fast Mode Plus support for I2C STM32F7 Append optional bindings to update SYSCFG Fast Mode Plus bits if Fast Mode Plus speed is selected. Signed-off-by: Pierre-Yves MORDRET Reviewed-by: Rob Herring Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-stm32.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt index 3b5489966634..69240e189b01 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt @@ -26,6 +26,11 @@ Optional properties : - i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board (default: 10) I2C Timings are derived from these 2 values +- st,syscfg-fmp: Only for STM32F7, use to set Fast Mode Plus bit within SYSCFG + whether Fast Mode Plus speed is selected by slave. + 1st cell : phandle to syscfg + 2nd cell : register offset within SYSCFG + 3rd cell : register bitmask for FMP bit Example : @@ -53,4 +58,5 @@ Example : clocks = <&rcc 1 CLK_I2C1>; pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>; pinctrl-names = "default"; + st,syscfg-fmp = <&syscfg 0x4 0x1>; }; -- cgit v1.2.3 From fca34b910ddc556c51294d58287f7c33863dddef Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 21 Nov 2018 13:09:27 +0100 Subject: i2c: sh_mobile: document support for r8a77990 (R-Car E3) Document support for the IIC code for the r8a77990 (R-Car E3). It is not considered compatible with existing fallback bindings due to the documented absence of automatic transmission registers. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt index d81b62643655..bc876b71d1e4 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt @@ -16,6 +16,7 @@ Required properties: - "renesas,iic-r8a7795" (R-Car H3) - "renesas,iic-r8a7796" (R-Car M3-W) - "renesas,iic-r8a77965" (R-Car M3-N) + - "renesas,iic-r8a77990" (R-Car E3) - "renesas,iic-sh73a0" (SH-Mobile AG5) - "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1 compatible device) @@ -28,7 +29,13 @@ Required properties: the platform first followed by the generic R-Car version. - renesas,rmobile-iic must always follow. + When compatible with "renesas,rmobile-iic" it should + be the last compatibility string listed. + + The r8a77990 (R-Car E3) controller is not + considered compatible with "renesas,rcar-gen3-iic" + or "renesas,rmobile-iic" due to the absence of + automatic transmission registers. - reg : address start and address range size of device - interrupts : interrupt of device -- cgit v1.2.3 From 34e8b809bf136c0554ba1131c6671ae6339543e0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 23 Nov 2018 13:18:37 +0100 Subject: dt-bindings: thermal: tegra-bpmp: Add Tegra194 support The thermal controller implementation on Tegra194 is very similar to the implementation on Tegra186. Add a compatible string for the new generation. Signed-off-by: Thierry Reding --- .../devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt index 276387dd6815..e17c07be270b 100644 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt @@ -15,7 +15,8 @@ Required properties: - compatible: Array of strings. One of: - - "nvidia,tegra186-bpmp-thermal". + - "nvidia,tegra186-bpmp-thermal" + - "nvidia,tegra194-bpmp-thermal" - #thermal-sensor-cells: Cell for sensor index. Single-cell integer. Must be <1>. -- cgit v1.2.3 From e431c92188a9b76c16707302a9fe848a70982c13 Mon Sep 17 00:00:00 2001 From: Amit Nischal Date: Sun, 25 Nov 2018 10:06:07 +0530 Subject: dt-bindings: clock: Introduce QCOM Graphics clock bindings Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SDM845 SoCs. Signed-off-by: Amit Nischal Reviewed-by: Rob Herring [sboyd@kernel.org: Add input clocks property] Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,gpucc.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt new file mode 100644 index 000000000000..9d0358cc08b4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -0,0 +1,22 @@ +Qualcomm Graphics Clock & Reset Controller Binding +-------------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,sdm845-gpucc" +- reg : shall contain base register location and length +- #clock-cells : from common clock binding, shall contain 1 +- #reset-cells : from common reset binding, shall contain 1 +- #power-domain-cells : from generic power domain binding, shall contain 1 +- clocks : shall contain the XO clock +- clock-names : shall be "xo" + +Example: + gpucc: clock-controller@5090000 { + compatible = "qcom,sdm845-gpucc"; + reg = <0x5090000 0x9000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; -- cgit v1.2.3 From a3641b30c19b93b1298028a7210b55145e70056c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Nov 2018 15:41:40 +0200 Subject: ASoC: davinci-mcasp: Document dismod optional property The dismod property can be used to specify the drive on level of inactive TX slots. Signed-off-by: Peter Ujfalusi Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt index 46bc9829c71a..b279b6072bd5 100644 --- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt +++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt @@ -30,6 +30,11 @@ Optional properties: - ti,hwmods : Must be "mcasp", n is controller instance starting 0 - tx-num-evt : FIFO levels. - rx-num-evt : FIFO levels. +- dismod : Specify the drive on TX pin during inactive slots + 0 : 3-state + 2 : logic low + 3 : logic high + Defaults to 'logic low' when the property is not present - sram-size-playback : size of sram to be allocated during playback - sram-size-capture : size of sram to be allocated during capture - interrupts : Interrupt numbers for McASP -- cgit v1.2.3 From 7038250756c42b2bbe02b04223da14aac3a6f641 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 15:28:28 +0100 Subject: ARM: dts: sunxi: Change default CMA pool node name The CMA node has a unit address, but no reg property which generates a warning in DTC. Change the node name to reflect its usage and drop the unit address. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/media/cedrus.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/cedrus.txt b/Documentation/devicetree/bindings/media/cedrus.txt index a089a0c1ff05..33833a43fff8 100644 --- a/Documentation/devicetree/bindings/media/cedrus.txt +++ b/Documentation/devicetree/bindings/media/cedrus.txt @@ -31,7 +31,7 @@ reserved-memory { ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: cma@4a000000 { + cma_pool: default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; -- cgit v1.2.3 From 22cc062c4dfb16330fe18e8d7e155d733fd59e61 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Nov 2018 14:46:30 +0200 Subject: dt-bindings: sound: omap-mcpdm: Update documentation for pdmclk McPDM module receives it's functional clock from external source. This clock is the pdmclk provided by the twl6040 audio IC. If the clock is not available all register accesses to McPDM fails and the module is not operational. Signed-off-by: Peter Ujfalusi Acked-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/omap-mcpdm.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt b/Documentation/devicetree/bindings/sound/omap-mcpdm.txt index 5f4e68ca228c..ff98a0cb5b3f 100644 --- a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt +++ b/Documentation/devicetree/bindings/sound/omap-mcpdm.txt @@ -7,6 +7,8 @@ Required properties: ; - interrupts: Interrupt number for McPDM - ti,hwmods: Name of the hwmod associated to the McPDM +- clocks: phandle for the pdmclk provider, likely <&twl6040> +- clock-names: Must be "pdmclk" Example: @@ -18,3 +20,11 @@ mcpdm: mcpdm@40132000 { interrupt-parent = <&gic>; ti,hwmods = "mcpdm"; }; + +In board DTS file the pdmclk needs to be added: + +&mcpdm { + clocks = <&twl6040>; + clock-names = "pdmclk"; + status = "okay"; +}; -- cgit v1.2.3 From bc0a7dbc5a54a06b925064adba8b07d65acf8718 Mon Sep 17 00:00:00 2001 From: Jenny TC Date: Wed, 28 Nov 2018 12:22:45 +0530 Subject: ASoC: dmic: introduce mode switch delay On startup, applications such as PulseAudio or CRAS enable playback or capture on all PCM devices to verify that configurations are correct, and close them immediately. For DMICs, this can result in the clock being turned off very quickly, which may not compatible with internal state machine transition requirements. This patch add a mode-switch delay which will prevent the clock from being turned off without complying with manufacturer timing specifications. While the DMIC clock may be controlled at a lower level, be it with hardware or firmware, applying the delay during the STOP_TRIGGER phase ensures that there is no race condition, e.g. with the hardware/firmware turning off the clock earlier Signed-off-by: Sathyanarayana Nujella Signed-off-by: Jairaj Arava Signed-off-by: Harsha Priya Signed-off-by: Jenny TC Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/dmic.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/dmic.txt b/Documentation/devicetree/bindings/sound/dmic.txt index e957b4136716..32e871037269 100644 --- a/Documentation/devicetree/bindings/sound/dmic.txt +++ b/Documentation/devicetree/bindings/sound/dmic.txt @@ -9,6 +9,7 @@ Optional properties: - dmicen-gpios: GPIO specifier for dmic to control start and stop - num-channels: Number of microphones on this DAI - wakeup-delay-ms: Delay (in ms) after enabling the DMIC + - modeswitch-delay-ms: Delay (in ms) to complete DMIC mode switch Example node: @@ -17,4 +18,5 @@ Example node: dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; num-channels = <1>; wakeup-delay-ms <50>; + modeswitch-delay-ms <35>; }; -- cgit v1.2.3 From c5435adc3d2981bbf608a5fa8de1cf2d0d2f2ef9 Mon Sep 17 00:00:00 2001 From: Shubhrajyoti Datta Date: Fri, 12 Oct 2018 09:55:09 +0530 Subject: dt-bindings: can: xilinx_can: add Xilinx CAN FD 2.0 bindings Add compatible string and new attributes to support the Xilinx CAN FD 2.0. Signed-off-by: Shubhrajyoti Datta Reviewed-by: Rob Herring Signed-off-by: Marc Kleine-Budde --- Documentation/devicetree/bindings/net/can/xilinx_can.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/can/xilinx_can.txt b/Documentation/devicetree/bindings/net/can/xilinx_can.txt index 060e2d46bad9..100cc40b8510 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx_can.txt +++ b/Documentation/devicetree/bindings/net/can/xilinx_can.txt @@ -6,6 +6,7 @@ Required properties: - "xlnx,zynq-can-1.0" for Zynq CAN controllers - "xlnx,axi-can-1.00.a" for Axi CAN controllers - "xlnx,canfd-1.0" for CAN FD controllers + - "xlnx,canfd-2.0" for CAN FD 2.0 controllers - reg : Physical base address and size of the controller registers map. - interrupts : Property with a value describing the interrupt -- cgit v1.2.3 From b4c7bf003cb57220af64b59e887581e74f0ce527 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 21 Sep 2018 12:03:54 +0200 Subject: dt-bindings: tegra186-pmc: Add interrupt controller properties The PMC can be a top-level interrupt controller that provides the top- level controls for wake events. Add optional properties to mark the PMC as interrupt controller. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt index c9fd6d1de57e..2d89cdc39eb0 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt @@ -15,6 +15,9 @@ Required properties: Optional properties: - nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. +- interrupt-controller: Identifies the node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The value must be 2. Example: -- cgit v1.2.3 From b9c9c39e3d20666c80f64e931ccf4c5684c525ba Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Fri, 23 Nov 2018 08:35:29 +0000 Subject: dt-bindings: can: flexcan: add stop mode property to device tree The FlexCAN controller can parse the stop mode property to enable CAN self wakeup feature. Signed-off-by: Aisheng Dong Signed-off-by: Joakim Zhang Reviewed-by: Rob Herring Signed-off-by: Marc Kleine-Budde --- Documentation/devicetree/bindings/net/can/fsl-flexcan.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt index bfc0c433654f..bc77477c6878 100644 --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt @@ -24,6 +24,14 @@ Optional properties: if this property is present then controller is assumed to be big endian. +- fsl,stop-mode: register bits of stop mode control, the format is + <&gpr req_gpr req_bit ack_gpr ack_bit>. + gpr is the phandle to general purpose register node. + req_gpr is the gpr register offset of CAN stop request. + req_bit is the bit offset of CAN stop request. + ack_gpr is the gpr register offset of CAN stop acknowledge. + ack_bit is the bit offset of CAN stop acknowledge. + Example: can@1c000 { -- cgit v1.2.3 From 922b8fae085d6561ef4a2d1527a14bfde82fd1e8 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 28 Nov 2018 10:57:42 -0800 Subject: dt-bindings: clock: qcom: Fix the xo parent in gpucc example In the bindings that landed for the gpucc we require that the XO clock (one possible parent of the gpucc) be listed. The code doesn't use this yet--this is just to allow us to move toward the day when it does use it. What the code does do today is to hardcode the parent name to "bi_tcxo". That's all well and good. ...but the example in the bindings shows this clock mapping to the clock "xo_board". On the current sdm845.dtsi file the "xo_board" clock is a fixed clock with an output name of "xo_board". The clock with the name "bi_tcxo" is actually provided by the RPMh Clock Controller. Presumably that's the one that was wanted. Let's update the example to make this clearer. Fixes: e431c92188a9 ("dt-bindings: clock: Introduce QCOM Graphics clock bindings") Signed-off-by: Douglas Anderson Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,gpucc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt index 9d0358cc08b4..4e5215ef1acd 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -17,6 +17,6 @@ Example: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clocks = <&xo_board>; + clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; }; -- cgit v1.2.3 From b4c29e89026892494952b648f03958906d357129 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Sun, 18 Nov 2018 14:53:10 +0100 Subject: dt-bindings: amlogic: Add Internal Clock Measurer bindings The Amlogic Meson SoCs embeds a clock measurer IP to measure the internal clock paths frequencies. Acked-by: Martin Blumenstingl Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- .../devicetree/bindings/soc/amlogic/clk-measure.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt new file mode 100644 index 000000000000..205a54bcd7c7 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt @@ -0,0 +1,18 @@ +Amlogic Internal Clock Measurer +=============================== + +The Amlogic SoCs contains an IP to measure the internal clocks. +The precision is multiple of MHz, useful to debug the clock states. + +Required properties: +- compatible: Shall contain one of the following : + "amlogic,meson-gx-clk-measure" for GX SoCs + "amlogic,meson8-clk-measure" for Meson8 SoCs + "amlogic,meson8b-clk-measure" for Meson8b SoCs +- reg: base address and size of the Clock Measurer register space. + +Example: + clock-measure@8758 { + compatible = "amlogic,meson-gx-clk-measure"; + reg = <0x0 0x8758 0x0 0x10>; + }; -- cgit v1.2.3 From b7e386177fa53c3d704754095bd81189ef43bce4 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 19 Sep 2018 18:45:40 -0700 Subject: soc: qcom: smd-rpm: Add QCS404 compatible This patch adds a compatible for the rpm on the Qualcomm QCS404 platform. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt index 89e1cb9212f6..ec95705ba692 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt @@ -23,6 +23,7 @@ resources. "qcom,rpm-msm8916" "qcom,rpm-msm8974" "qcom,rpm-msm8998" + "qcom,rpm-qcs404" - qcom,smd-channels: Usage: required -- cgit v1.2.3 From ef29fcc381814f56b7a6dfef5cb498edee176003 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 8 Nov 2018 14:53:51 +0100 Subject: Documentation: bindings: Add missing Amlogic SCPI sensor bindings amlogic,meson-gxbb-scpi-sensors is both the driver and DT but is not documented. Just add it to amlogic's scpi documentation Signed-off-by: Jerome Brunet Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic,scpi.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt index 7b9a861e9306..5ab59da052df 100644 --- a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt +++ b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt @@ -17,4 +17,11 @@ Required sub-node properties: - compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared memory on Amlogic GXBB SoC. +Sensor bindings for the sensors based on SCPI Message Protocol +-------------------------------------------------------------- +SCPI provides an API to access the various sensors on the SoC. + +Required properties: +- compatible : should be "amlogic,meson-gxbb-scpi-sensors". + [0] Documentation/devicetree/bindings/arm/arm,scpi.txt -- cgit v1.2.3 From 2078231510714578d044b39109f0ab622bf49582 Mon Sep 17 00:00:00 2001 From: He Yangxuan Date: Sat, 10 Nov 2018 11:39:03 +0800 Subject: dt-bindings: Add vendor prefix for PHICOMM Co., Ltd. PHICOMM Co., Ltd. is a hardware provider headquartered in Shanghai, it's product includes router and smart devices. Signed-off-by: He Yangxuan Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 4b1a2a8fcc16..8c413d8cc2a5 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -296,6 +296,7 @@ panasonic Panasonic Corporation parade Parade Technologies Inc. pericom Pericom Technology Inc. pervasive Pervasive Displays, Inc. +phicomm PHICOMM Co., Ltd. phytec PHYTEC Messtechnik GmbH picochip Picochip Ltd pine64 Pine64 -- cgit v1.2.3 From bf0fbc8f0f06b9aaef81a42c3223b8998fb33eab Mon Sep 17 00:00:00 2001 From: He Yangxuan Date: Sat, 10 Nov 2018 11:39:04 +0800 Subject: dt-bindings: arm: amlogic: Add Phicomm N1 Add bindings documentation for the Phicomm N1. Signed-off-by: He Yangxuan Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 4498292b833d..93177f38ec19 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -91,6 +91,7 @@ Board compatible values (alphabetically, grouped by SoC): - "amlogic,p230" (Meson gxl s905d) - "amlogic,p231" (Meson gxl s905d) + - "phicomm,n1" (Meson gxl s905d) - "amlogic,p241" (Meson gxl s805x) -- cgit v1.2.3 From bc3285052afb7f8405b56831b028e14545d08891 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 16 Nov 2018 16:15:38 +0100 Subject: dt-bindings: arm: amlogic: add libretech aml-s805x-ac bindings Add bindings for the Libretech aml-s805x-ac board, aka 'La Frite'. Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 93177f38ec19..8dbc259081e4 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -94,6 +94,7 @@ Board compatible values (alphabetically, grouped by SoC): - "phicomm,n1" (Meson gxl s905d) - "amlogic,p241" (Meson gxl s805x) + - "libretech,aml-s805x-ac" (Meson gxl s805x) - "amlogic,p281" (Meson gxl s905w) - "oranth,tx3-mini" (Meson gxl s905w) -- cgit v1.2.3 From 0cd41af05f130adcce6050acade97ec0fb5069b9 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Mon, 5 Nov 2018 16:43:56 +0800 Subject: dt-bindings: arm: mediatek: document clk bindings for MT7629 This patch adds the binding documentation for apmixedsys, infracfg, pciesys, pericfg, topckgen, ethsys, sgmiisys and ssusbsys for MT7629. Signed-off-by: Ryder Lee Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt | 1 + 8 files changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index 4e4a3c0ab9ab..de4075413d91 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -11,6 +11,7 @@ Required Properties: - "mediatek,mt6797-apmixedsys" - "mediatek,mt7622-apmixedsys" - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" + - "mediatek,mt7629-apmixedsys" - "mediatek,mt8135-apmixedsys" - "mediatek,mt8173-apmixedsys" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt index f17cfe64255d..6b7e8067e7aa 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt @@ -9,6 +9,7 @@ Required Properties: - "mediatek,mt2701-ethsys", "syscon" - "mediatek,mt7622-ethsys", "syscon" - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" + - "mediatek,mt7629-ethsys", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index 89f4272a1441..417bd83d1378 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -12,6 +12,7 @@ Required Properties: - "mediatek,mt6797-infracfg", "syscon" - "mediatek,mt7622-infracfg", "syscon" - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" + - "mediatek,mt7629-infracfg", "syscon" - "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt index 7fe5dc6097a6..d179a61536f4 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-pciesys", "syscon" + - "mediatek,mt7629-pciesys", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt index 6755514deb80..4c7e478117a0 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt @@ -11,6 +11,7 @@ Required Properties: - "mediatek,mt2712-pericfg", "syscon" - "mediatek,mt7622-pericfg", "syscon" - "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon" + - "mediatek,mt7629-pericfg", "syscon" - "mediatek,mt8135-pericfg", "syscon" - "mediatek,mt8173-pericfg", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt index d113b8e741f3..30cb645c0e54 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-sgmiisys", "syscon" + - "mediatek,mt7629-sgmiisys", "syscon" - #clock-cells: Must be 1 The SGMIISYS controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt index b8184da2508c..7cb02c930613 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-ssusbsys", "syscon" + - "mediatek,mt7629-ssusbsys", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index d849465b8c99..d160c2b4b6fe 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -11,6 +11,7 @@ Required Properties: - "mediatek,mt6797-topckgen" - "mediatek,mt7622-topckgen" - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" + - "mediatek,mt7629-topckgen" - "mediatek,mt8135-topckgen" - "mediatek,mt8173-topckgen" - #clock-cells: Must be 1 -- cgit v1.2.3 From c51ba54f6349e677d136dac4d45d628bf1f9524d Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 27 Nov 2018 11:24:43 -0800 Subject: dt-bindings: clock: Require #reset-cells in sdm845-videocc The #reset-cells was listed as optional in the bindings for qcom,sdm845-videocc. There's no reason for it to be optional. As per Stephen [1]: > We should update the binding to make it a required property. It > doesn't make any sense why that property would be optional given > that the hardware either has support for resets or it doesn't. sdm845 support is still in its infancy so we shouldn't be affecting any real device trees by modifying the bindings here. [1] https://lkml.kernel.org/r/154330186815.88331.12720647562079303842@swboyd.mtv.corp.google.com Fixes: 84b66b211603 ("dt-bindings: clock: Introduce QCOM Video clock bindings") Suggested-by: Stephen Boyd Signed-off-by: Douglas Anderson Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,videocc.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt index e7c035afa778..8a8622c65c5a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt @@ -6,8 +6,6 @@ Required properties : - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1. - #power-domain-cells : from generic power domain binding, shall contain 1. - -Optional properties : - #reset-cells : from common reset binding, shall contain 1. Example: @@ -16,4 +14,5 @@ Example: reg = <0xab00000 0x10000>; #clock-cells = <1>; #power-domain-cells = <1>; + #reset-cells = <1>; }; -- cgit v1.2.3 From ca40d2bd813efcee058760c63c9eae043d2939d9 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Wed, 28 Nov 2018 18:53:05 +0100 Subject: dt-bindings: mrvl,mmp-timer: add clock The timer needs the timer clock to be enabled, otherwise it stops ticking. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring Acked-by: Pavel Machek Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt b/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt index 9a6e251462e7..b8f02c663521 100644 --- a/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt +++ b/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt @@ -5,9 +5,13 @@ Required properties: - reg : Address and length of the register set of timer controller. - interrupts : Should be the interrupt number. +Optional properties: +- clocks : Should contain a single entry describing the clock input. + Example: timer0: timer@d4014000 { compatible = "mrvl,mmp-timer"; reg = <0xd4014000 0x100>; interrupts = <13>; + clocks = <&coreclk 2>; }; -- cgit v1.2.3 From e3d786a3745473e905e68aa918b1543c6f9da67c Mon Sep 17 00:00:00 2001 From: Matheus Tavares Date: Fri, 23 Nov 2018 22:23:09 -0200 Subject: dt-bindings:iio:resolver: Add docs for ad2s90 This patch adds the device tree binding documentation for the ad2s90 resolver-to-digital converter. Signed-off-by: Matheus Tavares Reviewed-by: Rob Herring Acked-by: Alexandru Ardelean Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/resolver/ad2s90.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/resolver/ad2s90.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/resolver/ad2s90.txt b/Documentation/devicetree/bindings/iio/resolver/ad2s90.txt new file mode 100644 index 000000000000..477d41fa6467 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/resolver/ad2s90.txt @@ -0,0 +1,31 @@ +Analog Devices AD2S90 Resolver-to-Digital Converter + +https://www.analog.com/en/products/ad2s90.html + +Required properties: + - compatible: should be "adi,ad2s90" + - reg: SPI chip select number for the device + - spi-max-frequency: set maximum clock frequency, must be 830000 + - spi-cpol and spi-cpha: + Either SPI mode (0,0) or (1,1) must be used, so specify none or both of + spi-cpha, spi-cpol. + +See for more details: + Documentation/devicetree/bindings/spi/spi-bus.txt + +Note about max frequency: + Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns + delay is expected between the application of a logic LO to CS and the + application of SCLK, as also specified. And since the delay is not + implemented in the spi code, to satisfy it, SCLK's period should be at most + 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives + roughly 830000Hz. + +Example: +resolver@0 { + compatible = "adi,ad2s90"; + reg = <0>; + spi-max-frequency = <830000>; + spi-cpol; + spi-cpha; +}; -- cgit v1.2.3 From f567035a6187f1a5e7f86d4da4dbbca46cb68082 Mon Sep 17 00:00:00 2001 From: Kun Yi Date: Wed, 17 Oct 2018 15:27:09 -0700 Subject: dt-bindings: hwmon: Add adm127x documentation adm127x are hot-swap controllers that allow a circuit board to be removed from or inserted into a live backplane. This patch adds the device tree bindings documentation. Signed-off-by: Kun Yi Reviewed-by: Rob Herring Signed-off-by: Guenter Roeck --- .../devicetree/bindings/hwmon/adm1275.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/adm1275.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/adm1275.txt b/Documentation/devicetree/bindings/hwmon/adm1275.txt new file mode 100644 index 000000000000..1ecd03f3da4d --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/adm1275.txt @@ -0,0 +1,25 @@ +adm1275 properties + +Required properties: +- compatible: Must be one of the supported compatible strings: + - "adi,adm1075" for adm1075 + - "adi,adm1272" for adm1272 + - "adi,adm1275" for adm1275 + - "adi,adm1276" for adm1276 + - "adi,adm1278" for adm1278 + - "adi,adm1293" for adm1293 + - "adi,adm1294" for adm1294 +- reg: I2C address + +Optional properties: + +- shunt-resistor-micro-ohms + Shunt resistor value in micro-Ohm + +Example: + +adm1272@10 { + compatible = "adi,adm1272"; + reg = <0x10>; + shunt-resistor-micro-ohms = <500>; +}; -- cgit v1.2.3 From 6021c48f3acd68301eacd99ff5dd4744f7b2f288 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Thu, 8 Nov 2018 15:05:20 -0600 Subject: dt-bindings: fsi: Add P9 OCC device documentation Document the bindings for the FSI-attached POWER9 On-Chip Controller. Signed-off-by: Eddie James Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt b/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt new file mode 100644 index 000000000000..99ca9862a586 --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt @@ -0,0 +1,16 @@ +Device-tree bindings for FSI-attached POWER9 On-Chip Controller (OCC) +--------------------------------------------------------------------- + +This is the binding for the P9 On-Chip Controller accessed over FSI from a +service processor. See fsi.txt for details on bindings for FSI slave and CFAM +nodes. The OCC is not an FSI slave device itself, rather it is accessed +through the SBE fifo. + +Required properties: + - compatible = "ibm,p9-occ" + +Examples: + + occ { + compatible = "ibm,p9-occ"; + }; -- cgit v1.2.3 From c0c9872a8ba291fc39fdb62652c24418670ccc46 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Thu, 8 Nov 2018 15:05:23 -0600 Subject: dt-bindings: i2c: Add P8 OCC hwmon device documentation Document the bindings for I2C-based OCC hwmon device. Signed-off-by: Eddie James Acked-by: Rob Herring Signed-off-by: Guenter Roeck --- .../devicetree/bindings/i2c/ibm,p8-occ-hwmon.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/ibm,p8-occ-hwmon.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/ibm,p8-occ-hwmon.txt b/Documentation/devicetree/bindings/i2c/ibm,p8-occ-hwmon.txt new file mode 100644 index 000000000000..5dc5d2e2573d --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/ibm,p8-occ-hwmon.txt @@ -0,0 +1,25 @@ +Device-tree bindings for I2C-based On-Chip Controller hwmon device +------------------------------------------------------------------ + +Required properties: + - compatible = "ibm,p8-occ-hwmon"; + - reg = ; : I2C bus address + +Examples: + + i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + < more properties > + + occ-hwmon@1 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x50>; + }; + + occ-hwmon@2 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x51>; + }; + }; -- cgit v1.2.3 From 71cd532d665159417f9c233b698b7400bc66bd8f Mon Sep 17 00:00:00 2001 From: Mesih Kilinc Date: Sun, 2 Dec 2018 23:23:36 +0300 Subject: dt-bindings: arm: Add new Allwinner ARMv5 F1C100s SoC Add new Allwinner ARMv5 F1C100s SoC's compatible string Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index e4beec3d9ad3..f9ddc05d32f0 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -18,4 +18,5 @@ using one of the following compatible strings: allwinner,sun8i-v3s allwinner,sun9i-a80 allwinner,sun50i-a64 + allwinner,suniv-f1c100s nextthing,gr8 -- cgit v1.2.3 From 1286f930a0d7447748b398564d14e84ea5dfe890 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Mon, 3 Dec 2018 12:47:28 +0100 Subject: ASoC: dt-bindings: use a generic node name for rt5631 The example should follow the practice or using a generic node name instead of the precise programming model, as recommended by the DTSpec. Signed-off-by: Lubomir Rintel Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/rt5631.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/rt5631.txt b/Documentation/devicetree/bindings/sound/rt5631.txt index 92b986ca337b..56bc85232c49 100644 --- a/Documentation/devicetree/bindings/sound/rt5631.txt +++ b/Documentation/devicetree/bindings/sound/rt5631.txt @@ -35,14 +35,14 @@ Pins on the device (for linking into audio routes): Example: -alc5631: alc5631@1a { +alc5631: audio-codec@1a { compatible = "realtek,alc5631"; reg = <0x1a>; }; or -rt5631: rt5631@1a { +rt5631: audio-codec@1a { compatible = "realtek,rt5631"; reg = <0x1a>; }; -- cgit v1.2.3 From 4fb86404a977b932eed56c0dd0954f6225eee3eb Mon Sep 17 00:00:00 2001 From: Alex Gonzalez Date: Thu, 25 Oct 2018 17:09:30 +0200 Subject: drm/panel: simple: Add AUO G101EVN010 panel support The change adds support for the AU Optronics G101EVN010 10.1" TFT LCD panel. Signed-off-by: Alex Gonzalez Reviewed-by: Rob Herring [treding@nvidia.com: sort new entry alphabetically] Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/1540480173-12009-2-git-send-email-alex.gonzalez@digi.com --- .../devicetree/bindings/display/panel/auo,g101evn010 | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/auo,g101evn010 (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/auo,g101evn010 b/Documentation/devicetree/bindings/display/panel/auo,g101evn010 new file mode 100644 index 000000000000..bc6a0c858e23 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/auo,g101evn010 @@ -0,0 +1,12 @@ +AU Optronics Corporation 10.1" (1280x800) color TFT LCD panel + +Required properties: +- compatible: should be "auo,g101evn010" +- power-supply: as specified in the base binding + +Optional properties: +- backlight: as specified in the base binding +- enable-gpios: as specified in the base binding + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- cgit v1.2.3 From 7898e4fef8352ef8a0d2bbd13c10fcc77c38e80e Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 30 Nov 2018 23:51:27 +0530 Subject: dt-bindings: clock: Update GCC bindings for protected-clocks Add protected-clocks list which could used to specify the clocks to be bypassed on certain devices. Reviewed-by: Rob Herring Signed-off-by: Taniya Das Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,gcc.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 52d9345c9927..5e37de95bfe8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -35,6 +35,8 @@ be part of GCC and hence the TSENS properties can also be part of the GCC/clock-controller node. For more details on the TSENS properties please refer Documentation/devicetree/bindings/thermal/qcom-tsens.txt +- protected-clocks : Protected clock specifier list as per common clock + binding. Example: clock-controller@900000 { @@ -55,3 +57,15 @@ Example of GCC with TSENS properties: #reset-cells = <1>; #thermal-sensor-cells = <1>; }; + +Example of GCC with protected-clocks properties: + clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + protected-clocks = , + , + ; + }; -- cgit v1.2.3 From 8ff1a156cb0b40a267fe7a2c69c06a6d566a7524 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 30 Nov 2018 23:51:28 +0530 Subject: dt-bindings: clock: Introduce QCOM LPASS clock bindings Add device tree bindings for Low Power Audio subsystem clock controller for Qualcomm Technology Inc's SDM845 SoCs. Reviewed-by: Rob Herring Signed-off-by: Taniya Das Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,gcc.txt | 4 +++- .../devicetree/bindings/clock/qcom,lpasscc.txt | 26 ++++++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,lpasscc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 5e37de95bfe8..8661c3cd3ccf 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -67,5 +67,7 @@ Example of GCC with protected-clocks properties: #power-domain-cells = <1>; protected-clocks = , , - ; + , + , + ; }; diff --git a/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file mode 100644 index 000000000000..b9e9787045b9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt @@ -0,0 +1,26 @@ +Qualcomm LPASS Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,sdm845-lpasscc" +- #clock-cells : from common clock binding, shall contain 1. +- reg : shall contain base register address and size, + in the order + Index-0 maps to LPASS_CC register region + Index-1 maps to LPASS_QDSP6SS register region + +Optional properties : +- reg-names : register names of LPASS domain + "cc", "qdsp6ss". + +Example: + +The below node has to be defined in the cases where the LPASS peripheral loader +would bring the subsystem out of reset. + + lpasscc: clock-controller@17014000 { + compatible = "qcom,sdm845-lpasscc"; + reg = <0x17014000 0x1f004>, <0x17300000 0x200>; + reg-names = "cc", "qdsp6ss"; + #clock-cells = <1>; + }; -- cgit v1.2.3 From 1cf3817bf1f52e57b3f5eb0413ee0d7f0c2e9829 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 1 Dec 2018 10:52:10 +0000 Subject: dt-bindings: Add binding for i.MX8MQ CCM This adds the binding for the i.MX8MQ Clock Controller Module. Signed-off-by: Lucas Stach Signed-off-by: Abel Vesa Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/imx8mq-clock.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx8mq-clock.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/imx8mq-clock.txt b/Documentation/devicetree/bindings/clock/imx8mq-clock.txt new file mode 100644 index 000000000000..52de8263e012 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8mq-clock.txt @@ -0,0 +1,20 @@ +* Clock bindings for NXP i.MX8M Quad + +Required properties: +- compatible: Should be "fsl,imx8mq-ccm" +- reg: Address and length of the register set +- #clock-cells: Should be <1> +- clocks: list of clock specifiers, must contain an entry for each required + entry in clock-names +- clock-names: should include the following entries: + - "ckil" + - "osc_25m" + - "osc_27m" + - "clk_ext1" + - "clk_ext2" + - "clk_ext3" + - "clk_ext4" + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h +for the full list of i.MX8M Quad clock IDs. -- cgit v1.2.3 From 5d331b7f4c4c9042298028f73f9f782b11fadaa2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 8 Nov 2018 07:50:10 -0500 Subject: media: sony-cxd2880: add optional vcc regulator to bindings This patchset adds an optional VCC regulator to the bindings of the Sony CXD2880 DVB-T2/T tuner + demodulator adapter. Signed-off-by: Neil Armstrong Acked-by: Yasunari Takiguchi Reviewed-by: Rob Herring Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt b/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt index fc5aa263abe5..98a72c0b3c64 100644 --- a/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt +++ b/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt @@ -5,6 +5,10 @@ Required properties: - reg: SPI chip select number for the device. - spi-max-frequency: Maximum bus speed, should be set to <55000000> (55MHz). +Optional properties: +- vcc-supply: Optional phandle to the vcc regulator to power the adapter, + as described in the file ../regulator/regulator.txt + Example: cxd2880@0 { -- cgit v1.2.3 From eb299e4d5708c1d95779997b3268aac1a1854bbf Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Wed, 14 Nov 2018 13:01:56 +0000 Subject: dt-bindings: clock: add imx7ulp clock binding doc i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks Note IMX7ULP has two clock domains: M4 and A7. This binding doc is only for A7 clock domain. Cc: Rob Herring Cc: Mark Rutland Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/imx7ulp-clock.txt | 104 +++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt new file mode 100644 index 000000000000..a4f8cd478f92 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt @@ -0,0 +1,104 @@ +* Clock bindings for Freescale i.MX7ULP + +i.MX7ULP Clock functions are under joint control of the System +Clock Generation (SCG) modules, Peripheral Clock Control (PCC) +modules, and Core Mode Controller (CMC)1 blocks + +The clocking scheme provides clear separation between M4 domain +and A7 domain. Except for a few clock sources shared between two +domains, such as the System Oscillator clock, the Slow IRC (SIRC), +and and the Fast IRC clock (FIRCLK), clock sources and clock +management are separated and contained within each domain. + +M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. +A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. + +Note: this binding doc is only for A7 clock domain. + +System Clock Generation (SCG) modules: +--------------------------------------------------------------------- +The System Clock Generation (SCG) is responsible for clock generation +and distribution across this device. Functions performed by the SCG +include: clock reference selection, generation of clock used to derive +processor, system, peripheral bus and external memory interface clocks, +source selection for peripheral clocks and control of power saving +clock gating mode. + +Required properties: + +- compatible: Should be "fsl,imx7ulp-scg1". +- reg : Should contain registers location and length. +- #clock-cells: Should be <1>. +- clocks: Should contain the fixed input clocks. +- clock-names: Should contain the following clock names: + "rosc", "sosc", "sirc", "firc", "upll", "mpll". + +Peripheral Clock Control (PCC) modules: +--------------------------------------------------------------------- +The Peripheral Clock Control (PCC) is responsible for clock selection, +optional division and clock gating mode for peripherals in their +respected power domain + +Required properties: +- compatible: Should be one of: + "fsl,imx7ulp-pcc2", + "fsl,imx7ulp-pcc3". +- reg : Should contain registers location and length. +- #clock-cells: Should be <1>. +- clocks: Should contain the fixed input clocks. +- clock-names: Should contain the following clock names: + "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", + "apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk", + "mpll", "firc_bus_clk", "rosc", "spll_bus_clk"; + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. +See include/dt-bindings/clock/imx7ulp-clock.h +for the full list of i.MX7ULP clock IDs of each module. + +Examples: + +#include + +scg1: scg1@403e0000 { + compatible = "fsl,imx7ulp-scg1; + reg = <0x403e0000 0x10000>; + clocks = <&rosc>, <&sosc>, <&sirc>, + <&firc>, <&upll>, <&mpll>; + clock-names = "rosc", "sosc", "sirc", + "firc", "upll", "mpll"; + #clock-cells = <1>; +}; + +pcc2: pcc2@403f0000 { + compatible = "fsl,imx7ulp-pcc2"; + reg = <0x403f0000 0x10000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&scg1 IMX7ULP_CLK_DDR_DIV>, + <&scg1 IMX7ULP_CLK_APLL_PFD2>, + <&scg1 IMX7ULP_CLK_APLL_PFD1>, + <&scg1 IMX7ULP_CLK_APLL_PFD0>, + <&scg1 IMX7ULP_CLK_UPLL>, + <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_MIPI_PLL>, + <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_ROSC>, + <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; + clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", + "apll_pfd2", "apll_pfd1", "apll_pfd0", + "upll", "sosc_bus_clk", "mpll", + "firc_bus_clk", "rosc", "spll_bus_clk"; +}; + +usdhc1: usdhc@40380000 { + compatible = "fsl,imx7ulp-usdhc"; + reg = <0x40380000 0x10000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&pcc2 IMX7ULP_CLK_USDHC1>; + clock-names ="ipg", "ahb", "per"; + bus-width = <4>; +}; -- cgit v1.2.3 From 3d737ddbe74c421ab5da563908484a06748e0211 Mon Sep 17 00:00:00 2001 From: Mesih Kilinc Date: Sun, 2 Dec 2018 23:23:46 +0300 Subject: dt-bindings: clock: Add Allwinner suniv F1C100s CCU Add compatiple string for Allwinner suniv F1C100s CCU. Add clock and reset definitions. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Acked-by: Stephen Boyd Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 47d2e902ced4..e3bd88ae456b 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -22,6 +22,7 @@ Required properties : - "allwinner,sun50i-h5-ccu" - "allwinner,sun50i-h6-ccu" - "allwinner,sun50i-h6-r-ccu" + - "allwinner,suniv-f1c100s-ccu" - "nextthing,gr8-ccu" - reg: Must contain the registers base address and length -- cgit v1.2.3 From 6331d184e65e270b4768679b94e73eef1ab2ccde Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sun, 11 Nov 2018 20:31:13 +0100 Subject: dt-bindings: rtc: add generic bindings Add generic binding documentation for the RTC subsystem. Signed-off-by: Alexandre Belloni Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/rtc/rtc.txt | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/rtc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc.txt b/Documentation/devicetree/bindings/rtc/rtc.txt new file mode 100644 index 000000000000..221b7da50aca --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/rtc.txt @@ -0,0 +1,30 @@ +Generic device tree bindings for Real Time Clock devices +======================================================== + +This document describes generic bindings which can be used to describe Real Time +Clock devices in a device tree. + +Required properties +------------------- + +- compatible : name of RTC device following generic names recommended practice. + +For other required properties e.g. to describe register sets, +clocks, etc. check the binding documentation of the specific driver. + +Optional properties +------------------- + +- start-year : if provided, the default hardware range supported by the RTC is + shifted so the first usable year is the specified one. + +The following properties may not be supported by all drivers. However, if a +driver wants to support one of the below features, it should adapt the bindings +below. +- trickle-resistor-ohms : Selected resistor for trickle charger. Should be given + if trickle charger should be enabled +- trickle-diode-disable : Do not use internal trickle charger diode Should be + given if internal trickle charger diode should be + disabled +- wakeup-source : Enables wake up of host system on alarm + -- cgit v1.2.3 From ae517053f003bc3739640acd8d77617b14bf45d2 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sun, 11 Nov 2018 20:31:14 +0100 Subject: dt-bindings: rtc: Move trivial RTCs to rtc.txt Move trivial RTCs to the rtc generic binding documentation as they all also support at least 'start-year'. Signed-off-by: Alexandre Belloni Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/rtc/rtc.txt | 34 ++++++++++++++++++++++ .../devicetree/bindings/trivial-devices.txt | 24 --------------- 2 files changed, 34 insertions(+), 24 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc.txt b/Documentation/devicetree/bindings/rtc/rtc.txt index 221b7da50aca..7c8da6926095 100644 --- a/Documentation/devicetree/bindings/rtc/rtc.txt +++ b/Documentation/devicetree/bindings/rtc/rtc.txt @@ -28,3 +28,37 @@ below. disabled - wakeup-source : Enables wake up of host system on alarm +Trivial RTCs +------------ + +This is a list of trivial RTC devices that have simple device tree +bindings, consisting only of a compatible field, an address and +possibly an interrupt line. + + +Compatible Vendor / Chip +========== ============= +abracon,abb5zes3 AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface +dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output +dallas,ds1672 Dallas DS1672 Real-time Clock +dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM +epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE +epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE +emmicro,em3027 EM Microelectronic EM3027 Real-time Clock +isil,isl1208 Intersil ISL1208 Low Power RTC with Battery Backed SRAM +isil,isl1218 Intersil ISL1218 Low Power RTC with Battery Backed SRAM +isil,isl12022 Intersil ISL12022 Real-time Clock +microcrystal,rv3029 Real Time Clock Module with I2C-Bus +nxp,pcf2127 Real-time clock +nxp,pcf2129 Real-time clock +nxp,pcf8523 Real-time Clock +nxp,pcf8563 Real-time clock/calendar +nxp,pcf85063 Tiny Real-Time Clock +pericom,pt7c4338 Real-time Clock Module +ricoh,r2025sd I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC +ricoh,r2221tl I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC +ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC +ricoh,rs5c372b I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC +ricoh,rv5c386 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC +ricoh,rv5c387a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC +sii,s35390a 2-wire CMOS real-time clock diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt index 6ab001fa1ed4..fda7a0f50c1e 100644 --- a/Documentation/devicetree/bindings/trivial-devices.txt +++ b/Documentation/devicetree/bindings/trivial-devices.txt @@ -9,7 +9,6 @@ document for it just like any other devices. Compatible Vendor / Chip ========== ============= -abracon,abb5zes3 AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface ad,ad7414 SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin ad,adm9240 ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems adi,adt7461 +/-1C TDM Extended Temp Range I.C @@ -25,12 +24,9 @@ at,24c08 i2c serial eeprom (24cxx) atmel,at97sc3204t i2c trusted platform module (TPM) capella,cm32181 CM32181: Ambient Light Sensor capella,cm3232 CM3232: Ambient Light Sensor -dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output dallas,ds1631 High-Precision Digital Thermometer -dallas,ds1672 Dallas DS1672 Real-time Clock dallas,ds1682 Total-Elapsed-Time Recorder with Alarm dallas,ds1775 Tiny Digital Thermometer and Thermostat -dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O dallas,ds75 Digital Thermometer and Thermostat devantech,srf02 Devantech SRF02 ultrasonic ranger in I2C mode @@ -40,9 +36,6 @@ dlg,da9053 DA9053: flexible system level PMIC with multicore support dlg,da9063 DA9063: system PMIC for quad-core application processors domintech,dmard09 DMARD09: 3-axis Accelerometer domintech,dmard10 DMARD10: 3-axis Accelerometer -epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE -epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE -emmicro,em3027 EM Microelectronic EM3027 Real-time Clock fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer fsl,mma7660 MMA7660FC: 3-Axis Orientation/Motion Detection Sensor fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer @@ -53,9 +46,6 @@ gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire In infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) infineon,tlv493d-a1b6 Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor -isil,isl1208 Intersil ISL1208 Low Power RTC with Battery Backed SRAM -isil,isl1218 Intersil ISL1218 Low Power RTC with Battery Backed SRAM -isil,isl12022 Intersil ISL12022 Real-time Clock isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor isil,isl29030 Intersil ISL29030 Ambient Light and Proximity Sensor maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator @@ -142,7 +132,6 @@ microchip,mcp4662-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Mem microchip,mcp4662-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) microchip,tc654 PWM Fan Speed Controller With Fan Fault Detection microchip,tc655 PWM Fan Speed Controller With Fan Fault Detection -microcrystal,rv3029 Real Time Clock Module with I2C-Bus miramems,da226 MiraMEMS DA226 2-axis 14-bit digital accelerometer miramems,da280 MiraMEMS DA280 3-axis 14-bit digital accelerometer miramems,da311 MiraMEMS DA311 3-axis 12-bit digital accelerometer @@ -156,25 +145,12 @@ nuvoton,npct601 i2c trusted platform module (TPM2) nuvoton,w83773g Nuvoton Temperature Sensor nxp,pca9556 Octal SMBus and I2C registered interface nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset -nxp,pcf2127 Real-time clock -nxp,pcf2129 Real-time clock -nxp,pcf8523 Real-time Clock -nxp,pcf8563 Real-time clock/calendar -nxp,pcf85063 Tiny Real-Time Clock oki,ml86v7667 OKI ML86V7667 video decoder ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus -pericom,pt7c4338 Real-time Clock Module plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch pulsedlight,lidar-lite-v2 Pulsedlight LIDAR range-finding sensor -ricoh,r2025sd I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,r2221tl I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rs5c372b I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rv5c386 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rv5c387a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) sgx,vz89x SGX Sensortech VZ89X Sensors -sii,s35390a 2-wire CMOS real-time clock silabs,si7020 Relative Humidity and Temperature Sensors skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply st,24c256 i2c serial eeprom (24cxx) -- cgit v1.2.3 From 685efffe37c921cf1d56dd3c8617dc67bc343a99 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 16 Nov 2018 16:49:27 +0100 Subject: soc: imx: gpcv2: add support for i.MX8MQ SoC The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the GPCv2 on the i.MX7, but only controls more power domains with a different mapping. Signed-off-by: Lucas Stach Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt index 9acce75b29ab..7c947a996df1 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt @@ -6,7 +6,9 @@ Control (PGC) for various power domains. Required properties: -- compatible: Should be "fsl,imx7d-gpc" +- compatible: Should be one of: + - "fsl,imx7d-gpc" + - "fsl,imx8mq-gpc" - reg: should be register base and length as documented in the datasheet @@ -22,7 +24,8 @@ which, in turn, is expected to contain the following: Required properties: - reg: Power domain index. Valid values are defined in - include/dt-bindings/power/imx7-power.h + include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and + include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc - #power-domain-cells: Should be 0 -- cgit v1.2.3 From fa3abfb6943ef2976deda78d83788a1352963f47 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 3 Dec 2018 18:16:38 +0100 Subject: dt-bindings: clk: meson: add ao controller clock inputs Add the clock inputs of amlogic AO clock controller Signed-off-by: Jerome Brunet Reviewed-by: Stephen Boyd Signed-off-by: Kevin Hilman --- .../devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt index 3a880528030e..79511d7bb321 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt @@ -11,6 +11,13 @@ Required Properties: - GXM (S912) : "amlogic,meson-gxm-aoclkc" - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" followed by the common "amlogic,meson-gx-aoclkc" +- clocks: list of clock phandle, one for each entry clock-names. +- clock-names: should contain the following: + * "xtal" : the platform xtal + * "mpeg-clk" : the main clock controller mother clock (aka clk81) + * "ext-32k-0" : external 32kHz reference #0 if any (optional) + * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only) + * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only) - #clock-cells: should be 1. @@ -40,8 +47,9 @@ ao_sysctrl: sys-ctrl@0 { compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; -}; Example: UART controller node that consumes the clock and reset generated by the clock controller: -- cgit v1.2.3 From b1d02a84b552fde1232dc11b3c8465433fa1339d Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 3 Dec 2018 18:16:39 +0100 Subject: dt-bindings: clk: meson: add main controller clock input Add the clock input of the main clock controller Signed-off-by: Jerome Brunet Reviewed-by: Stephen Boyd Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599566a9..a6871953bf04 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,9 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. +- clocks : list of clock phandle, one for each entry clock-names. +- clock-names : should contain the following: + * "xtal": the platform xtal - #clock-cells: should be 1. @@ -31,6 +34,8 @@ sysctrl: system-controller@0 { clkc: clock-controller { #clock-cells = <1>; compatible = "amlogic,gxbb-clkc"; + clocks = <&xtal>; + clock-names = "xtal"; }; }; -- cgit v1.2.3 From 89212465c194853becaa17f82dfc1d7d30b56d5e Mon Sep 17 00:00:00 2001 From: Long Cheng Date: Wed, 5 Dec 2018 16:42:57 +0800 Subject: dt-bindings: dma: uart: add uart dma bindings add uart dma bindings Signed-off-by: Long Cheng Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/dma/8250_mtk_dma.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/8250_mtk_dma.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/8250_mtk_dma.txt b/Documentation/devicetree/bindings/dma/8250_mtk_dma.txt new file mode 100644 index 000000000000..3fe0961bcf64 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/8250_mtk_dma.txt @@ -0,0 +1,33 @@ +* Mediatek UART APDMA Controller + +Required properties: +- compatible should contain: + * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA + * "mediatek,mt6577-uart-dma" for MT6577 and all of the above + +- reg: The base address of the APDMA register bank. + +- interrupts: A single interrupt specifier. + +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: The APDMA clock for register accesses + +Examples: + + apdma: dma-controller@11000380 { + compatible = "mediatek,mt2712-uart-dma"; + reg = <0 0x11000380 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&pericfg CLK_PERI_AP_DMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + -- cgit v1.2.3 From 46d1ec73c19067dad22523632306e3fffedb5f11 Mon Sep 17 00:00:00 2001 From: Mesih Kilinc Date: Sun, 2 Dec 2018 23:23:48 +0300 Subject: dt-bindings: sram: Add Allwinner suniv F1C100s The suniv ARMv5 F1C100s chip has similar sram controller to sun4i A10. Add compatible string for it. Signed-off-by: Mesih Kilinc Reviewed-by: Rob Herring Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/sram/sunxi-sram.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt index 62dd0748f0ef..5c84850dd0df 100644 --- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt +++ b/Documentation/devicetree/bindings/sram/sunxi-sram.txt @@ -19,6 +19,7 @@ Required properties: - "allwinner,sun50i-a64-sram-controller" (deprecated) - "allwinner,sun50i-a64-system-control" - "allwinner,sun50i-h6-system-control", "allwinner,sun50i-a64-system-control" + - "allwinner,suniv-f1c100s-system-control", "allwinner,sun4i-a10-system-control" - reg : sram controller register offset + length SRAM nodes @@ -58,6 +59,9 @@ The valid sections compatible for A64 are: The valid sections compatible for H6 are: - allwinner,sun50i-h6-sram-c, allwinner,sun50i-a64-sram-c +The valid sections compatible for F1C100s are: + - allwinner,suniv-f1c100s-sram-d, allwinner,sun4i-a10-sram-d + Devices using SRAM sections --------------------------- -- cgit v1.2.3 From dabfc8364ca76c8f8a24e8b5efc348869ac35d79 Mon Sep 17 00:00:00 2001 From: Mesih Kilinc Date: Sun, 2 Dec 2018 23:23:49 +0300 Subject: dt-bindings: watchdog: Add Allwinner ARMv5 F1C100s wdt Allwinner ARMv5 F1C100s has similar watchdog timer to sun6i A31. Add definition for it. Signed-off-by: Mesih Kilinc Reviewed-by: Rob Herring Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt index ed11ce0ac836..46055254e8dd 100644 --- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt @@ -6,6 +6,7 @@ Required properties: "allwinner,sun4i-a10-wdt" "allwinner,sun6i-a31-wdt" "allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt" + "allwinner,suniv-f1c100s-wdt", "allwinner,sun4i-a10-wdt" - reg : Specifies base physical address and size of the registers. Optional properties: -- cgit v1.2.3 From ebc0a24d11b3618e7680e117ee3be421c09ad43a Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 5 Dec 2018 10:24:34 +0100 Subject: dt-bindings: sram: sunxi: Add bindings for the H5 with SRAM C1 This introduces new bindings for the H5 SoC in the SRAM controller. Because the SRAM layout is different from other SoCs, no backward compatibility is assumed with any of them. However, the C1 SRAM section alone looks similar to previous SoCs, so it is compatible with the initial A10 binding. Signed-off-by: Paul Kocialkowski Acked-by: Chen-Yu Tsai Reviewed-by: Rob Herring Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/sram/sunxi-sram.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt index 5c84850dd0df..5c9a54ad3b53 100644 --- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt +++ b/Documentation/devicetree/bindings/sram/sunxi-sram.txt @@ -18,6 +18,7 @@ Required properties: - "allwinner,sun8i-h3-system-control" - "allwinner,sun50i-a64-sram-controller" (deprecated) - "allwinner,sun50i-a64-system-control" + - "allwinner,sun50i-h5-system-control" - "allwinner,sun50i-h6-system-control", "allwinner,sun50i-a64-system-control" - "allwinner,suniv-f1c100s-system-control", "allwinner,sun4i-a10-system-control" - reg : sram controller register offset + length @@ -56,6 +57,9 @@ The valid sections compatible for H3 are: The valid sections compatible for A64 are: - allwinner,sun50i-a64-sram-c +The valid sections compatible for H5 are: + - allwinner,sun50i-h5-sram-c1, allwinner,sun4i-a10-sram-c1 + The valid sections compatible for H6 are: - allwinner,sun50i-h6-sram-c, allwinner,sun50i-a64-sram-c -- cgit v1.2.3 From d44d37cb27df5501de0693fb03803e244653713c Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 5 Dec 2018 10:24:38 +0100 Subject: dt-bindings: sram: sunxi: Add compatible for the A64 SRAM C1 This introduces a new compatible for the A64 SRAM C1 section, that is compatible with the SRAM C1 section as found on the A10. Signed-off-by: Paul Kocialkowski Acked-by: Chen-Yu Tsai Reviewed-by: Rob Herring Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/sram/sunxi-sram.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt index 5c9a54ad3b53..ab5a70bb9a64 100644 --- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt +++ b/Documentation/devicetree/bindings/sram/sunxi-sram.txt @@ -56,6 +56,7 @@ The valid sections compatible for H3 are: The valid sections compatible for A64 are: - allwinner,sun50i-a64-sram-c + - allwinner,sun50i-a64-sram-c1, allwinner,sun4i-a10-sram-c1 The valid sections compatible for H5 are: - allwinner,sun50i-h5-sram-c1, allwinner,sun4i-a10-sram-c1 -- cgit v1.2.3 From 302d29700d0e25beb3c72474f90342f840945894 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Tue, 27 Nov 2018 05:02:51 -0500 Subject: media: dt-bindings: media: mt9m111: adapt documentation to be more clear Replace the vague binding by a more verbose. Remove the remote property from the example since the driver don't support such a property. Also remove the bus-width property from the endpoint since the driver don't take care of it. Signed-off-by: Marco Felsch Reviewed-by: Rob Herring Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/i2c/mt9m111.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/mt9m111.txt b/Documentation/devicetree/bindings/media/i2c/mt9m111.txt index 6b910036b57e..a431fb45704b 100644 --- a/Documentation/devicetree/bindings/media/i2c/mt9m111.txt +++ b/Documentation/devicetree/bindings/media/i2c/mt9m111.txt @@ -9,8 +9,10 @@ Required Properties: - clocks: reference to the master clock. - clock-names: shall be "mclk". -For further reading on port node refer to -Documentation/devicetree/bindings/media/video-interfaces.txt. +The device node must contain one 'port' child node with one 'endpoint' child +sub-node for its digital output video port, in accordance with the video +interface bindings defined in: +Documentation/devicetree/bindings/media/video-interfaces.txt Example: @@ -21,10 +23,8 @@ Example: clocks = <&mclk>; clock-names = "mclk"; - remote = <&pxa_camera>; port { mt9m111_1: endpoint { - bus-width = <8>; remote-endpoint = <&pxa_camera>; }; }; -- cgit v1.2.3 From 48856d91321f07e001f53f9726843b1e4144aeca Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Tue, 27 Nov 2018 05:02:52 -0500 Subject: media: dt-bindings: media: mt9m111: add pclk-sample property Add the pclk-sample property to the list of optional properties for the mt9m111 camera sensor. Signed-off-by: Marco Felsch Reviewed-by: Rob Herring Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/i2c/mt9m111.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/mt9m111.txt b/Documentation/devicetree/bindings/media/i2c/mt9m111.txt index a431fb45704b..d0bed6fa901a 100644 --- a/Documentation/devicetree/bindings/media/i2c/mt9m111.txt +++ b/Documentation/devicetree/bindings/media/i2c/mt9m111.txt @@ -14,6 +14,10 @@ sub-node for its digital output video port, in accordance with the video interface bindings defined in: Documentation/devicetree/bindings/media/video-interfaces.txt +Optional endpoint properties: +- pclk-sample: For information see ../video-interfaces.txt. The value is set to + 0 if it isn't specified. + Example: i2c_master { @@ -26,6 +30,7 @@ Example: port { mt9m111_1: endpoint { remote-endpoint = <&pxa_camera>; + pclk-sample = <1>; }; }; }; -- cgit v1.2.3 From e29d0d9c90c9592dea18d0a838fffc85d6e3d028 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Fri, 21 Jul 2017 12:22:23 +0200 Subject: dt-bindings: i3c: Document Cadence I3C master bindings Document Cadence I3C master DT bindings. Signed-off-by: Boris Brezillon Reviewed-by: Rob Herring Reviewed-by: Arnd Bergmann Acked-by: Greg Kroah-Hartman --- .../devicetree/bindings/i3c/cdns,i3c-master.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/cdns,i3c-master.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i3c/cdns,i3c-master.txt b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.txt new file mode 100644 index 000000000000..69da2115abdc --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.txt @@ -0,0 +1,43 @@ +Bindings for cadence I3C master block +===================================== + +Required properties: +-------------------- +- compatible: shall be "cdns,i3c-master" +- clocks: shall reference the pclk and sysclk +- clock-names: shall contain "pclk" and "sysclk" +- interrupts: the interrupt line connected to this I3C master +- reg: I3C master registers + +Mandatory properties defined by the generic binding (see +Documentation/devicetree/bindings/i3c/i3c.txt for more details): + +- #address-cells: shall be set to 1 +- #size-cells: shall be set to 0 + +Optional properties defined by the generic binding (see +Documentation/devicetree/bindings/i3c/i3c.txt for more details): + +- i2c-scl-hz +- i3c-scl-hz + +I3C device connected on the bus follow the generic description (see +Documentation/devicetree/bindings/i3c/i3c.txt for more details). + +Example: + + i3c-master@0d040000 { + compatible = "cdns,i3c-master"; + clocks = <&coreclock>, <&i3csysclock>; + clock-names = "pclk", "sysclk"; + interrupts = <3 0>; + reg = <0x0d040000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + i2c-scl-hz = <100000>; + + nunchuk: nunchuk@52 { + compatible = "nintendo,nunchuk"; + reg = <0x52 0x80000010 0>; + }; + }; -- cgit v1.2.3 From 116e246a8bcd5ace5cac887228afe60152b30d10 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Tue, 13 Nov 2018 14:09:52 +0000 Subject: dt-binding: i3c: Document Synopsys DesignWare I3C Document Synopsys DesignWare I3C master module Signed-off-by: Vitor Soares Reviewed-by: Rob Herring Signed-off-by: Boris Brezillon --- .../devicetree/bindings/i3c/snps,dw-i3c-master.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.txt b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.txt new file mode 100644 index 000000000000..5020eb71eb8d --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.txt @@ -0,0 +1,41 @@ +Bindings for Synopsys DesignWare I3C master block +================================================= + +Required properties: +-------------------- +- compatible: shall be "snps,dw-i3c-master-1.00a" +- clocks: shall reference the core_clk +- interrupts: the interrupt line connected to this I3C master +- reg: Offset and length of I3C master registers + +Mandatory properties defined by the generic binding (see +Documentation/devicetree/bindings/i3c/i3c.txt for more details): + +- #address-cells: shall be set to 3 +- #size-cells: shall be set to 0 + +Optional properties defined by the generic binding (see +Documentation/devicetree/bindings/i3c/i3c.txt for more details): + +- i2c-scl-hz +- i3c-scl-hz + +I3C device connected on the bus follow the generic description (see +Documentation/devicetree/bindings/i3c/i3c.txt for more details). + +Example: + + i3c-master@2000 { + compatible = "snps,dw-i3c-master-1.00a"; + #address-cells = <3>; + #size-cells = <0>; + reg = <0x02000 0x1000>; + interrupts = <0>; + clocks = <&i3cclk>; + + eeprom@57{ + compatible = "atmel,24c01"; + reg = <0x57 0x0 0x10>; + pagesize = <0x8>; + }; + }; -- cgit v1.2.3 From 89d21972da2b16c6acd1d07baed220ed843bd096 Mon Sep 17 00:00:00 2001 From: Oskari Lemmela Date: Tue, 20 Nov 2018 19:52:04 +0200 Subject: dt-bindings: power: supply: axp20x: add AXP813 AC power DT binding The AXP803/AXP813 AC power supply can limit input current and voltage. Signed-off-by: Oskari Lemmela Reviewed-by: Rob Herring Reviewed-by: Quentin Schulz Reviewed-by: Chen-Yu Tsai Reviewed-by: Sebastian Reichel Tested-by: Vasily Khoruzhick Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/supply/axp20x_ac_power.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/axp20x_ac_power.txt b/Documentation/devicetree/bindings/power/supply/axp20x_ac_power.txt index 826e8a879121..7a1fb532abe5 100644 --- a/Documentation/devicetree/bindings/power/supply/axp20x_ac_power.txt +++ b/Documentation/devicetree/bindings/power/supply/axp20x_ac_power.txt @@ -4,6 +4,7 @@ Required Properties: - compatible: One of: "x-powers,axp202-ac-power-supply" "x-powers,axp221-ac-power-supply" + "x-powers,axp813-ac-power-supply" This node is a subnode of the axp20x PMIC. @@ -13,6 +14,8 @@ reading ADC channels from the AXP20X ADC. The AXP22X is only able to tell if an AC power supply is present and usable. +AXP813/AXP803 are able to limit current and supply voltage + Example: &axp209 { -- cgit v1.2.3 From 7f22507b1397acd90481d79085c902789b62157f Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 30 Nov 2018 12:34:30 -0500 Subject: media: dt-bindings: Document the Rockchip VPU bindings Add devicetree binding documentation for Rockchip Video Processing Unit IP. Reviewed-by: Rob Herring Signed-off-by: Ezequiel Garcia Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/rockchip-vpu.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/rockchip-vpu.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.txt b/Documentation/devicetree/bindings/media/rockchip-vpu.txt new file mode 100644 index 000000000000..35dc464ad7c8 --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip-vpu.txt @@ -0,0 +1,29 @@ +device-tree bindings for rockchip VPU codec + +Rockchip (Video Processing Unit) present in various Rockchip platforms, +such as RK3288 and RK3399. + +Required properties: +- compatible: value should be one of the following + "rockchip,rk3288-vpu"; + "rockchip,rk3399-vpu"; +- interrupts: encoding and decoding interrupt specifiers +- interrupt-names: should be "vepu" and "vdpu" +- clocks: phandle to VPU aclk, hclk clocks +- clock-names: should be "aclk" and "hclk" +- power-domains: phandle to power domain node +- iommus: phandle to a iommu node + +Example: +SoC-specific DT entry: + vpu: video-codec@ff9a0000 { + compatible = "rockchip,rk3288-vpu"; + reg = <0x0 0xff9a0000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3288_PD_VIDEO>; + iommus = <&vpu_mmu>; + }; -- cgit v1.2.3 From b255e500c8dc111dd9efac1442a85a0dac913feb Mon Sep 17 00:00:00 2001 From: Jakub Kicinski Date: Mon, 3 Dec 2018 17:43:28 -0800 Subject: net: documentation: build a directory structure for drivers Documentation/networking/ is full of cryptically named files with driver documentation. This makes finding interesting information at a glance really hard. Move all those files into a directory called device_drivers (since not all drivers are for device) and fix up references. RFC v0.1 -> RFC v1: - also add .txt suffix to the files which are missing it (Quentin) Signed-off-by: Jakub Kicinski Reviewed-by: Quentin Monnet Acked-by: David Ahern Acked-by: Henrik Austad Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt index 01fdc33a41d0..bb7e896cb644 100644 --- a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt +++ b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt @@ -10,7 +10,7 @@ such as network interfaces, crypto accelerator instances, L2 switches, etc. For an overview of the DPAA2 architecture and fsl-mc bus see: -Documentation/networking/dpaa2/overview.rst +Documentation/networking/device_drivers/freescale/dpaa2/overview.rst As described in the above overview, all DPAA2 objects in a DPRC share the same hardware "isolation context" and a 10-bit value called an ICID -- cgit v1.2.3 From 6c9e3e80c526155b14c6af6f55653677707c822b Mon Sep 17 00:00:00 2001 From: Benjamin Gaignard Date: Wed, 14 Nov 2018 10:00:24 +0100 Subject: dt-bindings: hwlock: Document STM32 hwspinlock bindings Add bindings for STM32 hardware spinlock device Reviewed-by: Rob Herring Signed-off-by: Benjamin Gaignard Signed-off-by: Benjamin Gaignard Signed-off-by: Bjorn Andersson --- .../bindings/hwlock/st,stm32-hwspinlock.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt new file mode 100644 index 000000000000..adf4f000ea3d --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt @@ -0,0 +1,23 @@ +STM32 Hardware Spinlock Device Binding +------------------------------------- + +Required properties : +- compatible : should be "st,stm32-hwspinlock". +- reg : the register address of hwspinlock. +- #hwlock-cells : hwlock users only use the hwlock id to represent a specific + hwlock, so the number of cells should be <1> here. +- clock-names : Must contain "hsem". +- clocks : Must contain a phandle entry for the clock in clock-names, see the + common clock bindings. + +Please look at the generic hwlock binding for usage information for consumers, +"Documentation/devicetree/bindings/hwlock/hwlock.txt" + +Example of hwlock provider: + hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hsem"; + }; -- cgit v1.2.3 From 76ee875c2f48c57cbafa35d9c3b34e7202a45a83 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 11 Nov 2018 22:45:38 +0100 Subject: power: reset: gpio-poweroff: add ability to specific active and inactive delays Similar to gpio-reset allow to specify active and inactive delays while keeping the 100ms defaults that were used previously all the time. The dt-properties are named the same as in gpio-reset but get an "-ms" suffix as properties should contain such a suffix specifying its unit. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring Reviewed-by: Moritz Fischer Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt index 6d8980c18c34..3e56c1b34a4c 100644 --- a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt +++ b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt @@ -27,6 +27,8 @@ Optional properties: it to an output when the power-off handler is called. If this optional property is not specified, the GPIO is initialized as an output in its inactive state. +- active-delay-ms: Delay (default 100) to wait after driving gpio active +- inactive-delay-ms: Delay (default 100) to wait after driving gpio inactive - timeout-ms: Time to wait before asserting a WARN_ON(1). If nothing is specified, 3000 ms is used. -- cgit v1.2.3 From 8e49c0b4bbe9482a26e8ad26a99ee99b806f6ac4 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Wed, 31 Oct 2018 20:11:43 -0400 Subject: dt-bindings: power: supply: bq24190_charger: add bq24192 and usb-otg-vbus Add support for the ti,bq24192 variant and a child node for the usb-otg-vbus regulator. Signed-off-by: Brian Masney Reviewed-by: Rob Herring Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/supply/bq24190.txt | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/bq24190.txt b/Documentation/devicetree/bindings/power/supply/bq24190.txt index 9e517d307070..c8ac028bd3c7 100644 --- a/Documentation/devicetree/bindings/power/supply/bq24190.txt +++ b/Documentation/devicetree/bindings/power/supply/bq24190.txt @@ -3,6 +3,7 @@ TI BQ24190 Li-Ion Battery Charger Required properties: - compatible: contains one of the following: * "ti,bq24190" + * "ti,bq24192" * "ti,bq24192i" - reg: integer, I2C address of the charger. - interrupts[-extended]: configuration for charger INT pin. @@ -19,6 +20,12 @@ Optional properties: - ti,system-minimum-microvolt: when power is connected and the battery is below minimum system voltage, the system will be regulated above this setting. +child nodes: +- usb-otg-vbus: + Usage: optional + Description: Regulator that is used to control the VBUS voltage direction for + either USB host mode or for charging on the OTG port. + Notes: - Some circuit boards wire the chip's "OTG" pin high (enabling 500mA default charge current on USB SDP ports, among other features). To simulate this on @@ -39,6 +46,8 @@ Example: interrupts-extended = <&gpiochip 10 IRQ_TYPE_EDGE_FALLING>; monitored-battery = <&bat>; ti,system-minimum-microvolt = <3200000>; + + usb_otg_vbus: usb-otg-vbus { }; }; &twl_gpio { -- cgit v1.2.3 From d0717d73be810f8c814048502f36cf4e10fe5fce Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 13 Nov 2018 13:47:53 +0100 Subject: power: supply: bq24190_charger: add support for bq24196 variant The bq24196 is another variant of the bq24190 charger ic. Its register set is identical to the bq24192 and it even reuses the same part number (0x5). Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/supply/bq24190.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/bq24190.txt b/Documentation/devicetree/bindings/power/supply/bq24190.txt index c8ac028bd3c7..ffe2be408bb6 100644 --- a/Documentation/devicetree/bindings/power/supply/bq24190.txt +++ b/Documentation/devicetree/bindings/power/supply/bq24190.txt @@ -5,6 +5,7 @@ Required properties: * "ti,bq24190" * "ti,bq24192" * "ti,bq24192i" + * "ti,bq24196" - reg: integer, I2C address of the charger. - interrupts[-extended]: configuration for charger INT pin. -- cgit v1.2.3 From 6be57bd2badfc05892f266076c6321c4a9c2431d Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Wed, 14 Nov 2018 17:07:04 +0800 Subject: dt-bindings: power: supply: Add nvmem properties to calibrate FGU Add nvmem properties to calibrate FGU from eFuse controller. Signed-off-by: Baolin Wang Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt b/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt index 98a24004131f..fc35ac577401 100644 --- a/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt +++ b/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt @@ -11,6 +11,8 @@ Required properties: - battery-detect-gpios: GPIO for battery detection. - io-channels: Specify the IIO ADC channel to get temperature. - io-channel-names: Should be "bat-temp". +- nvmem-cells: A phandle to the calibration cells provided by eFuse device. +- nvmem-cell-names: Should be "fgu_calib". - monitored-battery: Phandle of battery characteristics devicetree node. See Documentation/devicetree/bindings/power/supply/battery.txt @@ -47,6 +49,8 @@ Example: battery-detect-gpios = <&pmic_eic 9 GPIO_ACTIVE_HIGH>; io-channels = <&pmic_adc 5>; io-channel-names = "bat-temp"; + nvmem-cells = <&fgu_calib>; + nvmem-cell-names = "fgu_calib"; monitored-battery = <&bat>; }; }; -- cgit v1.2.3 From 36ead91499160b459d66cd70949511cde829204f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 28 Aug 2018 08:45:54 +0200 Subject: ARM: dts: rockchip: add BQ Edison 2 QC devicetree The Edison 2 Quad-Core was a Tablet device released in 2013 by MundoReader using a rk3188 soc. Add a devicetree for it. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 0cc71236d639..4e37938edbe9 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -33,6 +33,10 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; +- bq Edison 2 Quad-Core tablet: + Required root node properties: + - compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; + - ChipSPARK Rayeager PX2 board: Required root node properties: - compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; -- cgit v1.2.3 From a91ae340ad05c24b921f433357ca82a83480ce95 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 30 Nov 2018 11:53:22 +0000 Subject: nvmem: meson-efuse: bindings: add peripheral clock The efuse found in gx SoC requires a peripheral clock to properly operate. We have been able to work without it until now because the clock was on by default, and left on by the CCF. Soon, it will not be the case anymore, so the device needs to claim the clock it needs Signed-off-by: Jerome Brunet Reviewed-by: Rob Herring Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt b/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt index e3298e18de26..2e0723ab3384 100644 --- a/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt +++ b/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt @@ -2,6 +2,8 @@ Required properties: - compatible: should be "amlogic,meson-gxbb-efuse" +- clocks: phandle to the efuse peripheral clock provided by the + clock controller. = Data cells = Are child nodes of eFuse, bindings of which as described in @@ -11,6 +13,7 @@ Example: efuse: efuse { compatible = "amlogic,meson-gxbb-efuse"; + clocks = <&clkc CLKID_EFUSE>; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 9ca22651e134c5d33b8776b63bf7384f8686b5f6 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 3 Dec 2018 22:58:12 +0800 Subject: dt-bindings: rtc: sun6i-rtc: Rewrite clock outputs as a list The clock output section for this binding describes the two outputs in the descriptions for both the #clock-cells and clock-output-names properties. Instead of overlapping information that is hard to read, rewrite the clock outputs as a list of indices and descriptions. The properies can reference this list instead. This will also make it easier to add notes or conditions to the clocks, and also for adding new outputs. Acked-by: Maxime Ripard Tested-by: Corentin Labbe Signed-off-by: Chen-Yu Tsai Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/sun6i-rtc.txt | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt index 12c083c1140a..d3e96459fc66 100644 --- a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt @@ -10,10 +10,12 @@ Required properties: Required properties for new device trees - clocks : phandle to the 32kHz external oscillator -- clock-output-names : names of the LOSC and its external output clocks created -- #clock-cells : must be equals to 1. The RTC provides two clocks: the - LOSC and its external output, with index 0 and 1 - respectively. +- clock-output-names : names of the two clock outputs. See below. +- #clock-cells : must be equal to 1. + +The RTC provides the following clocks at the given indices: +- 0: LOSC +- 1: LOSC external output, known as X32KFOUT in the datasheet. Example: -- cgit v1.2.3 From 347d3570300ee961a5b51a02473761262b06980f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 3 Dec 2018 22:58:13 +0800 Subject: dt-bindings: rtc: sun6i-rtc: Add compatible strings for pre-H6 variants While doing Bluetooth enablement for various boards based on various Allwinner SoCs, minor differences in the RTC modules were found. These include a lack of an external clock output (A31), different internal oscillator frequencies (H3/H5/A64/V3/V3s), different regulator voltage settings (H5/H6), and the presence of miscellaneous registers unrelated to the RTC (A64/R40/H5/H6). The datasheet also describes different number of registers for non-volatile storage, though based on actual experiments the actual number is the same across the board. This patch adds a list of all pre-H6 variants, grouped by the internal oscillator's clock rate, regulator settings, and the presence of the external clock output. Combinations are introduced for the variants that have miscellaneous registers. The RTC block in the H6 also handles the 24 MHz DCXO. This will require more device tree binding changes and will be done later. Acked-by: Maxime Ripard Tested-by: Corentin Labbe Signed-off-by: Chen-Yu Tsai Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/sun6i-rtc.txt | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt index d3e96459fc66..b1eaa443347d 100644 --- a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt @@ -3,7 +3,21 @@ RTC controller for the Allwinner A31 Required properties: -- compatible : Should be "allwinner,sun6i-a31-rtc" +- compatible : Should be one of the following combinations: + - "allwinner,sun6i-a31-rtc" + - "allwinner,sun8i-a23-rtc" + - "allwinner,sun8i-h3-rtc" + - "allwinner,sun8i-r40-rtc", "allwinner,sun8i-h3-rtc" + - "allwinner,sun8i-v3-rtc" + - "allwinner,sun50i-a64-rtc", "allwinner,sun8i-h3-rtc" + - "allwinner,sun50i-h5-rtc" + + Where there are two or more compatible strings, this + denotes the hardware covered by the most specific one + is backward-compatible with the latter ones, and the + implementation for the latter ones can be used, albeit + with reduced functionality. + - reg : physical base address of the controller and length of memory mapped region. - interrupts : IRQ lines for the RTC alarm 0 and alarm 1, in that order. -- cgit v1.2.3 From 5a0923aad7d466b683e52b766290dcdc02453e1b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 3 Dec 2018 22:58:14 +0800 Subject: dt-bindings: rtc: sun6i-rtc: Deprecate external clock output for A31 The A31 does not have an external clock output directly from the RTC. Instead, it has four muxable clock outputs: three (A, B, C) are controlled from the CCU, and the last (D) is controlled from the PRCM. Deprecate the usage of the external clock output for the A31 compatible. Acked-by: Maxime Ripard Tested-by: Corentin Labbe Signed-off-by: Chen-Yu Tsai Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/sun6i-rtc.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt index b1eaa443347d..dba4d32cfbad 100644 --- a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt @@ -24,12 +24,14 @@ Required properties: Required properties for new device trees - clocks : phandle to the 32kHz external oscillator -- clock-output-names : names of the two clock outputs. See below. +- clock-output-names : names of up to two clock outputs. See below. - #clock-cells : must be equal to 1. The RTC provides the following clocks at the given indices: - 0: LOSC - 1: LOSC external output, known as X32KFOUT in the datasheet. + This clock is not available on the A31 and is deprecated for old + device trees still using the "allwinner,sun6i-a31-rtc" compatible. Example: @@ -37,7 +39,7 @@ rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <0 40 4>, <0 41 4>; - clock-output-names = "osc32k", "osc32k-out"; + clock-output-names = "osc32k"; clocks = <&ext_osc32k>; #clock-cells = <1>; }; -- cgit v1.2.3 From 9cd3558678385329709b6d52f639d1f918e04aae Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 3 Dec 2018 22:58:15 +0800 Subject: dt-bindings: rtc: sun6i-rtc: Export internal RC oscillator Experiments showed that on at least the H3/H5/A64 the RTC's internal oscillator also feeds the CPUS mux in the PRCM. Export this clock through the device tree, instead of having to use a dummy fixed-clock device node, for the PRCM to consume. This will properly describe the relationship between the clocks. Tested-by: Corentin Labbe Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/sun6i-rtc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt index dba4d32cfbad..ceb38abf1ea2 100644 --- a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt @@ -24,7 +24,7 @@ Required properties: Required properties for new device trees - clocks : phandle to the 32kHz external oscillator -- clock-output-names : names of up to two clock outputs. See below. +- clock-output-names : names of up to three clock outputs. See below. - #clock-cells : must be equal to 1. The RTC provides the following clocks at the given indices: @@ -32,6 +32,7 @@ The RTC provides the following clocks at the given indices: - 1: LOSC external output, known as X32KFOUT in the datasheet. This clock is not available on the A31 and is deprecated for old device trees still using the "allwinner,sun6i-a31-rtc" compatible. +- 2: InternalOSC, or internal RC oscillator (A64/H3/H5 only) Example: -- cgit v1.2.3 From 1deb430d291270f9d0067061a5dc7409819dfcfb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 26 Sep 2018 09:21:44 +0100 Subject: dt-bindings: arm: renesas: Document iWave RZ/G1N SOM Document the iW-RainboW-G20M-RZ/G1N Qseven device tree bindings, listing it as a supported system on module. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index f5e0f82fd503..4cfb56787a90 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -101,6 +101,8 @@ Boards: compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) compatible = "iwave,g20m", "renesas,r8a7743" + - iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven) + compatible = "iwave,g20m", "renesas,r8a7744" - Kingfisher (SBEV-RCAR-KF-M03) compatible = "shimafuji,kingfisher" - Koelsch (RTP0RC7791SEB00010S) -- cgit v1.2.3 From ea456bf918e31a0f755c5c02963b4e10513fa82c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 26 Sep 2018 11:44:46 +0100 Subject: dt-bindings: arm: renesas: Document iW-RainboW-G20D-Qseven-RZG1N board Document the iW-RainboW-G20D-Qseven-RZG1N device tree bindings, listing it as a supported board. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 4cfb56787a90..144f045a9f4b 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -101,6 +101,8 @@ Boards: compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) compatible = "iwave,g20m", "renesas,r8a7743" + - iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven) + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744" - iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven) compatible = "iwave,g20m", "renesas,r8a7744" - Kingfisher (SBEV-RCAR-KF-M03) -- cgit v1.2.3 From 74791d15fd7c405511e3cc097c2f043171ecbdb0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 3 Dec 2018 15:32:14 -0600 Subject: dt-bindings: arm: renesas: Move 'renesas,prr' binding to its own doc In preparation to convert board-level bindings to json-schema, move various misc SoC bindings out to their own file. Signed-off-by: Rob Herring Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- .../devicetree/bindings/arm/renesas,prr.txt | 20 ++++++++++++++++++++ Documentation/devicetree/bindings/arm/shmobile.txt | 18 ------------------ 2 files changed, 20 insertions(+), 18 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.txt b/Documentation/devicetree/bindings/arm/renesas,prr.txt new file mode 100644 index 000000000000..08e482e953ca --- /dev/null +++ b/Documentation/devicetree/bindings/arm/renesas,prr.txt @@ -0,0 +1,20 @@ +Renesas Product Register + +Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that +allows to retrieve SoC product and revision information. If present, a device +node for this register should be added. + +Required properties: + - compatible: Must be one of: + "renesas,prr" + "renesas,bsid" + - reg: Base address and length of the register block. + + +Examples +-------- + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 144f045a9f4b..92cda17870d3 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -153,21 +153,3 @@ Boards: compatible = "renesas,v3msk", "renesas,r8a77970" - Wheat (RTP0RC7792ASKB0000JE) compatible = "renesas,wheat", "renesas,r8a7792" - - -Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that -allows to retrieve SoC product and revision information. If present, a device -node for this register should be added. - -Required properties: - - compatible: Must be "renesas,prr" or "renesas,bsid" - - reg: Base address and length of the register block. - - -Examples --------- - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; -- cgit v1.2.3 From eab8e354a8c7b4496cb68a6f5adc5ec3a1f59151 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 6 Dec 2018 13:24:25 +0100 Subject: ASoC: dt-bindings: cs4270: use 'reset-gpios' rather than 'reset-gpio' Bindings should use 'reset-gpios', not 'reset-gpio'. The driver needs to switch to the gpiod consume API to handle this correctly. Signed-off-by: Daniel Mack Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/cs4270.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/cs4270.txt b/Documentation/devicetree/bindings/sound/cs4270.txt index 6b222f9b8ef5..c33770ec4c3c 100644 --- a/Documentation/devicetree/bindings/sound/cs4270.txt +++ b/Documentation/devicetree/bindings/sound/cs4270.txt @@ -10,8 +10,8 @@ Required properties: Optional properties: - - reset-gpio : a GPIO spec for the reset pin. If specified, it will be - deasserted before communication to the codec starts. + - reset-gpios : a GPIO spec for the reset pin. If specified, it will be + deasserted before communication to the codec starts. Example: -- cgit v1.2.3 From db097f95b4b81c5371928449706fabfa576cd65c Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 6 Dec 2018 13:24:56 +0100 Subject: ASoC: dt-bindings: ak4104: use 'reset-gpios' rather than 'reset-gpio' Bindings should use 'reset-gpios', not 'reset-gpio'. The driver needs to switch to the gpiod consume API to handle this correctly. Signed-off-by: Daniel Mack Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/ak4104.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/ak4104.txt b/Documentation/devicetree/bindings/sound/ak4104.txt index deca5e18f304..ae5f7f057dc3 100644 --- a/Documentation/devicetree/bindings/sound/ak4104.txt +++ b/Documentation/devicetree/bindings/sound/ak4104.txt @@ -12,8 +12,8 @@ Required properties: Optional properties: - - reset-gpio : a GPIO spec for the reset pin. If specified, it will be - deasserted before communication to the device starts. + - reset-gpios : a GPIO spec for the reset pin. If specified, it will be + deasserted before communication to the device starts. Example: -- cgit v1.2.3 From 6ab4a3502923c20c5a6921868e787e5fd033409b Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Tue, 4 Dec 2018 15:54:42 +0200 Subject: spi: Update NPCM PSPI controller documentation Update the PSPI NPCM binding document of the spi aliases use to define the spi ID number. Signed-off-by: Tomer Maimon Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt index 99606b22e5c2..1fd9a4406a1d 100644 --- a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt @@ -19,8 +19,16 @@ Optional properties: - clock-frequency : Input clock frequency to the PSPI block in Hz. Default is 25000000 Hz. +Aliases: +- All the SPI controller nodes should be represented in the aliases node using + the following format 'spi{n}' withe the correct numbered in "aliases" node. + Example: +aliases { + spi0 = &spi0; +}; + spi0: spi@f0200000 { compatible = "nuvoton,npcm750-pspi"; reg = <0xf0200000 0x1000>; -- cgit v1.2.3 From fefbc0b4bcb3c0cc45bed906af46e7cd627ac4bc Mon Sep 17 00:00:00 2001 From: Gilad Ben-Yossef Date: Tue, 13 Nov 2018 09:40:36 +0000 Subject: dt-bindings: crypto: ccree: add dt bindings for ccree 703 Add device tree bindings associating Arm TrustZone CryptoCell 703 with the ccree driver. Signed-off-by: Gilad Ben-Yossef Reviewed-by: Rob Herring Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/crypto/arm-cryptocell.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt index 0ac06ec05272..6130e6eb4af8 100644 --- a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt +++ b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt @@ -3,6 +3,7 @@ Arm TrustZone CryptoCell cryptographic engine Required properties: - compatible: Should be one of - "arm,cryptocell-713-ree" + "arm,cryptocell-703-ree" "arm,cryptocell-712-ree" "arm,cryptocell-710-ree" "arm,cryptocell-630p-ree" -- cgit v1.2.3 From 8c4cf161a8b42749e986a3503f6cd4f3b5682fe3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 7 Dec 2018 16:47:19 +0800 Subject: dt-bindings: rtc: sun6i-rtc: Fix register range in example The register range for the RTC extends beyond 0x54. Use the size from the user manual's memory map instead. Fixes: 9765d2d94309 ("rtc: sun6i: Add sun6i RTC driver") Signed-off-by: Chen-Yu Tsai Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/sun6i-rtc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt index ceb38abf1ea2..6b732c41392b 100644 --- a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt @@ -38,7 +38,7 @@ Example: rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; + reg = <0x01f00000 0x400>; interrupts = <0 40 4>, <0 41 4>; clock-output-names = "osc32k"; clocks = <&ext_osc32k>; -- cgit v1.2.3 From e96fd5ce5ffab81ca1153eda28805dd3f073f03e Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 29 Nov 2018 00:48:40 +0200 Subject: dt-bindings: gpio: lpc18xx: describe interrupt controllers of GPIO controller From LPC18xx and LPC43xx User Manuals the GPIO controller consists of the following weakly connected blocks: * GPIO pin interrupt block at 0x40087000, * GPIO GROUP0 interrupt block at 0x40088000, * GPIO GROUP1 interrupt block at 0x40089000, * GPIO port block at 0x400F4000. While all 4 sub-controller blocks have their own I/O addresses, moreover all 3 interrupt blocks are APB0 peripherals and high-speed GPIO block is an AHB slave, according to the hardware manual interrupt controllers and GPIO controller block are seen as a single device, all 4 sub-controllers have the shared reset signal RGU #28 and the same shared clock to access registers CLK_Mx_GPIO on CCU1. The change adds descriptions of the currently missing interrupt controller blocks found on GPIO controller, new added properties are 'reg-names', 'resets', 'interrupt-controller' and '#interrupt-cells', also the example is updated to reflect the changes in device tree binding description. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/nxp,lpc1850-gpio.txt | 38 +++++++++++++++++----- 1 file changed, 29 insertions(+), 9 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt b/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt index eb7cdd69e10b..627efc78ecf2 100644 --- a/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt @@ -3,12 +3,24 @@ NXP LPC18xx/43xx GPIO controller Device Tree Bindings Required properties: - compatible : Should be "nxp,lpc1850-gpio" -- reg : Address and length of the register set for the device -- clocks : Clock specifier (see clock bindings for details) -- gpio-controller : Marks the device node as a GPIO controller. -- #gpio-cells : Should be two - - First cell is the GPIO line number - - Second cell is used to specify polarity +- reg : List of addresses and lengths of the GPIO controller + register sets +- reg-names : Should be "gpio", "gpio-pin-ic", "gpio-group0-ic" and + "gpio-gpoup1-ic" +- clocks : Phandle and clock specifier pair for GPIO controller +- resets : Phandle and reset specifier pair for GPIO controller +- gpio-controller : Marks the device node as a GPIO controller +- #gpio-cells : Should be two: + - The first cell is the GPIO line number + - The second cell is used to specify polarity +- interrupt-controller : Marks the device node as an interrupt controller +- #interrupt-cells : Should be two: + - The first cell is an interrupt number within + 0..9 range, for GPIO pin interrupts it is equal + to 'nxp,gpio-pin-interrupt' property value of + GPIO pin configuration, 8 is for GPIO GROUP0 + interrupt, 9 is for GPIO GROUP1 interrupt + - The second cell is used to specify interrupt type Optional properties: - gpio-ranges : Mapping between GPIO and pinctrl @@ -19,21 +31,29 @@ Example: gpio: gpio@400f4000 { compatible = "nxp,lpc1850-gpio"; - reg = <0x400f4000 0x4000>; + reg = <0x400f4000 0x4000>, <0x40087000 0x1000>, + <0x40088000 0x1000>, <0x40089000 0x1000>; + reg-names = "gpio", "gpio-pin-ic", + "gpio-group0-ic", "gpio-gpoup1-ic"; clocks = <&ccu1 CLK_CPU_GPIO>; + resets = <&rgu 28>; gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, ... <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; }; gpio_joystick { - compatible = "gpio-keys-polled"; + compatible = "gpio-keys"; ... - button@0 { + button0 { ... + interrupt-parent = <&gpio>; + interrupts = <1 IRQ_TYPE_EDGE_BOTH>; gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; }; }; -- cgit v1.2.3 From 3ba37c2bcb0cb5dc9b278f730e520f61b2597fe3 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 6 Aug 2018 12:56:27 -0400 Subject: media: rcar-csi2: add R8A77980 support Add the R-Car V3H (AKA R8A77980) SoC support to the R-Car CSI2 driver. Signed-off-by: Sergei Shtylyov Acked-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt b/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt index 282448911267..541d936b62e8 100644 --- a/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt +++ b/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt @@ -12,6 +12,7 @@ Mandatory properties - "renesas,r8a7796-csi2" for the R8A7796 device. - "renesas,r8a77965-csi2" for the R8A77965 device. - "renesas,r8a77970-csi2" for the R8A77970 device. + - "renesas,r8a77980-csi2" for the R8A77980 device. - "renesas,r8a77990-csi2" for the R8A77990 device. - reg: the register base and size for the device registers -- cgit v1.2.3 From a383096c98b4b44151a9fde106b01500ccc2a060 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 6 Aug 2018 14:48:20 -0400 Subject: media: rcar-vin: add R8A77980 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the R8A77980 SoC support to the R-Car VIN driver. Signed-off-by: Sergei Shtylyov Acked-by: Niklas Söderlund Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/rcar_vin.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt index 7c878ca29f45..0dd84a183ca7 100644 --- a/Documentation/devicetree/bindings/media/rcar_vin.txt +++ b/Documentation/devicetree/bindings/media/rcar_vin.txt @@ -24,6 +24,7 @@ on Gen3 platforms to a CSI-2 receiver. - "renesas,vin-r8a7796" for the R8A7796 device - "renesas,vin-r8a77965" for the R8A77965 device - "renesas,vin-r8a77970" for the R8A77970 device + - "renesas,vin-r8a77980" for the R8A77980 device - "renesas,vin-r8a77990" for the R8A77990 device - "renesas,vin-r8a77995" for the R8A77995 device - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible -- cgit v1.2.3 From 66ca86fe37db23cfdcf1170ec05db7ab0e658073 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 5 Dec 2018 04:24:40 -0500 Subject: media: dt-bindings: media: cedrus: Add compatibles for the A64 and H5 This introduces two new compatibles for the cedrus driver, for the A64 and H5 platforms. Signed-off-by: Paul Kocialkowski Reviewed-by: Rob Herring Acked-by: Maxime Ripard Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/cedrus.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/cedrus.txt b/Documentation/devicetree/bindings/media/cedrus.txt index a089a0c1ff05..b3c0635dcd0e 100644 --- a/Documentation/devicetree/bindings/media/cedrus.txt +++ b/Documentation/devicetree/bindings/media/cedrus.txt @@ -11,6 +11,8 @@ Required properties: - "allwinner,sun7i-a20-video-engine" - "allwinner,sun8i-a33-video-engine" - "allwinner,sun8i-h3-video-engine" + - "allwinner,sun50i-a64-video-engine" + - "allwinner,sun50i-h5-video-engine" - reg : register base and length of VE; - clocks : list of clock specifiers, corresponding to entries in the clock-names property; -- cgit v1.2.3 From c3e566c8cb553026cf530f01c80b665a2a0926f9 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Mon, 3 Dec 2018 12:47:40 +0100 Subject: dt-bindings: iio: accel: use a generic node name for lis302 The example should follow the practice or using a generic node name instead of the precise programming model, as recommended by the DTSpec. Signed-off-by: Lubomir Rintel Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/accel/lis302.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/accel/lis302.txt b/Documentation/devicetree/bindings/iio/accel/lis302.txt index dfdce67826ba..764e28ec1a0a 100644 --- a/Documentation/devicetree/bindings/iio/accel/lis302.txt +++ b/Documentation/devicetree/bindings/iio/accel/lis302.txt @@ -64,7 +64,7 @@ Optional properties for all bus drivers: Example for a SPI device node: - lis302@0 { + accelerometer@0 { compatible = "st,lis302dl-spi"; reg = <0>; spi-max-frequency = <1000000>; @@ -89,7 +89,7 @@ Example for a SPI device node: Example for a I2C device node: - lis331dlh: lis331dlh@18 { + lis331dlh: accelerometer@18 { compatible = "st,lis331dlh", "st,lis3lv02d"; reg = <0x18>; Vdd-supply = <&lis3_reg>; -- cgit v1.2.3 From 8ff7754ae1f57c50a977aab7565ab84376ed6af6 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 7 Nov 2018 05:35:17 +0000 Subject: dt-bindings: pci: layerscape-pci: add compatible strings "fsl,ls1043a-pcie" The PCIe compatible string for LS1043A was lost, so add it. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 66df1e81e0b8..5eb1c202932f 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -18,6 +18,7 @@ Required properties: "fsl,ls2088a-pcie" "fsl,ls1088a-pcie" "fsl,ls1046a-pcie" + "fsl,ls1043a-pcie" "fsl,ls1012a-pcie" - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an -- cgit v1.2.3 From ac8ed2824e8d7655bbf4eb6d22ee08ca3f1f63d4 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 7 Nov 2018 05:35:22 +0000 Subject: dt-bindings: pci: layerscape-pci: removed compatible string "snps,dw-pcie" Removed the compatible string "snps,dw-pcie", it is for the reference platform driver for PCI RC IP Protoyping Kits based on the ARC SDP, so it is not suitable for all platform with designware PCIe controller, and platform vendors have themselves' drivers. The compatible string "snsp,dw-pcie" was added by mistake and it's not matched that time, but it is matched because PCIe drivers has been collected recently. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 5eb1c202932f..9b2b8d66d1f4 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -13,8 +13,8 @@ information. Required properties: - compatible: should contain the platform identifier such as: - "fsl,ls1021a-pcie", "snps,dw-pcie" - "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" + "fsl,ls1021a-pcie" + "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" "fsl,ls2088a-pcie" "fsl,ls1088a-pcie" "fsl,ls1046a-pcie" @@ -36,7 +36,7 @@ Required properties: Example: pcie@3400000 { - compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1021a-pcie"; reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; -- cgit v1.2.3 From d87cf8ce52820256dcff3a52871d67e3994e39e0 Mon Sep 17 00:00:00 2001 From: Jan Tuerk Date: Tue, 27 Nov 2018 16:04:02 +0100 Subject: dt-bindings: arm: Document emtrion emCON-MX6 bindings Document the compatible strings for emtrion emCON-MX6 SoM's. Signed-off-by: Jan Tuerk Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/emtrion.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt new file mode 100644 index 000000000000..83329aefc483 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/emtrion.txt @@ -0,0 +1,12 @@ +Emtrion Devicetree Bindings +=========================== + +emCON Series: +------------- + +Required root node properties + - compatible: + - "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base + - "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base -- cgit v1.2.3 From 2bf5751726e8face217a39f2132df643b995d8bc Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Sat, 10 Nov 2018 15:12:56 +0000 Subject: dt-bindings: fsl: add compatible for imx7ulp evk Add compatible string for imx7ulp evk board. Cc: devicetree@vger.kernel.org Cc: Shawn Guo Acked-by: Rob Herring Signed-off-by: Dong Aisheng Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index 5074aeecd327..7fbc42484001 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -101,6 +101,10 @@ i.MX7 SabreSD Board Required root node properties: - compatible = "fsl,imx7d-sdb", "fsl,imx7d"; +i.MX7ULP Evaluation Kit +Required root node properties: + - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; + Generic i.MX boards ------------------- @@ -123,6 +127,10 @@ i.MX6q generic board Required root node properties: - compatible = "fsl,imx6q"; +i.MX7ULP generic board +Required root node properties: + - compatible = "fsl,imx7ulp"; + Freescale Vybrid Platform Device Tree Bindings ---------------------------------------------- -- cgit v1.2.3 From 61ccb001534b7d555e01d013ecb7f94bbf3d1bbe Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Sat, 10 Nov 2018 15:13:00 +0000 Subject: dt-bindings: fsl: add imx7ulp pm related components bindings Add imx7ulp pm related components bindings. Cc: Shawn Guo Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- .../bindings/arm/freescale/fsl,imx7ulp-pm.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt new file mode 100644 index 000000000000..75195bee116f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt @@ -0,0 +1,23 @@ +Freescale i.MX7ULP Power Management Components +---------------------------------------------- + +The Multi-System Mode Controller (MSMC) is responsible for sequencing +the MCU into and out of all stop and run power modes. Specifically, it +monitors events to trigger transitions between power modes while +controlling the power, clocks, and memories of the MCU to achieve the +power consumption and functionality of that mode. + +The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or +Standby modes for either Cortex family. Run, Wait, and Stop are the +common terms used for the primary operating modes of Kinetis +microcontrollers. + +Required properties: +- compatible: Should be "fsl,imx7ulp-smc1". +- reg: Specifies base physical address and size of the register sets. + +Example: +smc1: smc1@40410000 { + compatible = "fsl,imx7ulp-smc1"; + reg = <0x40410000 0x1000>; +}; -- cgit v1.2.3 From f1518cd84b44d6c28fb40e0551a9785bc38f55af Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Tue, 4 Dec 2018 11:52:12 +0530 Subject: dt-bindings: arm-smmu: Add bindings for qcom,smmu-v2 Add bindings doc for Qcom's smmu-v2 implementation. Signed-off-by: Vivek Gautam Reviewed-by: Tomasz Figa Tested-by: Srinivas Kandagatla Reviewed-by: Rob Herring Reviewed-by: Robin Murphy Signed-off-by: Will Deacon --- .../devicetree/bindings/iommu/arm,smmu.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 8a6ffce12af5..a6504b37cc21 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -17,10 +17,16 @@ conditions. "arm,mmu-401" "arm,mmu-500" "cavium,smmu-v2" + "qcom,smmu-v2" depending on the particular implementation and/or the version of the architecture implemented. + Qcom SoCs must contain, as below, SoC-specific compatibles + along with "qcom,smmu-v2": + "qcom,msm8996-smmu-v2", "qcom,smmu-v2", + "qcom,sdm845-smmu-v2", "qcom,smmu-v2". + - reg : Base address and size of the SMMU. - #global-interrupts : The number of global interrupts exposed by the @@ -71,6 +77,22 @@ conditions. or using stream matching with #iommu-cells = <2>, and may be ignored if present in such cases. +- clock-names: List of the names of clocks input to the device. The + required list depends on particular implementation and + is as follows: + - for "qcom,smmu-v2": + - "bus": clock required for downstream bus access and + for the smmu ptw, + - "iface": clock required to access smmu's registers + through the TCU's programming interface. + - unspecified for other implementations. + +- clocks: Specifiers for all clocks listed in the clock-names property, + as per generic clock bindings. + +- power-domains: Specifiers for power domains required to be powered on for + the SMMU to operate, as per generic power domain bindings. + ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : @@ -137,3 +159,20 @@ conditions. iommu-map = <0 &smmu3 0 0x400>; ... }; + + /* Qcom's arm,smmu-v2 implementation */ + smmu4: iommu@d00000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0xd00000 0x10000>; + + #global-interrupts = <1>; + interrupts = , + , + ; + #iommu-cells = <1>; + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc SMMU_MDP_AHB_CLK>; + clock-names = "bus", "iface"; + }; -- cgit v1.2.3 From 6c0c5dc33ff42af49243e94842d0ebdb153189ea Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Thu, 29 Nov 2018 21:58:57 +0200 Subject: dt-bindings: eeprom: at24: add "atmel,24c2048" compatible string Add new compatible to the device tree bindings. Signed-off-by: Adrian Bunk Acked-by: Rob Herring Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/eeprom/at24.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt index aededdbc262b..f9a7c984274c 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.txt +++ b/Documentation/devicetree/bindings/eeprom/at24.txt @@ -27,6 +27,7 @@ Required properties: "atmel,24c256", "atmel,24c512", "atmel,24c1024", + "atmel,24c2048", If is not "atmel", then a fallback must be used with the same and "atmel" as manufacturer. -- cgit v1.2.3 From a29be9185d195bf5abd5ff5482a26800d58bac19 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 15 Nov 2018 15:30:27 +0100 Subject: clk: imx6q: optionally get CCM inputs via standard clock handles When specifying external clock inputs to the CCM the current code requires the clocks to be in a "clocks" child node of the DT root. This is not really conformant with DT best practices. To avoid the need to deviate from those best practices, allow the clock inputs to be specified via standard clock handles. This is in line with how drivers of the later CCM driver revisions on newer i.MX SoCs handle this. As we can't retroactively change the DT binding, allow this as an option with a fallback to the old way of how this has been handled. Signed-off-by: Lucas Stach Acked-by: Rob Herring Reviewed-by: Dong Aisheng Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/imx6q-clock.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index e1308346e00d..13d36d4c6991 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt @@ -13,6 +13,9 @@ Optional properties: management IC (PMIC) triggered via PMIC_STBY_REQ signal. Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should be using "syscon-poweroff" driver instead. +- clocks: list of clock specifiers, must contain an entry for each entry + in clock-names +- clock-names: valid names are "osc", "ckil", "ckih1", "anaclk1" and "anaclk2" The clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h -- cgit v1.2.3 From a324d6e454aa986d64cb650caa8ed7150023b3f3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 10 Dec 2018 14:43:05 +0100 Subject: net: dsa: ksz: Add optional reset GPIO to Microchip KSZ switch binding Add optional reset GPIO, as such a signal is available on the KSZ switches. Signed-off-by: Marek Vasut Cc: Andrew Lunn Cc: Florian Fainelli Cc: Woojung Huh Cc: David S. Miller Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/dsa/ksz.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dsa/ksz.txt b/Documentation/devicetree/bindings/net/dsa/ksz.txt index ac145b885e95..0f407fb371ce 100644 --- a/Documentation/devicetree/bindings/net/dsa/ksz.txt +++ b/Documentation/devicetree/bindings/net/dsa/ksz.txt @@ -8,6 +8,10 @@ Required properties: - "microchip,ksz9477" - "microchip,ksz9897" +Optional properties: + +- reset-gpios : Should be a gpio specifier for a reset line + See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional required and optional properties. -- cgit v1.2.3 From 27b4feb7fe373e1ed92b9362b1e33cead271ac84 Mon Sep 17 00:00:00 2001 From: Stefano Stabellini Date: Mon, 3 Dec 2018 14:26:09 -0800 Subject: devicetree,xen: add xen,shared-memory binding Introduce a device tree binding for Xen reserved-memory regions. They are used to share memory across VMs from the VM config files. (See static_shm config option.) Signed-off-by: Stefano Stabellini Cc: julien.grall@arm.com Cc: devicetree@vger.kernel.org Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: xen-devel@lists.xen.org Signed-off-by: Rob Herring --- .../bindings/reserved-memory/xen,shared-memory.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/reserved-memory/xen,shared-memory.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reserved-memory/xen,shared-memory.txt b/Documentation/devicetree/bindings/reserved-memory/xen,shared-memory.txt new file mode 100644 index 000000000000..d483a2103d70 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/xen,shared-memory.txt @@ -0,0 +1,24 @@ +* Xen hypervisor reserved-memory binding + +Expose one or more memory regions as reserved-memory to the guest +virtual machine. Typically, a region is configured at VM creation time +to be a shared memory area across multiple virtual machines for +communication among them. + +For each of these pre-shared memory regions, a range is exposed under +the /reserved-memory node as a child node. Each range sub-node is named +xen-shmem@
and has the following properties: + +- compatible: + compatible = "xen,shared-memory-v1" + +- reg: + the base guest physical address and size of the shared memory region + +- xen,offset: (borrower VMs only) + 64 bit integer offset within the owner virtual machine's shared + memory region used for the mapping in the borrower VM. + +- xen,id: + a string that identifies the shared memory region as specified in + the VM config file -- cgit v1.2.3 From 2cb5e4743ab52d3a43ef25f229f6770fd9ca0065 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Mon, 3 Dec 2018 12:47:36 +0100 Subject: dt-bindings: rtc: use a generic node name for ds1307 The example should follow the practice or using a generic node name instead of the precise programming model, as recommended by the DTSpec. Signed-off-by: Lubomir Rintel Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/rtc-ds1307.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt b/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt index eebfbe04207a..eaee19b60960 100644 --- a/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt +++ b/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt @@ -35,7 +35,7 @@ Optional properties: Should be given if internal trickle charger diode should be disabled Example: - rtc1: ds1339@68 { + ds1339: rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; interrupt-parent = <&gpio4>; -- cgit v1.2.3 From bae5e94bea188e652d798eeb4b92b88a355591f6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 7 Dec 2018 11:27:43 +0000 Subject: dt-bindings: rtc: pcf85363: Document pcf85263 real-time clock The pcf85263 RTC is compatible with the pcf85363 RTC. The difference between the pcf85263 and pcf85363 RTC is that the latter has 64 bytes more RAM. This renders them incompatible from a DT point of view. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Reviewed-by: Simon Horman Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/pcf85363.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/pcf85363.txt b/Documentation/devicetree/bindings/rtc/pcf85363.txt index 76fdabc59742..94adc1cf93d9 100644 --- a/Documentation/devicetree/bindings/rtc/pcf85363.txt +++ b/Documentation/devicetree/bindings/rtc/pcf85363.txt @@ -1,8 +1,8 @@ -NXP PCF85363 Real Time Clock +NXP PCF85263/PCF85363 Real Time Clock ============================ Required properties: -- compatible: Should contain "nxp,pcf85363". +- compatible: Should contain "nxp,pcf85263" or "nxp,pcf85363". - reg: I2C address for chip. Optional properties: -- cgit v1.2.3 From 4dddb862d3e3438129927bfcce6ee2c2c7064eaf Mon Sep 17 00:00:00 2001 From: Peter Chen Date: Tue, 16 Oct 2018 12:30:37 +0800 Subject: doc: usb: ci-hdrc-usb2: Add pinctrl properties for HSIC pin groups For USB HSIC, the data and strobe pin needs to be pulled down at default, we consider it as "idle" state. When the USB host is ready to be used, the strobe pin needs to be pulled up, we consider it as "active" state. Signed-off-by: Peter Chen --- .../devicetree/bindings/usb/ci-hdrc-usb2.txt | 31 +++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index 529e51879fb2..3381b9618b5b 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -80,7 +80,10 @@ Optional properties: controller. It's expected that a mux state of 0 indicates device mode and a mux state of 1 indicates host mode. - mux-control-names: Shall be "usb_switch" if mux-controls is specified. -- pinctrl-names: Names for optional pin modes in "default", "host", "device" +- pinctrl-names: Names for optional pin modes in "default", "host", "device". + In case of HSIC-mode, "idle" and "active" pin modes are mandatory. In this + case, the "idle" state needs to pull down the data and strobe pin + and the "active" state needs to pull up the strobe pin. - pinctrl-n: alternate pin modes i.mx specific properties @@ -111,3 +114,29 @@ Example: mux-controls = <&usb_switch>; mux-control-names = "usb_switch"; }; + +Example for HSIC: + + usb@2184400 { + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184400 0x200>; + interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_USBOH3>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc 2>; + phy_type = "hsic"; + dr_mode = "host"; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_idle>; + pinctrl-1 = <&pinctrl_usbh2_active>; + #address-cells = <1>; + #size-cells = <0>; + + usbnet: smsc@1 { + compatible = "usb424,9730"; + reg = <1>; + }; + }; -- cgit v1.2.3 From a82bf696aa39b08c0dfce5569525e61368c6827f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 4 Dec 2018 09:31:29 +0100 Subject: usb: chipidea: imx: support configuring for active low oc signal MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The status quo on i.MX6 is that if "over-current-active-high" is specified in the device tree this is configured as expected. If the property is missing polarity isn't changed and so the polarity is kept as setup by the bootloader. Reset default is active high, so active low can only be used with help by the bootloader. On i.MX7 it is similar, but there disabling of over current detection has a similar inconsistency. This patch introduces a new property that allows to explicitly configure for active low over current detection and consistently sets this up. In the absence of an explicit configuration the bit is kept as is. On i.MX7 over current detection is used unless disabled in the device tree. Signed-off-by: Uwe Kleine-König Signed-off-by: Peter Chen --- Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index 3381b9618b5b..adae82385dd6 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -90,8 +90,9 @@ i.mx specific properties - fsl,usbmisc: phandler of non-core register device, with one argument that indicate usb controller index - disable-over-current: disable over current detect -- over-current-active-high: over current signal polarity is high active, - typically over current signal polarity is low active. +- over-current-active-low: over current signal polarity is active low. +- over-current-active-high: over current signal polarity is active high. + It's recommended to specify the over current polarity. - external-vbus-divider: enables off-chip resistor divider for Vbus Example: -- cgit v1.2.3 From f72f4f1ae498a3c93c23c3d0e600df92977e86b1 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 4 Dec 2018 10:16:57 -0500 Subject: drm/msm/mdp4: add lcdc-align-lsb flag to control lane alignment This allows controlling which of the 8 lanes are used for 6 bit color. Signed-off-by: Jonathan Marek Reviewed-by: Rob Herring Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/mdp4.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.txt b/Documentation/devicetree/bindings/display/msm/mdp4.txt index 3c341a15ccdc..b07eeb38f709 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp4.txt +++ b/Documentation/devicetree/bindings/display/msm/mdp4.txt @@ -38,6 +38,8 @@ Required properties: Optional properties: - clock-names: the following clocks are optional: * "lut_clk" +- qcom,lcdc-align-lsb: Boolean value indicating that LSB alignment should be + used for LCDC. This is only valid for 18bpp panels. Example: -- cgit v1.2.3 From e888c279579e9c2409899eb3a5e9ad5b9f91260e Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 4 Dec 2018 10:17:01 -0500 Subject: dt-bindings: display: msm/gpu: document amd,imageon compatible Document the new amd,imageon compatible, used for non-qcom hardware that uses the drm/msm driver (iMX5). Signed-off-by: Jonathan Marek Reviewed-by: Rob Herring Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/gpu.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 43fac0fe09bb..ac8df3b871f9 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -1,11 +1,13 @@ Qualcomm adreno/snapdragon GPU Required properties: -- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" +- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or + "amd,imageon-XYZ.W", "amd,imageon" for example: "qcom,adreno-306.0", "qcom,adreno" Note that you need to list the less specific "qcom,adreno" (since this is what the device is matched on), in addition to the more specific with the chip-id. + If "amd,imageon" is used, there should be no top level msm device. - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt signal from the gpu. - clocks: device clocks -- cgit v1.2.3 From fb42b5354d71b09d3dcfcf4e38b1e98b277a0fc8 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 4 Dec 2018 14:42:27 -0800 Subject: dt-bindings: msm/dsi: Add ref clock for PHYs Allow the PHY drivers to get the ref clock from the DT. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Rob Herring Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd8..9ae946942720 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -106,6 +106,7 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + * "ref" (only required for new DTS files/entries) For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: -- cgit v1.2.3 From 7841b88a8fdddc0e7f3377fc42efe4cb3be1ed8b Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 26 Nov 2018 15:35:06 -0200 Subject: ARM: dts: rockchip: Add internal timer support for rv1108 Add support for the internal timer peripheral on RV1108. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt index 16a5f4577a61..d65fdce7c7f0 100644 --- a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt +++ b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt @@ -2,6 +2,7 @@ Rockchip rk timer Required properties: - compatible: should be: + "rockchip,rv1108-timer", "rockchip,rk3288-timer": for Rockchip RV1108 "rockchip,rk3036-timer", "rockchip,rk3288-timer": for Rockchip RK3036 "rockchip,rk3066-timer", "rockchip,rk3288-timer": for Rockchip RK3066 "rockchip,rk3188-timer", "rockchip,rk3288-timer": for Rockchip RK3188 -- cgit v1.2.3 From 3ca3f86f7f4856222a8b697d60d32717160a1a1b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 23 Nov 2018 13:51:38 +0100 Subject: dt-bindings: i2c: Use correct vendor prefix for Atmel The "at," prefix was never correct for Atmel, so fix the few occurrences that got it wrong. Use "atmel," instead. Signed-off-by: Thierry Reding Signed-off-by: Bartosz Golaszewski Acked-by: Peter Rosin [wsa: merged two patches into one, dropped 'trivial-devices' hunk which needs to go in seperately] Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-at91.txt | 2 +- Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt | 4 ++-- Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt | 2 +- Documentation/devicetree/bindings/i2c/nxp,pca9541.txt | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt index ef973a0343c7..b7cec17c3daf 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt @@ -33,7 +33,7 @@ i2c0: i2c@fff84000 { clock-frequency = <400000>; 24c512@50 { - compatible = "24c512"; + compatible = "atmel,24c512"; reg = <0x50>; pagesize = <128>; } diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt index 1e98c6b3a721..8b1e49cdce3f 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt @@ -43,7 +43,7 @@ Example: reg = <0>; eeprom@50 { - compatible = "at,24c02"; + compatible = "atmel,24c02"; reg = <0x50>; }; }; @@ -54,7 +54,7 @@ Example: reg = <1>; eeprom@50 { - compatible = "at,24c02"; + compatible = "atmel,24c02"; reg = <0x50>; }; }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt index ccf6c86ed076..30ac6a60f041 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt @@ -54,7 +54,7 @@ Example: reg = <2>; eeprom@54 { - compatible = "at,24c08"; + compatible = "atmel,24c08"; reg = <0x54>; }; }; diff --git a/Documentation/devicetree/bindings/i2c/nxp,pca9541.txt b/Documentation/devicetree/bindings/i2c/nxp,pca9541.txt index 0fbbc6970ec5..42bfc09c8918 100644 --- a/Documentation/devicetree/bindings/i2c/nxp,pca9541.txt +++ b/Documentation/devicetree/bindings/i2c/nxp,pca9541.txt @@ -22,7 +22,7 @@ Example: #size-cells = <0>; eeprom@54 { - compatible = "at,24c08"; + compatible = "atmel,24c08"; reg = <0x54>; }; }; -- cgit v1.2.3 From 1726ea907a7f52d66560ccdb7d0c4da8a6094c14 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 4 Oct 2018 20:28:46 +0800 Subject: dt-bindings: phy: add binding for Allwinner H6 USB2 PHY The USB2.0 PHY on Allwinner H6 is similar to the ones on the ones on older SoCs, but with holes in PHY number (USB1 and USB2 are missing, in which USB1 is a USB3 PHY). Add binding for the PHY. Signed-off-by: Icenowy Zheng Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt index 07ca4ec4a745..f2e120af17f0 100644 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt @@ -14,13 +14,14 @@ Required properties: * allwinner,sun8i-r40-usb-phy * allwinner,sun8i-v3s-usb-phy * allwinner,sun50i-a64-usb-phy + * allwinner,sun50i-h6-usb-phy - reg : a list of offset + length pairs - reg-names : * "phy_ctrl" - * "pmu0" for H3, V3s and A64 + * "pmu0" for H3, V3s, A64 or H6 * "pmu1" * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3 - * "pmu3" for sun8i-h3 + * "pmu3" for sun8i-h3 or sun50i-h6 - #phy-cells : from the generic phy bindings, must be 1 - clocks : phandle + clock specifier for the phy clocks - clock-names : @@ -29,12 +30,13 @@ Required properties: * "usb0_phy", "usb1_phy" for sun8i * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3 + * "usb0_phy" and "usb3_phy" for sun50i-h6 - resets : a list of phandle + reset specifier pairs - reset-names : * "usb0_reset" * "usb1_reset" * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3 - * "usb3_reset" for sun8i-h3 + * "usb3_reset" for sun8i-h3 and sun50i-h6 Optional properties: - usb0_id_det-gpios : gpio phandle for reading the otg id pin value -- cgit v1.2.3 From cb96a690724e105f149b27a88d66669c53b01625 Mon Sep 17 00:00:00 2001 From: Alan Douglas Date: Mon, 12 Nov 2018 16:42:01 +0000 Subject: dt-bindings: phy: Document cadence Sierra PHY bindings Add DT binding documentation for Sierra PHY. The PHY supports a number of different protocols, including PCIe and USB. The PHY lanes may be configured as single or multi-lane links. Each link is treated as a separate sub-node. For example, if there are 4 lanes in total the first 2 might be configured as a multi-lane PCIe link while the other two are single lane USB links, and in this case there would be 3 sub-nodes. There are two resets for the PHY block (one for APB register access, one for the PHY link) and separate resets for each link. For multi-lane links, the reset corresponds to the reset line on the master lane, the resets on other lanes have no effect. Signed-off-by: Alan Douglas Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/phy-cadence-sierra.txt | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt new file mode 100644 index 000000000000..6e1b47bfce43 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt @@ -0,0 +1,67 @@ +Cadence Sierra PHY +----------------------- + +Required properties: +- compatible: cdns,sierra-phy-t0 +- clocks: Must contain an entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must be "phy_clk" +- resets: Must contain an entry for each in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include "sierra_reset" and "sierra_apb". + "sierra_reset" must control the reset line to the PHY. + "sierra_apb" must control the reset line to the APB PHY + interface. +- reg: register range for the PHY. +- #address-cells: Must be 1 +- #size-cells: Must be 0 + +Optional properties: +- cdns,autoconf: A boolean property whose presence indicates that the + PHY registers will be configured by hardware. If not + present, all sub-node optional properties must be + provided. + +Sub-nodes: + Each group of PHY lanes with a single master lane should be represented as + a sub-node. Note that the actual configuration of each lane is determined by + hardware strapping, and must match the configuration specified here. + +Sub-node required properties: +- #phy-cells: Generic PHY binding; must be 0. +- reg: The master lane number. This is the lowest numbered lane + in the lane group. +- resets: Must contain one entry which controls the reset line for the + master lane of the sub-node. + See ../reset/reset.txt for details. + +Sub-node optional properties: +- cdns,num-lanes: Number of lanes in this group. From 1 to 4. The + group is made up of consecutive lanes. +- cdns,phy-type: Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on + configuration of lanes. + +Example: + pcie_phy4: pcie-phy@fd240000 { + compatible = "cdns,sierra-phy-t0"; + reg = <0x0 0xfd240000 0x0 0x40000>; + resets = <&phyrst 0>, <&phyrst 1>; + reset-names = "sierra_reset", "sierra_apb"; + clocks = <&phyclock>; + clock-names = "phy_clk"; + #address-cells = <1>; + #size-cells = <0>; + pcie0_phy0: pcie-phy@0 { + reg = <0>; + resets = <&phyrst 2>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + }; + pcie0_phy1: pcie-phy@2 { + reg = <2>; + resets = <&phyrst 4>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + }; -- cgit v1.2.3 From 5b9bf512ca93a46d370215966d21208ca2e7dc64 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Sun, 25 Nov 2018 18:15:22 -0600 Subject: dt-bindings: phy: add cpsw port interface mode selection phy bindings Add CPSW Port's Interface Mode Selection PHY (phy-gmii-sel) DT Bindings Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Acked-by: Tony Lindgren Signed-off-by: Grygorii Strashko Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/ti-phy-gmii-sel.txt | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt new file mode 100644 index 000000000000..50ce9ae0f7a5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt @@ -0,0 +1,68 @@ +CPSW Port's Interface Mode Selection PHY Tree Bindings +----------------------------------------------- + +TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports +two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces. +The interface mode is selected by configuring the MII mode selection register(s) +(GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and +bit fields placement in SCM are different between SoCs while fields meaning +is the same. + +--------------+ + +-------------------------------+ |SCM | + | CPSW | | +---------+ | + | +--------------------------------+gmii_sel | | + | | | | +---------+ | + | +----v---+ +--------+ | +--------------+ + | |Port 1..<--+-->GMII/MII<-------> + | | | | | | | + | +--------+ | +--------+ | + | | | + | | +--------+ | + | | | RMII <-------> + | +--> | | + | | +--------+ | + | | | + | | +--------+ | + | | | RGMII <-------> + | +--> | | + | +--------+ | + +-------------------------------+ + +CPSW Port's Interface Mode Selection PHY describes MII interface mode between +CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration. + +CPSW Port's Interface Mode Selection PHY device should defined as child device +of SCM node (scm_conf) and can be attached to each CPSW port node using standard +PHY bindings (See phy/phy-bindings.txt). + +Required properties: +- compatible : Should be "ti,am3352-phy-gmii-sel" for am335x platform + "ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform + "ti,am43xx-phy-gmii-sel" for am43xx platform + "ti,dm814-phy-gmii-sel" for dm814x platform +- reg : Address and length of the register set for the device +- #phy-cells : must be 2. + cell 1 - CPSW port number (starting from 1) + cell 2 - RMII refclk mode + +Examples: + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,am3352-phy-gmii-sel"; + reg = <0x650 0x4>; + #phy-cells = <2>; + }; + + mac: ethernet@4a100000 { + compatible = "ti,am335x-cpsw","ti,cpsw"; + ... + + cpsw_emac0: slave@4a100200 { + ... + phys = <&phy_gmii_sel 1 1>; + }; + + cpsw_emac1: slave@4a100300 { + ... + phys = <&phy_gmii_sel 2 1>; + }; + }; -- cgit v1.2.3 From ad57b78579ab477d105b3349dad73af8633fe49a Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Sun, 25 Nov 2018 18:15:24 -0600 Subject: dt-bindings: net: ti: cpsw: switch to use phy-gmii-sel phy The cpsw-phy-sel driver was replaced with new PHY driver phy-gmii-sel, so deprecate cpsw-phy-sel bindings and update CPSW binding to use phy-gmii-sel PHY bindings. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/net/cpsw.txt | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt index b3acebe08eb0..3264e1978d25 100644 --- a/Documentation/devicetree/bindings/net/cpsw.txt +++ b/Documentation/devicetree/bindings/net/cpsw.txt @@ -22,7 +22,8 @@ Required properties: - cpsw-phy-sel : Specifies the phandle to the CPSW phy mode selection device. See also cpsw-phy-sel.txt for it's binding. Note that in legacy cases cpsw-phy-sel may be - a child device instead of a phandle. + a child device instead of a phandle + (DEPRECATED, use phys property instead). Optional properties: - ti,hwmods : Must be "cpgmac0" @@ -44,6 +45,7 @@ Optional properties: Slave Properties: Required properties: - phy-mode : See ethernet.txt file in the same directory +- phys : phandle on phy-gmii-sel PHY (see phy/ti-phy-gmii-sel.txt) Optional properties: - dual_emac_res_vlan : Specifies VID to be used to segregate the ports @@ -85,12 +87,14 @@ Examples: phy-mode = "rgmii-txid"; /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 0>; }; cpsw_emac1: slave@1 { phy_id = <&davinci_mdio>, <1>; phy-mode = "rgmii-txid"; /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 0>; }; }; @@ -114,11 +118,13 @@ Examples: phy-mode = "rgmii-txid"; /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 0>; }; cpsw_emac1: slave@1 { phy_id = <&davinci_mdio>, <1>; phy-mode = "rgmii-txid"; /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 0>; }; }; -- cgit v1.2.3 From 3c2ce40b2fbb52b5e861f8664f5422d39f11b39e Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 15 Nov 2018 15:12:46 +0100 Subject: dt-bindings: phy: add binding for Freescale i.MX8MQ USB3 PHY This adds the binding for the USB3 PHY found on the i.MX8M SoC. Signed-off-by: Lucas Stach Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt new file mode 100644 index 000000000000..a22e853d710c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt @@ -0,0 +1,17 @@ +* Freescale i.MX8MQ USB3 PHY binding + +Required properties: +- compatible: Should be "fsl,imx8mq-usb-phy" +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) +- reg: The base address and length of the registers +- clocks: phandles to the clocks for each clock listed in clock-names +- clock-names: must contain "phy" + +Example: + usb3_phy0: phy@381f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x381f0040 0x40>; + clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; + clock-names = "phy"; + #phy-cells = <0>; + }; -- cgit v1.2.3 From 2517d09b39f3bb811e7349efa8248147ccb2eaa1 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Mon, 10 Dec 2018 11:28:22 -0800 Subject: dt-bindings: phy-qcom-qmp: Fix register underspecification Add register regions for the second lane of dual-lane nodes. This additional specification is needed so that the driver can stop reaching beyond the tx and rx register allocations to get at the second lane registers in a dual-lane PHY. While in there, document #clock-cells as optional for PHYs that don't provide a pipe clock. Also, document the pcs_misc register region, which was being quietly supplied and used. Signed-off-by: Evan Green Reviewed-by: Douglas Anderson Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/qcom-qmp-phy.txt | 70 +++++++++++++++++++--- 1 file changed, 62 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index fbc198d5dd39..f7b532125a4d 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -25,7 +25,7 @@ Required properties: - For all others: - The reg-names property shouldn't be defined. - - #clock-cells: must be 1 + - #clock-cells: must be 1 (PCIe and USB3 PHYs only) - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe interface (for pipe based PHYs). These clock are then gate-controlled by gcc. @@ -82,23 +82,26 @@ Required nodes: - Each device node of QMP phy is required to have as many child nodes as the number of lanes the PHY has. -Required properties for child node: +Required properties for child nodes of PCIe PHYs (one child per lane): - reg: list of offset and length pairs of register sets for PHY blocks - - - index 0: tx - - index 1: rx - - index 2: pcs - - index 3: pcs_misc (optional) + tx, rx, pcs, and pcs_misc (optional). + - #phy-cells: must be 0 +Required properties for a single "lanes" child node of non-PCIe PHYs: + - reg: list of offset and length pairs of register sets for PHY blocks + For 1-lane devices: + tx, rx, pcs, and (optionally) pcs_misc + For 2-lane devices: + tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc - #phy-cells: must be 0 -Required properties child node of pcie and usb3 qmp phys: +Required properties for child node of PCIe and USB3 qmp phys: - clocks: a list of phandles and clock-specifier pairs, one for each entry in clock-names. - clock-names: Must contain following: "pipe" for pipe clock specific to each lane. - clock-output-names: Name of the PHY clock that will be the parent for the above pipe clock. - For "qcom,ipq8074-qmp-pcie-phy": - "pcie20_phy0_pipe_clk" Pipe Clock parent (or) @@ -150,3 +153,54 @@ Example: ... ... }; + + phy@88eb000 { + compatible = "qcom,sdm845-qmp-usb3-uni-phy"; + reg = <0x88eb000 0x18c>; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + lane@88eb200 { + reg = <0x88eb200 0x128>, + <0x88eb400 0x1fc>, + <0x88eb800 0x218>, + <0x88eb600 0x70>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + + phy@1d87000 { + compatible = "qcom,sdm845-qmp-ufs-phy"; + reg = <0x1d87000 0x18c>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + lanes@1d87400 { + reg = <0x1d87400 0x108>, + <0x1d87600 0x1e0>, + <0x1d87c00 0x1dc>, + <0x1d87800 0x108>, + <0x1d87a00 0x1e0>; + #phy-cells = <0>; + }; + }; -- cgit v1.2.3 From d21aafe9a4a55ae5efcd640c0f3dc64ac047d38e Mon Sep 17 00:00:00 2001 From: Evan Green Date: Mon, 10 Dec 2018 11:32:04 -0800 Subject: dt-bindings: phy-qcom-qmp: Move #clock-cells to child The phy-qcom-qmp bindings specified #clock-cells as 1. This was never used because of_clk_add_provider() was never called, so there was no way anybody could reference these clocks from DT. Furthermore, even if they could be accessed, the bindings never specified what should go in that additional cell. Fix these incomplete and broken bindings. Move the #clock-cells into the child node, since that is the actual clock provider, and not all instances of qcom-qmp-phy are clock providers. Also set #clock-cells to zero, since there's nothing to pass to it. Signed-off-by: Evan Green Reviewed-by: Stephen Boyd Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index f7b532125a4d..41a1074228ba 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -25,10 +25,6 @@ Required properties: - For all others: - The reg-names property shouldn't be defined. - - #clock-cells: must be 1 (PCIe and USB3 PHYs only) - - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe - interface (for pipe based PHYs). These clock are then gate-controlled - by gcc. - #address-cells: must be 1 - #size-cells: must be 1 - ranges: must be present @@ -106,6 +102,9 @@ Required properties for child node of PCIe and USB3 qmp phys: - "pcie20_phy0_pipe_clk" Pipe Clock parent (or) "pcie20_phy1_pipe_clk" + - #clock-cells: must be 0 + - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then + gate-controlled by the gcc. Required properties for child node of PHYs with lane reset, AKA: "qcom,msm8996-qmp-pcie-phy" @@ -118,7 +117,6 @@ Example: phy@34000 { compatible = "qcom,msm8996-qmp-pcie-phy"; reg = <0x34000 0x488>; - #clock-cells = <1>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -140,6 +138,7 @@ Example: reg = <0x35000 0x130>, <0x35200 0x200>, <0x35400 0x1dc>; + #clock-cells = <0>; #phy-cells = <0>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; @@ -157,7 +156,6 @@ Example: phy@88eb000 { compatible = "qcom,sdm845-qmp-usb3-uni-phy"; reg = <0x88eb000 0x18c>; - #clock-cells = <1>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -177,6 +175,7 @@ Example: <0x88eb400 0x1fc>, <0x88eb800 0x218>, <0x88eb600 0x70>; + #clock-cells = <0>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "pipe0"; -- cgit v1.2.3 From 95f0455c549cb926804f71cadb9be8b0af792e00 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Tue, 11 Dec 2018 11:57:00 -0500 Subject: media: dt-bindings: media: Add Aspeed Video Engine binding documentation Document the bindings. Signed-off-by: Eddie James Reviewed-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/aspeed-video.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/aspeed-video.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/aspeed-video.txt b/Documentation/devicetree/bindings/media/aspeed-video.txt new file mode 100644 index 000000000000..78b464ae2672 --- /dev/null +++ b/Documentation/devicetree/bindings/media/aspeed-video.txt @@ -0,0 +1,26 @@ +* Device tree bindings for Aspeed Video Engine + +The Video Engine (VE) embedded in the Aspeed AST2400 and AST2500 SOCs can +capture and compress video data from digital or analog sources. + +Required properties: + - compatible: "aspeed,ast2400-video-engine" or + "aspeed,ast2500-video-engine" + - reg: contains the offset and length of the VE memory region + - clocks: clock specifiers for the syscon clocks associated with + the VE (ordering must match the clock-names property) + - clock-names: "vclk" and "eclk" + - resets: reset specifier for the syscon reset associated with + the VE + - interrupts: the interrupt associated with the VE on this platform + +Example: + +video-engine@1e700000 { + compatible = "aspeed,ast2500-video-engine"; + reg = <0x1e700000 0x20000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + resets = <&syscon ASPEED_RESET_VIDEO>; + interrupts = <7>; +}; -- cgit v1.2.3 From 8a582fa9429108c247ff56dfbc4e3ead08a76956 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 11 Dec 2018 15:56:59 +0000 Subject: regulator: add documentation for regulator modes and suspend states Add documentation for regulator modes and suspend states. Signed-off-by: Claudiu Beznea Signed-off-by: Mark Brown --- .../bindings/regulator/act8945a-regulator.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/act8945a-regulator.txt b/Documentation/devicetree/bindings/regulator/act8945a-regulator.txt index ac955dea00d1..4017527619ab 100644 --- a/Documentation/devicetree/bindings/regulator/act8945a-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/act8945a-regulator.txt @@ -15,11 +15,17 @@ Optional input supply properties: - inl67-supply: The input supply for REG_LDO3 and REG_LDO4 Any standard regulator properties can be used to configure the single regulator. +regulator-initial-mode, regulator-allowed-modes and regulator-mode could be +specified using mode values from dt-bindings/regulator/active-semi,8945a-regulator.h +file. The valid names for regulators are: REG_DCDC1, REG_DCDC2, REG_DCDC3, REG_LDO1, REG_LDO2, REG_LDO3, REG_LDO4. Example: + +#include + pmic@5b { compatible = "active-semi,act8945a"; reg = <0x5b>; @@ -32,6 +38,18 @@ Example: regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; + + regulator-allowed-modes = , + ; + regulator-initial-mode = ; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt=<1400000>; + regulator-suspend-max-microvolt=<1400000>; + regulator-changeable-in-suspend; + regulator-mode=; + }; }; vdd_1v2_reg: REG_DCDC2 { @@ -39,6 +57,14 @@ Example: regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; regulator-always-on; + + regulator-allowed-modes = , + ; + regulator-initial-mode = ; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; vdd_3v3_reg: REG_DCDC3 { @@ -53,6 +79,14 @@ Example: regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; + + regulator-allowed-modes = , + ; + regulator-initial-mode = ; + + regulator-state-mem { + regulator-off-in-suspend; + }; }; vdd_3v3_lp_reg: REG_LDO2 { -- cgit v1.2.3 From a9b0a2a7c19316588421b94946c8e2e5a84ac14e Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 7 Dec 2018 20:11:36 +0100 Subject: dt-bindings: iio: adc: exynos-adc: Add S5PV210 variant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add information about new compatible for S5PV210 Signed-off-by: Jonathan Bakker Signed-off-by: Paweł Chmiel Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt index 6c49db7f8ad2..a10c1f89037d 100644 --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt @@ -11,7 +11,7 @@ New driver handles the following Required properties: - compatible: Must be "samsung,exynos-adc-v1" - for exynos4412/5250 and s5pv210 controllers. + for exynos4412/5250 controllers. Must be "samsung,exynos-adc-v2" for future controllers. Must be "samsung,exynos3250-adc" for @@ -28,6 +28,8 @@ Required properties: the ADC in s3c2443 and compatibles Must be "samsung,s3c6410-adc" for the ADC in s3c6410 and compatibles + Must be "samsung,s5pv210-adc" for + the ADC in s5pv210 and compatibles - reg: List of ADC register address range - The base address and range of ADC register - The base address and range of ADC_PHY register (every -- cgit v1.2.3 From a323a513c7128e1597e59f6d3db38c426d229cb9 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Dec 2018 09:50:11 +0100 Subject: dt-bindings: arm: Convert Rockchip board/soc bindings to json-schema Convert Rockchip SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Heiko Stuebner Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Rob Herring [move to per-board entries after confirming with Rob and added recently added boards] Signed-off-by: Heiko Stuebner Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/arm/rockchip.txt | 278 -------------- .../devicetree/bindings/arm/rockchip.yaml | 423 +++++++++++++++++++++ 2 files changed, 423 insertions(+), 278 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/rockchip.txt create mode 100644 Documentation/devicetree/bindings/arm/rockchip.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt deleted file mode 100644 index 6445dbc25c29..000000000000 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ /dev/null @@ -1,278 +0,0 @@ -Rockchip platforms device tree bindings ---------------------------------------- - -- 96boards RK3399 Ficus (ROCK960 Enterprise Edition) - Required root node properties: - - compatible = "vamrs,ficus", "rockchip,rk3399"; - -- 96boards RK3399 Rock960 (ROCK960 Consumer Edition) - Required root node properties: - - compatible = "vamrs,rock960", "rockchip,rk3399"; - -- Amarula Vyasa RK3288 board - Required root node properties: - - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; - -- Asus Tinker board - Required root node properties: - - compatible = "asus,rk3288-tinker", "rockchip,rk3288"; - -- Asus Tinker board S - Required root node properties: - - compatible = "asus,rk3288-tinker-s", "rockchip,rk3288"; - -- Kylin RK3036 board: - Required root node properties: - - compatible = "rockchip,kylin-rk3036", "rockchip,rk3036"; - -- MarsBoard RK3066 board: - Required root node properties: - - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; - -- bq Curie 2 tablet: - Required root node properties: - - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; - -- bq Edison 2 Quad-Core tablet: - Required root node properties: - - compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; - -- ChipSPARK Rayeager PX2 board: - Required root node properties: - - compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; - -- Radxa Rock board: - Required root node properties: - - compatible = "radxa,rock", "rockchip,rk3188"; - -- Radxa Rock2 Square board: - Required root node properties: - - compatible = "radxa,rock2-square", "rockchip,rk3288"; - -- Rikomagic MK808 v1 board: - Required root node properties: - - compatible = "rikomagic,mk808", "rockchip,rk3066a"; - -- Firefly Firefly-RK3288 board: - Required root node properties: - - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; - or - - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; - -- Firefly Firefly-RK3288 Reload board: - Required root node properties: - - compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; - -- Firefly Firefly-RK3399 board: - Required root node properties: - - compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; - -- Firefly roc-rk3328-cc board: - Required root node properties: - - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; - -- Firefly ROC-RK3399-PC board: - Required root node properties: - - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; - -- ChipSPARK PopMetal-RK3288 board: - Required root node properties: - - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; - -- Netxeon R89 board: - Required root node properties: - - compatible = "netxeon,r89", "rockchip,rk3288"; - -- GeekBuying GeekBox: - Required root node properties: - - compatible = "geekbuying,geekbox", "rockchip,rk3368"; - -- Google Bob (Asus Chromebook Flip C101PA): - Required root node properties: - compatible = "google,bob-rev13", "google,bob-rev12", - "google,bob-rev11", "google,bob-rev10", - "google,bob-rev9", "google,bob-rev8", - "google,bob-rev7", "google,bob-rev6", - "google,bob-rev5", "google,bob-rev4", - "google,bob", "google,gru", "rockchip,rk3399"; - -- Google Brain (dev-board): - Required root node properties: - - compatible = "google,veyron-brain-rev0", "google,veyron-brain", - "google,veyron", "rockchip,rk3288"; - -- Google Gru (dev-board): - Required root node properties: - - compatible = "google,gru-rev15", "google,gru-rev14", - "google,gru-rev13", "google,gru-rev12", - "google,gru-rev11", "google,gru-rev10", - "google,gru-rev9", "google,gru-rev8", - "google,gru-rev7", "google,gru-rev6", - "google,gru-rev5", "google,gru-rev4", - "google,gru-rev3", "google,gru-rev2", - "google,gru", "rockchip,rk3399"; - -- Google Jaq (Haier Chromebook 11 and more): - Required root node properties: - - compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4", - "google,veyron-jaq-rev3", "google,veyron-jaq-rev2", - "google,veyron-jaq-rev1", "google,veyron-jaq", - "google,veyron", "rockchip,rk3288"; - -- Google Jerry (Hisense Chromebook C11 and more): - Required root node properties: - - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", - "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", - "google,veyron-jerry-rev3", "google,veyron-jerry", - "google,veyron", "rockchip,rk3288"; - -- Google Kevin (Samsung Chromebook Plus): - Required root node properties: - - compatible = "google,kevin-rev15", "google,kevin-rev14", - "google,kevin-rev13", "google,kevin-rev12", - "google,kevin-rev11", "google,kevin-rev10", - "google,kevin-rev9", "google,kevin-rev8", - "google,kevin-rev7", "google,kevin-rev6", - "google,kevin", "google,gru", "rockchip,rk3399"; - -- Google Mickey (Asus Chromebit CS10): - Required root node properties: - - compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", - "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", - "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", - "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", - "google,veyron-mickey-rev0", "google,veyron-mickey", - "google,veyron", "rockchip,rk3288"; - -- Google Minnie (Asus Chromebook Flip C100P): - Required root node properties: - - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", - "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", - "google,veyron-minnie-rev0", "google,veyron-minnie", - "google,veyron", "rockchip,rk3288"; - -- Google Pinky (dev-board): - Required root node properties: - - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", - "google,veyron", "rockchip,rk3288"; - -- Google Scarlet - with display from Kingdisplay - Required root node properties: - - compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15", - "google,scarlet-rev14-sku7", "google,scarlet-rev14", - "google,scarlet-rev13-sku7", "google,scarlet-rev13", - "google,scarlet-rev12-sku7", "google,scarlet-rev12", - "google,scarlet-rev11-sku7", "google,scarlet-rev11", - "google,scarlet-rev10-sku7", "google,scarlet-rev10", - "google,scarlet-rev9-sku7", "google,scarlet-rev9", - "google,scarlet-rev8-sku7", "google,scarlet-rev8", - "google,scarlet-rev7-sku7", "google,scarlet-rev7", - "google,scarlet-rev6-sku7", "google,scarlet-rev6", - "google,scarlet-rev5-sku7", "google,scarlet-rev5", - "google,scarlet-rev4-sku7", "google,scarlet-rev4", - "google,scarlet-rev3-sku7", "google,scarlet-rev3", - "google,scarlet", "google,gru", "rockchip,rk3399"; - -- Google Scarlet - with display from Innolux - Required root node properties: - - compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", - "google,scarlet-rev14-sku6", "google,scarlet-rev14", - "google,scarlet-rev13-sku6", "google,scarlet-rev13", - "google,scarlet-rev12-sku6", "google,scarlet-rev12", - "google,scarlet-rev11-sku6", "google,scarlet-rev11", - "google,scarlet-rev10-sku6", "google,scarlet-rev10", - "google,scarlet-rev9-sku6", "google,scarlet-rev9", - "google,scarlet-rev8-sku6", "google,scarlet-rev8", - "google,scarlet-rev7-sku6", "google,scarlet-rev7", - "google,scarlet-rev6-sku6", "google,scarlet-rev6", - "google,scarlet-rev5-sku6", "google,scarlet-rev5", - "google,scarlet-rev4-sku6", "google,scarlet-rev4", - "google,scarlet", "google,gru", "rockchip,rk3399"; - - -- Google Speedy (Asus C201 Chromebook): - Required root node properties: - - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", - "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", - "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", - "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", - "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; - -- mqmaker MiQi: - Required root node properties: - - compatible = "mqmaker,miqi", "rockchip,rk3288"; - -- Phytec phyCORE-RK3288: Rapid Development Kit - Required root node properties: - - compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; - -- Pine64 Rock64 board: - Required root node properties: - - compatible = "pine64,rock64", "rockchip,rk3328"; - -- Pine64 RockPro64 board: - Required root node properties: - - compatible = "pine64,rockpro64", "rockchip,rk3399"; - -- Rockchip PX3 Evaluation board: - Required root node properties: - - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; - -- Rockchip PX5 Evaluation board: - Required root node properties: - - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; - -- Rockchip PX30 Evaluation board: - Required root node properties: - - compatible = "rockchip,px30-evb", "rockchip,px30"; - -- Rockchip RV1108 Evaluation board - Required root node properties: - - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - -- Rockchip RK3368 evb: - Required root node properties: - - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; - -- Rockchip R88 board: - Required root node properties: - - compatible = "rockchip,r88", "rockchip,rk3368"; - -- Rockchip RK3228 Evaluation board: - Required root node properties: - - compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; - -- Rockchip RK3229 Evaluation board: - - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - -- Rockchip RK3288 Fennec board: - Required root node properties: - - compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; - -- Rockchip RK3328 evb: - Required root node properties: - - compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; - -- Rockchip RK3399 evb: - Required root node properties: - - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; - -- Rockchip RK3399 Sapphire board standalone: - Required root node properties: - - compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; - -- Rockchip RK3399 Sapphire Excavator board: - Required root node properties: - - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; - -- Theobroma Systems RK3368-uQ7 Haikou Baseboard: - Required root node properties: - - compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368"; - -- Theobroma Systems RK3399-Q7 Haikou Baseboard: - Required root node properties: - - compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399"; - -- Tronsmart Orion R68 Meta - Required root node properties: - - compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368"; diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml new file mode 100644 index 000000000000..b12958bda09c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -0,0 +1,423 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/rockchip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip platforms device tree bindings + +maintainers: + - Heiko Stuebner + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: 96boards RK3399 Ficus (ROCK960 Enterprise Edition) + items: + - const: vamrs,ficus + - const: rockchip,rk3399 + + - description: 96boards RK3399 Rock960 (ROCK960 Consumer Edition) + items: + - const: vamrs,rock960 + - const: rockchip,rk3399 + + - description: Amarula Vyasa RK3288 + items: + - const: amarula,vyasa-rk3288 + - const: rockchip,rk3288 + + - description: Asus Tinker board + items: + - const: asus,rk3288-tinker + - const: rockchip,rk3288 + + - description: Asus Tinker board S + items: + - const: asus,rk3288-tinker-s + - const: rockchip,rk3288 + + - description: bq Curie 2 tablet + items: + - const: mundoreader,bq-curie2 + - const: rockchip,rk3066a + + - description: bq Edison 2 Quad-Core tablet + items: + - const: mundoreader,bq-edison2qc + - const: rockchip,rk3188 + + - description: ChipSPARK PopMetal-RK3288 + items: + - const: chipspark,popmetal-rk3288 + - const: rockchip,rk3288 + + - description: ChipSPARK Rayeager PX2 + items: + - const: chipspark,rayeager-px2 + - const: rockchip,rk3066a + + - description: Firefly Firefly-RK3288 + items: + - enum: + - firefly,firefly-rk3288 + - firefly,firefly-rk3288-beta + - const: rockchip,rk3288 + + - description: Firefly Firefly-RK3288 Reload + items: + - const: firefly,firefly-rk3288-reload + - const: rockchip,rk3288 + + - description: Firefly Firefly-RK3399 + items: + - const: firefly,firefly-rk3399 + - const: rockchip,rk3399 + + - description: Firefly roc-rk3328-cc + items: + - const: firefly,roc-rk3328-cc + - const: rockchip,rk3328 + + - description: Firefly ROC-RK3399-PC + items: + - const: firefly,roc-rk3399-pc + - const: rockchip,rk3399 + + - description: GeekBuying GeekBox + items: + - const: geekbuying,geekbox + - const: rockchip,rk3368 + + - description: Google Bob (Asus Chromebook Flip C101PA) + items: + - const: google,bob-rev13 + - const: google,bob-rev12 + - const: google,bob-rev11 + - const: google,bob-rev10 + - const: google,bob-rev9 + - const: google,bob-rev8 + - const: google,bob-rev7 + - const: google,bob-rev6 + - const: google,bob-rev5 + - const: google,bob-rev4 + - const: google,bob + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Brain (dev-board) + items: + - const: google,veyron-brain-rev0 + - const: google,veyron-brain + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Gru (dev-board) + items: + - const: google,gru-rev15 + - const: google,gru-rev14 + - const: google,gru-rev13 + - const: google,gru-rev12 + - const: google,gru-rev11 + - const: google,gru-rev10 + - const: google,gru-rev9 + - const: google,gru-rev8 + - const: google,gru-rev7 + - const: google,gru-rev6 + - const: google,gru-rev5 + - const: google,gru-rev4 + - const: google,gru-rev3 + - const: google,gru-rev2 + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Jaq (Haier Chromebook 11 and more) + items: + - const: google,veyron-jaq-rev5 + - const: google,veyron-jaq-rev4 + - const: google,veyron-jaq-rev3 + - const: google,veyron-jaq-rev2 + - const: google,veyron-jaq-rev1 + - const: google,veyron-jaq + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Jerry (Hisense Chromebook C11 and more) + items: + - const: google,veyron-jerry-rev7 + - const: google,veyron-jerry-rev6 + - const: google,veyron-jerry-rev5 + - const: google,veyron-jerry-rev4 + - const: google,veyron-jerry-rev3 + - const: google,veyron-jerry + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Kevin (Samsung Chromebook Plus) + items: + - const: google,kevin-rev15 + - const: google,kevin-rev14 + - const: google,kevin-rev13 + - const: google,kevin-rev12 + - const: google,kevin-rev11 + - const: google,kevin-rev10 + - const: google,kevin-rev9 + - const: google,kevin-rev8 + - const: google,kevin-rev7 + - const: google,kevin-rev6 + - const: google,kevin + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Mickey (Asus Chromebit CS10) + items: + - const: google,veyron-mickey-rev8 + - const: google,veyron-mickey-rev7 + - const: google,veyron-mickey-rev6 + - const: google,veyron-mickey-rev5 + - const: google,veyron-mickey-rev4 + - const: google,veyron-mickey-rev3 + - const: google,veyron-mickey-rev2 + - const: google,veyron-mickey-rev1 + - const: google,veyron-mickey-rev0 + - const: google,veyron-mickey + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Minnie (Asus Chromebook Flip C100P) + items: + - const: google,veyron-minnie-rev4 + - const: google,veyron-minnie-rev3 + - const: google,veyron-minnie-rev2 + - const: google,veyron-minnie-rev1 + - const: google,veyron-minnie-rev0 + - const: google,veyron-minnie + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Pinky (dev-board) + items: + - const: google,veyron-pinky-rev2 + - const: google,veyron-pinky + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10) + items: + - const: google,scarlet-rev15-sku7 + - const: google,scarlet-rev15 + - const: google,scarlet-rev14-sku7 + - const: google,scarlet-rev14 + - const: google,scarlet-rev13-sku7 + - const: google,scarlet-rev13 + - const: google,scarlet-rev12-sku7 + - const: google,scarlet-rev12 + - const: google,scarlet-rev11-sku7 + - const: google,scarlet-rev11 + - const: google,scarlet-rev10-sku7 + - const: google,scarlet-rev10 + - const: google,scarlet-rev9-sku7 + - const: google,scarlet-rev9 + - const: google,scarlet-rev8-sku7 + - const: google,scarlet-rev8 + - const: google,scarlet-rev7-sku7 + - const: google,scarlet-rev7 + - const: google,scarlet-rev6-sku7 + - const: google,scarlet-rev6 + - const: google,scarlet-rev5-sku7 + - const: google,scarlet-rev5 + - const: google,scarlet-rev4-sku7 + - const: google,scarlet-rev4 + - const: google,scarlet-rev3-sku7 + - const: google,scarlet-rev3 + - const: google,scarlet + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Scarlet - Innolux display (Acer Chromebook Tab 10) + items: + - const: google,scarlet-rev15-sku6 + - const: google,scarlet-rev15 + - const: google,scarlet-rev14-sku6 + - const: google,scarlet-rev14 + - const: google,scarlet-rev13-sku6 + - const: google,scarlet-rev13 + - const: google,scarlet-rev12-sku6 + - const: google,scarlet-rev12 + - const: google,scarlet-rev11-sku6 + - const: google,scarlet-rev11 + - const: google,scarlet-rev10-sku6 + - const: google,scarlet-rev10 + - const: google,scarlet-rev9-sku6 + - const: google,scarlet-rev9 + - const: google,scarlet-rev8-sku6 + - const: google,scarlet-rev8 + - const: google,scarlet-rev7-sku6 + - const: google,scarlet-rev7 + - const: google,scarlet-rev6-sku6 + - const: google,scarlet-rev6 + - const: google,scarlet-rev5-sku6 + - const: google,scarlet-rev5 + - const: google,scarlet-rev4-sku6 + - const: google,scarlet-rev4 + - const: google,scarlet + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Speedy (Asus C201 Chromebook) + items: + - const: google,veyron-speedy-rev9 + - const: google,veyron-speedy-rev8 + - const: google,veyron-speedy-rev7 + - const: google,veyron-speedy-rev6 + - const: google,veyron-speedy-rev5 + - const: google,veyron-speedy-rev4 + - const: google,veyron-speedy-rev3 + - const: google,veyron-speedy-rev2 + - const: google,veyron-speedy + - const: google,veyron + - const: rockchip,rk3288 + + - description: Haoyu MarsBoard RK3066 + items: + - const: haoyu,marsboard-rk3066 + - const: rockchip,rk3066a + + - description: mqmaker MiQi + items: + - const: mqmaker,miqi + - const: rockchip,rk3288 + + - description: Netxeon R89 board + items: + - const: netxeon,r89 + - const: rockchip,rk3288 + + - description: Phytec phyCORE-RK3288 Rapid Development Kit + items: + - const: phytec,rk3288-pcm-947 + - const: phytec,rk3288-phycore-som + - const: rockchip,rk3288 + + - description: Pine64 Rock64 + items: + - const: pine64,rock64 + - const: rockchip,rk3328 + + - description: Pine64 RockPro64 + items: + - const: pine64,rockpro64 + - const: rockchip,rk3399 + + - description: Radxa Rock + items: + - const: radxa,rock + - const: rockchip,rk3188 + + - description: Radxa Rock2 Square + items: + - const: radxa,rock2-square + - const: rockchip,rk3288 + + - description: Rikomagic MK808 v1 + items: + - const: rikomagic,mk808 + - const: rockchip,rk3066a + + - description: Rockchip Kylin + items: + - const: rockchip,kylin-rk3036 + - const: rockchip,rk3036 + + - description: Rockchip PX3 Evaluation board + items: + - const: rockchip,px3-evb + - const: rockchip,px3 + - const: rockchip,rk3188 + + - description: Rockchip PX30 Evaluation board + items: + - const: rockchip,px30-evb + - const: rockchip,px30 + + - description: Rockchip PX5 Evaluation board + items: + - const: rockchip,px5-evb + - const: rockchip,px5 + - const: rockchip,rk3368 + + - description: Rockchip R88 + items: + - const: rockchip,r88 + - const: rockchip,rk3368 + + - description: Rockchip RK3228 Evaluation board + items: + - const: rockchip,rk3228-evb + - const: rockchip,rk3228 + + - description: Rockchip RK3229 Evaluation board + items: + - const: rockchip,rk3229-evb + - const: rockchip,rk3229 + + - description: Rockchip RK3288 Evaluation board + items: + - enum: + - rockchip,rk3288-evb-act8846 + - rockchip,rk3288-evb-rk808 + - const: rockchip,rk3288 + + - description: Rockchip RK3288 Fennec + items: + - const: rockchip,rk3288-fennec + - const: rockchip,rk3288 + + - description: Rockchip RK3328 Evaluation board + items: + - const: rockchip,rk3328-evb + - const: rockchip,rk3328 + + - description: Rockchip RK3368 Evaluation board (act8846 pmic) + items: + - const: rockchip,rk3368-evb-act8846 + - const: rockchip,rk3368 + + - description: Rockchip RK3399 Evaluation board + items: + - const: rockchip,rk3399-evb + - const: rockchip,rk3399 + + - description: Rockchip RK3399 Sapphire standalone + items: + - const: rockchip,rk3399-sapphire + - const: rockchip,rk3399 + + - description: Rockchip RK3399 Sapphire with Excavator Baseboard + items: + - const: rockchip,rk3399-sapphire-excavator + - const: rockchip,rk3399 + + - description: Rockchip RV1108 Evaluation board + items: + - const: rockchip,rv1108-evb + - const: rockchip,rv1108 + + - description: Theobroma Systems RK3368-uQ7 with Haikou baseboard + items: + - const: tsd,rk3368-uq7-haikou + - const: rockchip,rk3368 + + - description: Theobroma Systems RK3399-Q7 with Haikou baseboard + items: + - const: tsd,rk3399-q7-haikou + - const: rockchip,rk3399 + + - description: Tronsmart Orion R68 Meta + items: + - const: tronsmart,orion-r68-meta + - const: rockchip,rk3368 +... -- cgit v1.2.3 From 58ee90284ffa495b04d56d643001d6f64a13a580 Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Wed, 12 Dec 2018 17:35:32 +0800 Subject: dt-binding: mediatek-dwmac: add binding document for MediaTek MT2712 DWMAC The commit adds the device tree binding documentation for the MediaTek DWMAC found on MediaTek MT2712. Signed-off-by: Biao Huang Signed-off-by: David S. Miller --- .../devicetree/bindings/net/mediatek-dwmac.txt | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/mediatek-dwmac.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt new file mode 100644 index 000000000000..4de479b4d44d --- /dev/null +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt @@ -0,0 +1,87 @@ +MediaTek DWMAC glue layer controller + +This file documents platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +The device node has following properties. + +Required properties: +- compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC +- reg: Address and length of the register set for the device +- interrupts: Should contain the MAC interrupts +- interrupt-names: Should contain a list of interrupt names corresponding to + the interrupts in the interrupts property, if available. + Should be "macirq" for the main MAC IRQ +- clocks: Must contain a phandle for each entry in clock-names. +- clock-names: The name of the clock listed in the clocks property. These are + "axi", "apb", "mac_main", "ptp_ref" for MT2712 SoC +- mac-address: See ethernet.txt in the same directory +- phy-mode: See ethernet.txt in the same directory +- mediatek,pericfg: A phandle to the syscon node that control ethernet + interface and timing delay. + +Optional properties: +- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0. + It should be defined for rgmii/rgmii-rxid/mii interface. +- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0. + It should be defined for rgmii/rgmii-txid/mii/rmii interface. +Both delay properties need to be a multiple of 170 for fine-tune rgmii, +range 0~31*170. +Both delay properties need to be a multiple of 550 for coarse-tune rgmii, +range 0~31*550. +Both delay properties need to be a multiple of 550 for mii/rmii, +range 0~31*550. + +- mediatek,fine-tune: boolean property, if present indicates that fine delay + is selected for rgmii interface. + If present, tx-delay-ps/rx-delay-ps is 170+/-50ps per stage. + Else tx-delay-ps/rx-delay-ps of coarse delay macro is 0.55+/-0.2ns per stage. + This property do not apply to non-rgmii PHYs. + Only coarse-tune delay is supported for mii/rmii PHYs. +- mediatek,rmii-rxc: boolean property, if present indicates that the rmii + reference clock, which is from external PHYs, is connected to RXC pin + on MT2712 SoC. + Otherwise, is connected to TXC pin. +- mediatek,txc-inverse: boolean property, if present indicates that + 1. tx clock will be inversed in mii/rgmii case, + 2. tx clock inside MAC will be inversed relative to reference clock + which is from external PHYs in rmii case, and it rarely happen. +- mediatek,rxc-inverse: boolean property, if present indicates that + 1. rx clock will be inversed in mii/rgmii case. + 2. reference clock will be inversed when arrived at MAC in rmii case. +- assigned-clocks: mac_main and ptp_ref clocks +- assigned-clock-parents: parent clocks of the assigned clocks + +Example: + eth: ethernet@1101c000 { + compatible = "mediatek,mt2712-gmac"; + reg = <0 0x1101c000 0 0x1300>; + interrupts = ; + interrupt-names = "macirq"; + phy-mode ="rgmii"; + mac-address = [00 55 7b b5 7d f7]; + clock-names = "axi", + "apb", + "mac_main", + "ptp_ref", + "ptp_top"; + clocks = <&pericfg CLK_PERI_GMAC>, + <&pericfg CLK_PERI_GMAC_PCLK>, + <&topckgen CLK_TOP_ETHER_125M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_SEL>; + assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, + <&topckgen CLK_TOP_APLL1_D3>; + mediatek,pericfg = <&pericfg>; + mediatek,tx-delay-ps = <1530>; + mediatek,rx-delay-ps = <1530>; + mediatek,fine-tune; + mediatek,rmii-rxc; + mediatek,txc-inverse; + mediatek,rxc-inverse; + snps,txpbl = <32>; + snps,rxpbl = <32>; + snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + }; -- cgit v1.2.3 From cdf6179630a5aa877fba986e1c5dc91f2285eb08 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 10 Dec 2018 23:05:39 +0530 Subject: dt-bindings: interrupt-controller: Document RDA8810PL intc Document interrupt controller in RDA Micro RDA8810PL SoC. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Marc Zyngier --- .../interrupt-controller/rda,8810pl-intc.txt | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt new file mode 100644 index 000000000000..e0062aebf025 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt @@ -0,0 +1,61 @@ +RDA Micro RDA8810PL Interrupt Controller + +The interrupt controller in RDA8810PL SoC is a custom interrupt controller +which supports up to 32 interrupts. + +Required properties: + +- compatible: Should be "rda,8810pl-intc". +- reg: Specifies base physical address of the registers set. +- interrupt-controller: Identifies the node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The value shall be 2. + +The interrupt sources are as follows: + +ID Name +------------ +0: PULSE_DUMMY +1: I2C +2: NAND_NFSC +3: SDMMC1 +4: SDMMC2 +5: SDMMC3 +6: SPI1 +7: SPI2 +8: SPI3 +9: UART1 +10: UART2 +11: UART3 +12: GPIO1 +13: GPIO2 +14: GPIO3 +15: KEYPAD +16: TIMER +17: TIMEROS +18: COMREG0 +19: COMREG1 +20: USB +21: DMC +22: DMA +23: CAMERA +24: GOUDA +25: GPU +26: VPU_JPG +27: VPU_HOST +28: VOC +29: AUIFC0 +30: AUIFC1 +31: L2CC + +Example: + apb@20800000 { + compatible = "simple-bus"; + ... + intc: interrupt-controller@0 { + compatible = "rda,8810pl-intc"; + reg = <0x0 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; -- cgit v1.2.3 From a15b7439083c30030f6269c4c0ec70af57949109 Mon Sep 17 00:00:00 2001 From: Mesih Kilinc Date: Sun, 2 Dec 2018 23:23:38 +0300 Subject: dt-bindings: interrupt-controller: Add suniv interrupt-controller Add compatible string for Alwinner suniv F1C100s SoC interrupt controller which is stripped version of sun4i Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Marc Zyngier --- .../devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt index b290ca150d30..404352524c3a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt @@ -2,7 +2,9 @@ Allwinner Sunxi Interrupt Controller Required properties: -- compatible : should be "allwinner,sun4i-a10-ic" +- compatible : should be one of the following: + "allwinner,sun4i-a10-ic" + "allwinner,suniv-f1c100s-ic" - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an -- cgit v1.2.3 From f0b3f8418711d2e482bd57d6c0b5790947ca6863 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 13 Dec 2018 08:36:38 -0200 Subject: ASoC: fsl-sai: Fix typo in "transmitter" Fix the spelling of "transmitter". Signed-off-by: Fabio Estevam Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/fsl-sai.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index dd9e59738e08..2e726b983845 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -35,13 +35,13 @@ Required properties: - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating that SAI will work in the synchronous mode (sync Tx - with Rx) which means both the transimitter and the + with Rx) which means both the transmitter and the receiver will send and receive data by following receiver's bit clocks and frame sync clocks. - fsl,sai-asynchronous: This is a boolean property. If present, indicating that SAI will work in the asynchronous mode, which - means both transimitter and receiver will send and + means both transmitter and receiver will send and receive data by following their own bit clocks and frame sync clocks separately. @@ -58,8 +58,8 @@ Optional properties (for mx6ul): Note: - If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the default synchronous mode (sync Rx with Tx) will be used, which means both - transimitter and receiver will send and receive data by following clocks - of transimitter. + transmitter and receiver will send and receive data by following clocks + of transmitter. - fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive. Example: -- cgit v1.2.3 From 62f82df488ce16f7068c7285820b2b7f7dcd7597 Mon Sep 17 00:00:00 2001 From: Clark Wang Date: Fri, 7 Dec 2018 02:50:41 +0000 Subject: doc: lpspi: Document DT bindings for LPSPI slave mode Add introductions of interrupt-parent and spi-slave. Signed-off-by: Clark Wang Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt index 8d178a4503cf..6cc3c6fe25a3 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt @@ -5,8 +5,11 @@ Required properties: - "fsl,imx7ulp-spi" for LPSPI compatible with the one integrated on i.MX7ULP soc - "fsl,imx8qxp-spi" for LPSPI compatible with the one integrated on i.MX8QXP soc - reg : address and length of the lpspi master registers +- interrupt-parent : core interrupt controller - interrupts : lpspi interrupt - clocks : lpspi clock specifier +- spi-slave : spi slave mode support. In slave mode, add this attribute without + value. In master mode, remove it. Examples: @@ -16,4 +19,5 @@ lpspi2: lpspi@40290000 { interrupt-parent = <&intc>; interrupts = ; clocks = <&clks IMX7ULP_CLK_LPSPI2>; + spi-slave; }; -- cgit v1.2.3 From 18dc4665fb6f3bb617c2e6d7da3f19586d06ab17 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 11 Dec 2018 14:47:11 +0100 Subject: ASoC: meson: add axg spdif input DT binding documentation Add the DT binding documentation for axg's SPDIF input. Signed-off-by: Jerome Brunet Signed-off-by: Mark Brown --- .../bindings/sound/amlogic,axg-spdifin.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/amlogic,axg-spdifin.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-spdifin.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-spdifin.txt new file mode 100644 index 000000000000..2e6cb7d9b202 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/amlogic,axg-spdifin.txt @@ -0,0 +1,22 @@ +* Amlogic Audio SPDIF Input + +Required properties: +- compatible: 'amlogic,axg-spdifin' +- interrupts: interrupt specifier for the spdif input. +- clocks: list of clock phandle, one for each entry clock-names. +- clock-names: should contain the following: + * "pclk" : peripheral clock. + * "refclk" : spdif input reference clock +- #sound-dai-cells: must be 0. + +Example on the A113 SoC: + +spdifin: audio-controller@400 { + compatible = "amlogic,axg-spdifin"; + reg = <0x0 0x400 0x0 0x30>; + #sound-dai-cells = <0>; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, + <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; + clock-names = "pclk", "refclk"; +}; -- cgit v1.2.3 From 96f3fb86d70fe64ba88a7f567bafe9c504b87d25 Mon Sep 17 00:00:00 2001 From: "Andrei.Stefanescu@microchip.com" Date: Wed, 12 Dec 2018 18:31:08 +0000 Subject: regulator: dt-bindings: add MCP16502 regulator bindings This patch describes the compatible and the device tree bindings necessary for the MCP16502 PMIC. Signed-off-by: Andrei Stefanescu Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- .../bindings/regulator/mcp16502-regulator.txt | 143 +++++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/mcp16502-regulator.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/mcp16502-regulator.txt b/Documentation/devicetree/bindings/regulator/mcp16502-regulator.txt new file mode 100644 index 000000000000..b8f843fa6092 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mcp16502-regulator.txt @@ -0,0 +1,143 @@ +MCP16502 PMIC + +Required properties: +- compatible: "microchip,mcp16502" +- reg: I2C slave address +- lpm-gpios: GPIO for LPM pin. Note that this GPIO *must* remain high during + suspend-to-ram, keeping the PMIC into HIBERNATE mode. +- regulators: A node that houses a sub-node for each regulator within + the device. Each sub-node is identified using the node's + name. The content of each sub-node is defined by the + standard binding for regulators; see regulator.txt. + +Regualtors of MCP16502 PMIC: +1) VDD_IO - Buck (1.2 - 3.7 V) +2) VDD_DDR - Buck (0.6 - 1.85 V) +3) VDD_CORE - Buck (0.6 - 1.85 V) +4) VDD_OTHER - BUCK (0.6 - 1.85 V) +5) LDO1 - LDO (1.2 - 3.7 V) +6) LDO2 - LDO (1.2 - 3.7 V) + +Regulator modes: +2 - FPWM: higher precision, higher consumption +4 - AutoPFM: lower precision, lower consumption + +Each regulator is defined using the standard binding for regulators. + +Example: + +mcp16502@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + status = "okay"; + lpm-gpios = <&pioBU 7 GPIO_ACTIVE_HIGH>; + + regulators { + VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + }; +}; -- cgit v1.2.3 From b0b41af12a1bf21a45ccfe48da194ee688170d03 Mon Sep 17 00:00:00 2001 From: Naga Sureshkumar Relli Date: Thu, 6 Dec 2018 18:17:33 +0530 Subject: dt-bindings: memory: Add pl353 smc controller devicetree binding information Add pl353 static memory controller devicetree binding information. Signed-off-by: Naga Sureshkumar Relli Reviewed-by: Linus Walleij Signed-off-by: Michal Simek --- .../bindings/memory-controllers/pl353-smc.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt new file mode 100644 index 000000000000..d56615fd343a --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt @@ -0,0 +1,47 @@ +Device tree bindings for ARM PL353 static memory controller + +PL353 static memory controller supports two kinds of memory +interfaces.i.e NAND and SRAM/NOR interfaces. +The actual devices are instantiated from the child nodes of pl353 smc node. + +Required properties: +- compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell". +- reg : Controller registers map and length. +- clock-names : List of input clock names - "memclk", "apb_pclk" + (See clock bindings for details). +- clocks : Clock phandles (see clock bindings for details). +- address-cells : Must be 2. +- size-cells : Must be 1. + +Child nodes: + For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are +supported as child nodes. + +for NAND partition information please refer the below file +Documentation/devicetree/bindings/mtd/partition.txt + +Example: + smcc: memory-controller@e000e000 + compatible = "arm,pl353-smc-r2p1", "arm,primecell"; + clock-names = "memclk", "apb_pclk"; + clocks = <&clkc 11>, <&clkc 44>; + reg = <0xe000e000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region + 0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region + 0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region + nand_0: flash@e1000000 { + compatible = "arm,pl353-nand-r2p1" + reg = <0 0 0x1000000>; + (...) + }; + nor0: flash@e2000000 { + compatible = "cfi-flash"; + reg = <1 0 0x2000000>; + }; + nor1: flash@e4000000 { + compatible = "cfi-flash"; + reg = <2 0 0x2000000>; + }; + }; -- cgit v1.2.3 From 644c2dcf2f2ea113602aa24170d3203942d3d140 Mon Sep 17 00:00:00 2001 From: Maruthi Srinivas Bayyavarapu Date: Sat, 8 Dec 2018 00:02:36 +0530 Subject: dt-bindings: ASoC: xlnx, i2s: Document i2s bindings Added documentation for I2S IP core DT bindings. Signed-off-by: Maruthi Srinivas Bayyavarapu Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/xlnx,i2s.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/xlnx,i2s.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/xlnx,i2s.txt b/Documentation/devicetree/bindings/sound/xlnx,i2s.txt new file mode 100644 index 000000000000..5e7c7d5bb60a --- /dev/null +++ b/Documentation/devicetree/bindings/sound/xlnx,i2s.txt @@ -0,0 +1,28 @@ +Device-Tree bindings for Xilinx I2S PL block + +The IP supports I2S based playback/capture audio + +Required property: + - compatible: "xlnx,i2s-transmitter-1.0" for playback and + "xlnx,i2s-receiver-1.0" for capture + +Required property common to both I2S playback and capture: + - reg: Base address and size of the IP core instance. + - xlnx,dwidth: sample data width. Can be any of 16, 24. + - xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4. + supported channels = 2 * xlnx,num-channels + +Example: + + i2s_receiver@a0080000 { + compatible = "xlnx,i2s-receiver-1.0"; + reg = <0x0 0xa0080000 0x0 0x10000>; + xlnx,dwidth = <0x18>; + xlnx,num-channels = <1>; + }; + i2s_transmitter@a0090000 { + compatible = "xlnx,i2s-transmitter-1.0"; + reg = <0x0 0xa0090000 0x0 0x10000>; + xlnx,dwidth = <0x18>; + xlnx,num-channels = <1>; + }; -- cgit v1.2.3 From 4f0e3a57d6eb727c54249542c509e0b7aa122465 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 6 Sep 2018 13:26:07 -0500 Subject: kbuild: Add support for DT binding schema checks This adds the build infrastructure for checking DT binding schema documents and validating dts files using the binding schema. Check DT binding schema documents: make dt_binding_check Build dts files and check using DT binding schema: make dtbs_check Optionally, DT_SCHEMA_FILES can be passed in with a schema file(s) to use for validation. This makes it easier to find and fix errors generated by a specific schema. Currently, the validation targets are separate from a normal build to avoid a hard dependency on the external DT schema project and because there are lots of warnings generated. Cc: Jonathan Corbet Cc: Mark Rutland Acked-by: Masahiro Yamada Cc: Michal Marek Cc: linux-doc@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kbuild@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/.gitignore | 2 ++ Documentation/devicetree/bindings/Makefile | 27 +++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/.gitignore create mode 100644 Documentation/devicetree/bindings/Makefile (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/.gitignore b/Documentation/devicetree/bindings/.gitignore new file mode 100644 index 000000000000..ef82fcfcccab --- /dev/null +++ b/Documentation/devicetree/bindings/.gitignore @@ -0,0 +1,2 @@ +*.example.dts +processed-schema.yaml diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile new file mode 100644 index 000000000000..6e5cef0ed6fb --- /dev/null +++ b/Documentation/devicetree/bindings/Makefile @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0 +DT_DOC_CHECKER ?= dt-doc-validate +DT_EXTRACT_EX ?= dt-extract-example +DT_MK_SCHEMA ?= dt-mk-schema +DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u) + +quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<) + cmd_chk_binding = $(DT_DOC_CHECKER) $< ; \ + $(DT_EXTRACT_EX) $< > $@ + +$(obj)/%.example.dts: $(src)/%.yaml FORCE + $(call if_changed,chk_binding) + +DT_TMP_SCHEMA := processed-schema.yaml +extra-y += $(DT_TMP_SCHEMA) + +quiet_cmd_mk_schema = SCHEMA $@ + cmd_mk_schema = $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $(filter-out FORCE, $^) + +DT_DOCS = $(shell cd $(srctree)/$(src) && find * -name '*.yaml') +DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS)) + +extra-y += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES)) +extra-y += $(patsubst $(src)/%.yaml,%.example.dtb, $(DT_SCHEMA_FILES)) + +$(obj)/$(DT_TMP_SCHEMA): $(DT_SCHEMA_FILES) FORCE + $(call if_changed,mk_schema) -- cgit v1.2.3 From 00ce8a800060c80c6d0c895fad10cacb03277fcc Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 29 Jun 2018 08:19:52 -0600 Subject: dt-bindings: Add a writing DT schemas how-to and annotated example Add a how-to doc on writing DT schema documentation. This gives a description of each section and details on how to validate the DT schema file. The DT schema are written using json-schema vocabulary in a YAML encoded document. Using jsonschema gives us access to existing tooling. A YAML encoding gives us something easy to edit. The example is annotated to help explain what each section does. This example is just the tip of the iceberg, but is it the part most developers writing bindings will interact with. Backing all this up are meta-schema (to validate the binding schemas), some DT core schema, YAML encoded DT output with dtc, and a small number of python scripts to run validation. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/example-schema.yaml | 170 +++++++++++++++++++++ Documentation/devicetree/writing-schema.md | 130 ++++++++++++++++ 2 files changed, 300 insertions(+) create mode 100644 Documentation/devicetree/bindings/example-schema.yaml create mode 100644 Documentation/devicetree/writing-schema.md (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml new file mode 100644 index 000000000000..9175d67f355d --- /dev/null +++ b/Documentation/devicetree/bindings/example-schema.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +# All the top-level keys are standard json-schema keywords except for +# 'maintainers' and 'select' + +# $id is a unique idenifier based on the filename. There may or may not be a +# file present at the URL. +$id: "http://devicetree.org/schemas/example-schema.yaml#" +# $schema is the meta-schema this schema should be validated with. +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: An example schema annotated with jsonschema details + +maintainers: + - Rob Herring + +description: | + A more detailed multi-line description of the binding. + + Details about the hardware device and any links to datasheets can go here. + + Literal blocks are marked with the '|' at the beginning. The end is marked by + indentation less than the first line of the literal block. Lines also cannot + begin with a tab character. + +select: false + # 'select' is a schema applied to a DT node to determine if this binding + # schema should be applied to the node. It is optional and by default the + # possible compatible strings are extracted and used to match. + + # In this case, a 'false' schema will never match. + +properties: + # A dictionary of DT properties for this binding schema + compatible: + # More complicated schema can use oneOf (XOR), anyOf (OR), or allOf (AND) + # to handle different conditions. + # In this case, it's needed to handle a variable number of values as there + # isn't another way to express a constraint of the last string value. + # The boolean schema must be a list of schemas. + oneOf: + - items: + # items is a list of possible values for the property. The number of + # values is determined by the number of elements in the list. + # Order in lists is significant, order in dicts is not + # Must be one of the 1st enums followed by the 2nd enum + # + # Each element in items should be 'enum' or 'const' + - enum: + - vendor,soc4-ip + - vendor,soc3-ip + - vendor,soc2-ip + - enum: + - vendor,soc1-ip + # additionalItems being false is implied + # minItems/maxItems equal to 2 is implied + - items: + # 'const' is just a special case of an enum with a single possible value + - const: vendor,soc1-ip + + reg: + # The core schema already checks that reg values are numbers, so device + # specific schema don't need to do those checks. + # The description of each element defines the order and implicitly defines + # the number of reg entries. + items: + - description: core registers + - description: aux registers + # minItems/maxItems equal to 2 is implied + + reg-names: + # The core schema enforces this is a string array + items: + - const: core + - const: aux + + clocks: + # Cases that have only a single entry just need to express that with maxItems + maxItems: 1 + description: bus clock + + clock-names: + items: + - const: bus + + interrupts: + # Either 1 or 2 interrupts can be present + minItems: 1 + maxItems: 2 + items: + - description: tx or combined interrupt + - description: rx interrupt + description: + A variable number of interrupts warrants a description of what conditions + affect the number of interrupts. Otherwise, descriptions on standard + properties are not necessary. + + interrupt-names: + # minItems must be specified here because the default would be 2 + minItems: 1 + maxItems: 2 + items: + - const: tx irq + - const: rx irq + + # Property names starting with '#' must be quoted + '#interrupt-cells': + # A simple case where the value must always be '2'. + # The core schema handles that this must be a single integer. + const: 2 + + interrupt-controller: true + # The core checks this is a boolean, so just have to list it here to be + # valid for this binding. + + clock-frequency: + # The type is set in the core schema. Per device schema only need to set + # constraints on the possible values. + minimum: 100 + maximum: 400000 + # The value that should be used if the property is not present + default: 200 + + foo-gpios: + maxItems: 1 + description: A connection of the 'foo' gpio line. + + vendor,int-property: + description: Vendor specific properties must have a description + # 'allOf' is the json-schema way of subclassing a schema. Here the base + # type schema is referenced and then additional constraints on the values + # are added. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [2, 4, 6, 8, 10] + + vendor,bool-property: + description: Vendor specific properties must have a description + # boolean properties is one case where the json-schema 'type' keyword + # can be used directly + type: boolean + + vendor,string-array-property: + description: Vendor specific properties should reference a type in the + core schema. + allOf: + - $ref: /schemas/types.yaml#/definitions/string-array + - items: + - enum: [ foo, bar ] + - enum: [ baz, boo ] + +required: + - compatible + - reg + - interrupts + - interrupt-controller + +examples: + # Examples are now compiled with dtc + - | + node@1000 { + compatible = "vendor,soc4-ip", "vendor,soc1-ip"; + reg = <0x1000 0x80>, + <0x3000 0x80>; + reg-names = "core", "aux"; + interrupts = <10>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/writing-schema.md b/Documentation/devicetree/writing-schema.md new file mode 100644 index 000000000000..a3652d33a48f --- /dev/null +++ b/Documentation/devicetree/writing-schema.md @@ -0,0 +1,130 @@ +# Writing DeviceTree Bindings in json-schema + +Devicetree bindings are written using json-schema vocabulary. Schema files are +written in a JSON compatible subset of YAML. YAML is used instead of JSON as it +considered more human readable and has some advantages such as allowing +comments (Prefixed with '#'). + +## Schema Contents + +Each schema doc is a structured json-schema which is defined by a set of +top-level properties. Generally, there is one binding defined per file. The +top-level json-schema properties used are: + +- __$id__ - A json-schema unique identifier string. The string must be a valid +URI typically containing the binding's filename and path. For DT schema, it must +begin with "http://devicetree.org/schemas/". The URL is used in constructing +references to other files specified in schema "$ref" properties. A $ref values +with a leading '/' will have the hostname prepended. A $ref value a relative +path or filename only will be prepended with the hostname and path components +of the current schema file's '$id' value. A URL is used even for local files, +but there may not actually be files present at those locations. + +- __$schema__ - Indicates the meta-schema the schema file adheres to. + +- __title__ - A one line description on the contents of the binding schema. + +- __maintainers__ - A DT specific property. Contains a list of email address(es) +for maintainers of this binding. + +- __description__ - Optional. A multi-line text block containing any detailed +information about this binding. It should contain things such as what the block +or device does, standards the device conforms to, and links to datasheets for +more information. + +- __select__ - Optional. A json-schema used to match nodes for applying the +schema. By default without 'select', nodes are matched against their possible +compatible string values or node name. Most bindings should not need select. + +- __allOf__ - Optional. A list of other schemas to include. This is used to +include other schemas the binding conforms to. This may be schemas for a +particular class of devices such as I2C or SPI controllers. + +- __properties__ - A set of sub-schema defining all the DT properties for the +binding. The exact schema syntax depends on whether properties are known, +common properties (e.g. 'interrupts') or are binding/vendor specific properties. + + A property can also define a child DT node with child properties defined +under it. + + For more details on properties sections, see 'Property Schema' section. + +- __patternProperties__ - Optional. Similar to 'properties', but names are regex. + +- __required__ - A list of DT properties from the 'properties' section that +must always be present. + +- __examples__ - Optional. A list of one or more DTS hunks implementing the +binding. Note: YAML doesn't allow leading tabs, so spaces must be used instead. + +Unless noted otherwise, all properties are required. + +## Property Schema + +The 'properties' section of the schema contains all the DT properties for a +binding. Each property contains a set of constraints using json-schema +vocabulary for that property. The properties schemas are what is used for +validation of DT files. + +For common properties, only additional constraints not covered by the common +binding schema need to be defined such as how many values are valid or what +possible values are valid. + +Vendor specific properties will typically need more detailed schema. With the +exception of boolean properties, they should have a reference to a type in +schemas/types.yaml. A "description" property is always required. + +The Devicetree schemas don't exactly match the YAML encoded DT data produced by +dtc. They are simplified to make them more compact and avoid a bunch of +boilerplate. The tools process the schema files to produce the final schema for +validation. There are currently 2 transformations the tools perform. + +The default for arrays in json-schema is they are variable sized and allow more +entries than explicitly defined. This can be restricted by defining 'minItems', +'maxItems', and 'additionalItems'. However, for DeviceTree Schemas, a fixed +size is desired in most cases, so these properties are added based on the +number of entries in an 'items' list. + +The YAML Devicetree format also makes all string values an array and scalar +values a matrix (in order to define groupings) even when only a single value +is present. Single entries in schemas are fixed up to match this encoding. + +## Testing + +### Dependencies + +The DT schema project must be installed in order to validate the DT schema +binding documents and validate DTS files using the DT schema. The DT schema +project can be installed with pip: + +`pip3 install git+https://github.com/robherring/yaml-bindings.git@master` + +dtc must also be built with YAML output support enabled. This requires that +libyaml and its headers be installed on the host system. + +### Running checks + +The DT schema binding documents must be validated using the meta-schema (the +schema for the schema) to ensure they are both valid json-schema and valid +binding schema. All of the DT binding documents can be validated using the +`dt_binding_check` target: + +`make dt_binding_check` + +In order to perform validation of DT source files, use the `dtbs_check` target: + +`make dtbs_check` + +This will first run the `dt_binding_check` which generates the processed schema. + +It is also possible to run checks with a single schema file by setting the +'DT_SCHEMA_FILES' variable to a specific schema file. + +`make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/trivial-devices.yaml` + + +## json-schema Resources + +[JSON-Schema Specifications](http://json-schema.org/) + +[Using JSON Schema Book](http://usingjsonschema.com/) -- cgit v1.2.3 From b31abceb0fec717948e4e8dae6705baf6914db96 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:40:09 -0500 Subject: dt-bindings: altera: Convert clkmgr binding to json-schema Convert Altera clkmgr to DT schema format using json-schema. Cc: Mark Rutland Acked-by: Dinh Nguyen Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../bindings/arm/altera/socfpga-clk-manager.txt | 11 -------- .../bindings/arm/altera/socfpga-clk-manager.yaml | 31 ++++++++++++++++++++++ 2 files changed, 31 insertions(+), 11 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt deleted file mode 100644 index 2c28f1d12f45..000000000000 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt +++ /dev/null @@ -1,11 +0,0 @@ -Altera SOCFPGA Clock Manager - -Required properties: -- compatible : "altr,clk-mgr" -- reg : Should contain base address and length for Clock Manager - -Example: - clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml new file mode 100644 index 000000000000..e4131fa42b26 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera SOCFPGA Clock Manager + +maintainers: + - Dinh Nguyen + +description: test + +properties: + compatible: + items: + - const: altr,clk-mgr + reg: + maxItems: 1 + +required: + - compatible + +examples: + - | + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + }; + +... -- cgit v1.2.3 From 0175ce4a58d6e42a707c413f21e1a1f354ea4988 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 2 Nov 2018 16:29:38 -0500 Subject: dt-bindings: i2c: Convert i2c-gpio binding to json-schema Convert the i2c-gpio binding to DT schema format using json-schema. This serves as an example of how to include other schema (i2c-controller.yaml in this case). Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/i2c/i2c-gpio.txt | 46 -------------- .../devicetree/bindings/i2c/i2c-gpio.yaml | 73 ++++++++++++++++++++++ 2 files changed, 73 insertions(+), 46 deletions(-) delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-gpio.txt create mode 100644 Documentation/devicetree/bindings/i2c/i2c-gpio.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-gpio.txt deleted file mode 100644 index 38a05562d1d2..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-gpio.txt +++ /dev/null @@ -1,46 +0,0 @@ -Device-Tree bindings for i2c gpio driver - -Required properties: - - compatible = "i2c-gpio"; - - sda-gpios: gpio used for the sda signal, this should be flagged as - active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) - from since the signal is by definition - open drain. - - scl-gpios: gpio used for the scl signal, this should be flagged as - active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) - from since the signal is by definition - open drain. - -Optional properties: - - i2c-gpio,scl-output-only: scl as output only - - i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform) - - i2c-gpio,timeout-ms: timeout to get data - -Deprecated properties, do not use in new device tree sources: - - gpios: sda and scl gpio, alternative for {sda,scl}-gpios - - i2c-gpio,sda-open-drain: this means that something outside of our - control has put the GPIO line used for SDA into open drain mode, and - that something is not the GPIO chip. It is essentially an - inconsistency flag. - - i2c-gpio,scl-open-drain: this means that something outside of our - control has put the GPIO line used for SCL into open drain mode, and - that something is not the GPIO chip. It is essentially an - inconsistency flag. - -Example nodes: - -#include - -i2c@0 { - compatible = "i2c-gpio"; - sda-gpios = <&pioA 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&pioA 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - rv3029c2@56 { - compatible = "rv3029c2"; - reg = <0x56>; - }; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-gpio.yaml b/Documentation/devicetree/bindings/i2c/i2c-gpio.yaml new file mode 100644 index 000000000000..da6129090a8e --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-gpio.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for GPIO bitbanged I2C + +maintainers: + - Wolfram Sang + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + items: + - const: i2c-gpio + + sda-gpios: + description: + gpio used for the sda signal, this should be flagged as + active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) + from since the signal is by definition + open drain. + maxItems: 1 + + scl-gpios: + description: + gpio used for the scl signal, this should be flagged as + active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) + from since the signal is by definition + open drain. + maxItems: 1 + + i2c-gpio,scl-output-only: + description: scl as output only + type: boolean + + i2c-gpio,delay-us: + description: delay between GPIO operations (may depend on each platform) + $ref: /schemas/types.yaml#/definitions/uint32 + + i2c-gpio,timeout-ms: + description: timeout to get data + $ref: /schemas/types.yaml#/definitions/uint32 + + # Deprecated properties, do not use in new device tree sources: + gpios: + minItems: 2 + maxItems: 2 + description: sda and scl gpio, alternative for {sda,scl}-gpios + + i2c-gpio,sda-open-drain: + # Generate a warning if present + not: true + description: this means that something outside of our control has put + the GPIO line used for SDA into open drain mode, and that something is + not the GPIO chip. It is essentially an inconsistency flag. + + i2c-gpio,scl-open-drain: + # Generate a warning if present + not: true + description: this means that something outside of our control has put the + GPIO line used for SCL into open drain mode, and that something is not + the GPIO chip. It is essentially an inconsistency flag. + +required: + - compatible + - sda-gpios + - scl-gpios + +... -- cgit v1.2.3 From 4d2bb3e65035954dce7c666616906004f2c049f8 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:42:37 -0500 Subject: dt-bindings: timer: Convert ARM timer bindings to json-schema Convert ARM timers to DT schema format using json-schema. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/timer/arm,arch_timer.txt | 112 ------------------- .../devicetree/bindings/timer/arm,arch_timer.yaml | 103 ++++++++++++++++++ .../bindings/timer/arm,arch_timer_mmio.yaml | 120 +++++++++++++++++++++ .../devicetree/bindings/timer/arm,global_timer.txt | 27 ----- .../bindings/timer/arm,global_timer.yaml | 46 ++++++++ 5 files changed, 269 insertions(+), 139 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer.txt create mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer.yaml create mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml delete mode 100644 Documentation/devicetree/bindings/timer/arm,global_timer.txt create mode 100644 Documentation/devicetree/bindings/timer/arm,global_timer.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.txt b/Documentation/devicetree/bindings/timer/arm,arch_timer.txt deleted file mode 100644 index 68301b77e854..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.txt +++ /dev/null @@ -1,112 +0,0 @@ -* ARM architected timer - -ARM cores may have a per-core architected timer, which provides per-cpu timers, -or a memory mapped architected timer, which provides up to 8 frames with a -physical and optional virtual timer per frame. - -The per-core architected timer is attached to a GIC to deliver its -per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC -to deliver its interrupts via SPIs. - -** CP15 Timer node properties: - -- compatible : Should at least contain one of - "arm,armv7-timer" - "arm,armv8-timer" - -- interrupts : Interrupt list for secure, non-secure, virtual and - hypervisor timers, in that order. - -- clock-frequency : The frequency of the main counter, in Hz. Should be present - only where necessary to work around broken firmware which does not configure - CNTFRQ on all CPUs to a uniform correct value. Use of this property is - strongly discouraged; fix your firmware unless absolutely impossible. - -- always-on : a boolean property. If present, the timer is powered through an - always-on power domain, therefore it never loses context. - -- fsl,erratum-a008585 : A boolean property. Indicates the presence of - QorIQ erratum A-008585, which says that reading the counter is - unreliable unless the same value is returned by back-to-back reads. - This also affects writes to the tval register, due to the implicit - counter read. - -- hisilicon,erratum-161010101 : A boolean property. Indicates the - presence of Hisilicon erratum 161010101, which says that reading the - counters is unreliable in some cases, and reads may return a value 32 - beyond the correct value. This also affects writes to the tval - registers, due to the implicit counter read. - -** Optional properties: - -- arm,cpu-registers-not-fw-configured : Firmware does not initialize - any of the generic timer CPU registers, which contain their - architecturally-defined reset values. Only supported for 32-bit - systems which follow the ARMv7 architected reset values. - -- arm,no-tick-in-suspend : The main counter does not tick when the system is in - low-power system suspend on some SoCs. This behavior does not match the - Architecture Reference Manual's specification that the system counter "must - be implemented in an always-on power domain." - - -Example: - - timer { - compatible = "arm,cortex-a15-timer", - "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - clock-frequency = <100000000>; - }; - -** Memory mapped timer node properties: - -- compatible : Should at least contain "arm,armv7-timer-mem". - -- clock-frequency : The frequency of the main counter, in Hz. Should be present - only when firmware has not configured the MMIO CNTFRQ registers. - -- reg : The control frame base address. - -Note that #address-cells, #size-cells, and ranges shall be present to ensure -the CPU can address a frame's registers. - -A timer node has up to 8 frame sub-nodes, each with the following properties: - -- frame-number: 0 to 7. - -- interrupts : Interrupt list for physical and virtual timers in that order. - The virtual timer interrupt is optional. - -- reg : The first and second view base addresses in that order. The second view - base address is optional. - -- status : "disabled" indicates the frame is not available for use. Optional. - -Example: - - timer@f0000000 { - compatible = "arm,armv7-timer-mem"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0xf0000000 0x1000>; - clock-frequency = <50000000>; - - frame@f0001000 { - frame-number = <0> - interrupts = <0 13 0x8>, - <0 14 0x8>; - reg = <0xf0001000 0x1000>, - <0xf0002000 0x1000>; - }; - - frame@f0003000 { - frame-number = <1> - interrupts = <0 15 0x8>; - reg = <0xf0003000 0x1000>; - }; - }; diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml new file mode 100644 index 000000000000..6deead07728e --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM architected timer + +maintainers: + - Marc Zyngier + - Mark Rutland +description: |+ + ARM cores may have a per-core architected timer, which provides per-cpu timers, + or a memory mapped architected timer, which provides up to 8 frames with a + physical and optional virtual timer per frame. + + The per-core architected timer is attached to a GIC to deliver its + per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC + to deliver its interrupts via SPIs. + +properties: + compatible: + oneOf: + - items: + - enum: + - arm,cortex-a15-timer + - enum: + - arm,armv7-timer + - items: + - enum: + - arm,armv7-timer + - items: + - enum: + - arm,armv8-timer + + interrupts: + items: + - description: secure timer irq + - description: non-secure timer irq + - description: virtual timer irq + - description: hypervisor timer irq + + clock-frequency: + description: The frequency of the main counter, in Hz. Should be present + only where necessary to work around broken firmware which does not configure + CNTFRQ on all CPUs to a uniform correct value. Use of this property is + strongly discouraged; fix your firmware unless absolutely impossible. + + always-on: + type: boolean + description: If present, the timer is powered through an always-on power + domain, therefore it never loses context. + + fsl,erratum-a008585: + type: boolean + description: Indicates the presence of QorIQ erratum A-008585, which says + that reading the counter is unreliable unless the same value is returned + by back-to-back reads. This also affects writes to the tval register, due + to the implicit counter read. + + hisilicon,erratum-161010101: + type: boolean + description: Indicates the presence of Hisilicon erratum 161010101, which + says that reading the counters is unreliable in some cases, and reads may + return a value 32 beyond the correct value. This also affects writes to + the tval registers, due to the implicit counter read. + + arm,cpu-registers-not-fw-configured: + type: boolean + description: Firmware does not initialize any of the generic timer CPU + registers, which contain their architecturally-defined reset values. Only + supported for 32-bit systems which follow the ARMv7 architected reset + values. + + arm,no-tick-in-suspend: + type: boolean + description: The main counter does not tick when the system is in + low-power system suspend on some SoCs. This behavior does not match the + Architecture Reference Manual's specification that the system counter "must + be implemented in an always-on power domain." + +required: + - compatible + +oneOf: + - required: + - interrupts + - required: + - interrupts-extended + +examples: + - | + timer { + compatible = "arm,cortex-a15-timer", + "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + clock-frequency = <100000000>; + }; + +... diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml new file mode 100644 index 000000000000..c4ab59550fc2 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM memory mapped architected timer + +maintainers: + - Marc Zyngier + - Mark Rutland + +description: |+ + ARM cores may have a memory mapped architected timer, which provides up to 8 + frames with a physical and optional virtual timer per frame. + + The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs. + +properties: + compatible: + items: + - enum: + - arm,armv7-timer-mem + + reg: + maxItems: 1 + description: The control frame base address + + '#address-cells': + enum: [1, 2] + + '#size-cells': + const: 1 + + clock-frequency: + description: The frequency of the main counter, in Hz. Should be present + only where necessary to work around broken firmware which does not configure + CNTFRQ on all CPUs to a uniform correct value. Use of this property is + strongly discouraged; fix your firmware unless absolutely impossible. + + always-on: + type: boolean + description: If present, the timer is powered through an always-on power + domain, therefore it never loses context. + + arm,cpu-registers-not-fw-configured: + type: boolean + description: Firmware does not initialize any of the generic timer CPU + registers, which contain their architecturally-defined reset values. Only + supported for 32-bit systems which follow the ARMv7 architected reset + values. + + arm,no-tick-in-suspend: + type: boolean + description: The main counter does not tick when the system is in + low-power system suspend on some SoCs. This behavior does not match the + Architecture Reference Manual's specification that the system counter "must + be implemented in an always-on power domain." + +patternProperties: + '^frame@[0-9a-z]*$': + description: A timer node has up to 8 frame sub-nodes, each with the following properties. + properties: + frame-number: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 7 + + interrupts: + minItems: 1 + maxItems: 2 + items: + - description: physical timer irq + - description: virtual timer irq + + reg : + minItems: 1 + maxItems: 2 + items: + - description: 1st view base address + - description: 2nd optional view base address + + required: + - frame-number + - interrupts + - reg + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +examples: + - | + timer@f0000000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xf0000000 0x1000>; + clock-frequency = <50000000>; + + frame@f0001000 { + frame-number = <0>; + interrupts = <0 13 0x8>, + <0 14 0x8>; + reg = <0xf0001000 0x1000>, + <0xf0002000 0x1000>; + }; + + frame@f0003000 { + frame-number = <1>; + interrupts = <0 15 0x8>; + reg = <0xf0003000 0x1000>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/timer/arm,global_timer.txt b/Documentation/devicetree/bindings/timer/arm,global_timer.txt deleted file mode 100644 index bdae3a818793..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,global_timer.txt +++ /dev/null @@ -1,27 +0,0 @@ - -* ARM Global Timer - Cortex-A9 are often associated with a per-core Global timer. - -** Timer node required properties: - -- compatible : should contain - * "arm,cortex-a5-global-timer" for Cortex-A5 global timers. - * "arm,cortex-a9-global-timer" for Cortex-A9 global - timers or any compatible implementation. Note: driver - supports versions r2p0 and above. - -- interrupts : One interrupt to each core - -- reg : Specify the base address and the size of the GT timer - register window. - -- clocks : Should be phandle to a clock. - -Example: - - timer@2c000600 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x2c000600 0x20>; - interrupts = <1 13 0xf01>; - clocks = <&arm_periph_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/arm,global_timer.yaml b/Documentation/devicetree/bindings/timer/arm,global_timer.yaml new file mode 100644 index 000000000000..21c24a8e28fd --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,global_timer.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/arm,global_timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Global Timer + +maintainers: + - Stuart Menefy + +description: + Cortex-A9 are often associated with a per-core Global timer. + +properties: + compatible: + items: + - enum: + - arm,cortex-a5-global-timer + - arm,cortex-a9-global-timer + + description: driver supports versions r2p0 and above. + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +examples: + - | + timer@2c000600 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x2c000600 0x20>; + interrupts = <1 13 0xf01>; + clocks = <&arm_periph_clk>; + }; +... -- cgit v1.2.3 From 672951cbd1b70a9ede6f9c6eba4ed6b726d32b03 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:41:07 -0500 Subject: dt-bindings: arm: Convert cpu binding to json-schema Convert ARM CPU binding to DT schema format using json-schema. Cc: Mark Rutland Cc: Matthias Brugger Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/cpus.txt | 490 ----------------------- Documentation/devicetree/bindings/arm/cpus.yaml | 507 ++++++++++++++++++++++++ 2 files changed, 507 insertions(+), 490 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/cpus.txt create mode 100644 Documentation/devicetree/bindings/arm/cpus.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt deleted file mode 100644 index b0198a1cf403..000000000000 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ /dev/null @@ -1,490 +0,0 @@ -================= -ARM CPUs bindings -================= - -The device tree allows to describe the layout of CPUs in a system through -the "cpus" node, which in turn contains a number of subnodes (ie "cpu") -defining properties for every cpu. - -Bindings for CPU nodes follow the Devicetree Specification, available from: - -https://www.devicetree.org/specifications/ - -with updates for 32-bit and 64-bit ARM systems provided in this document. - -================================ -Convention used in this document -================================ - -This document follows the conventions described in the Devicetree -Specification, with the addition: - -- square brackets define bitfields, eg reg[7:0] value of the bitfield in - the reg property contained in bits 7 down to 0 - -===================================== -cpus and cpu node bindings definition -===================================== - -The ARM architecture, in accordance with the Devicetree Specification, -requires the cpus and cpu nodes to be present and contain the properties -described below. - -- cpus node - - Description: Container of cpu nodes - - The node name must be "cpus". - - A cpus node must define the following properties: - - - #address-cells - Usage: required - Value type: - - Definition depends on ARM architecture version and - configuration: - - # On uniprocessor ARM architectures previous to v7 - value must be 1, to enable a simple enumeration - scheme for processors that do not have a HW CPU - identification register. - # On 32-bit ARM 11 MPcore, ARM v7 or later systems - value must be 1, that corresponds to CPUID/MPIDR - registers sizes. - # On ARM v8 64-bit systems value should be set to 2, - that corresponds to the MPIDR_EL1 register size. - If MPIDR_EL1[63:32] value is equal to 0 on all CPUs - in the system, #address-cells can be set to 1, since - MPIDR_EL1[63:32] bits are not used for CPUs - identification. - - #size-cells - Usage: required - Value type: - Definition: must be set to 0 - -- cpu node - - Description: Describes a CPU in an ARM based system - - PROPERTIES - - - device_type - Usage: required - Value type: - Definition: must be "cpu" - - reg - Usage and definition depend on ARM architecture version and - configuration: - - # On uniprocessor ARM architectures previous to v7 - this property is required and must be set to 0. - - # On ARM 11 MPcore based systems this property is - required and matches the CPUID[11:0] register bits. - - Bits [11:0] in the reg cell must be set to - bits [11:0] in CPU ID register. - - All other bits in the reg cell must be set to 0. - - # On 32-bit ARM v7 or later systems this property is - required and matches the CPU MPIDR[23:0] register - bits. - - Bits [23:0] in the reg cell must be set to - bits [23:0] in MPIDR. - - All other bits in the reg cell must be set to 0. - - # On ARM v8 64-bit systems this property is required - and matches the MPIDR_EL1 register affinity bits. - - * If cpus node's #address-cells property is set to 2 - - The first reg cell bits [7:0] must be set to - bits [39:32] of MPIDR_EL1. - - The second reg cell bits [23:0] must be set to - bits [23:0] of MPIDR_EL1. - - * If cpus node's #address-cells property is set to 1 - - The reg cell bits [23:0] must be set to bits [23:0] - of MPIDR_EL1. - - All other bits in the reg cells must be set to 0. - - - compatible: - Usage: required - Value type: - Definition: should be one of: - "arm,arm710t" - "arm,arm720t" - "arm,arm740t" - "arm,arm7ej-s" - "arm,arm7tdmi" - "arm,arm7tdmi-s" - "arm,arm9es" - "arm,arm9ej-s" - "arm,arm920t" - "arm,arm922t" - "arm,arm925" - "arm,arm926e-s" - "arm,arm926ej-s" - "arm,arm940t" - "arm,arm946e-s" - "arm,arm966e-s" - "arm,arm968e-s" - "arm,arm9tdmi" - "arm,arm1020e" - "arm,arm1020t" - "arm,arm1022e" - "arm,arm1026ej-s" - "arm,arm1136j-s" - "arm,arm1136jf-s" - "arm,arm1156t2-s" - "arm,arm1156t2f-s" - "arm,arm1176jzf" - "arm,arm1176jz-s" - "arm,arm1176jzf-s" - "arm,arm11mpcore" - "arm,cortex-a5" - "arm,cortex-a7" - "arm,cortex-a8" - "arm,cortex-a9" - "arm,cortex-a12" - "arm,cortex-a15" - "arm,cortex-a17" - "arm,cortex-a53" - "arm,cortex-a57" - "arm,cortex-a72" - "arm,cortex-a73" - "arm,cortex-m0" - "arm,cortex-m0+" - "arm,cortex-m1" - "arm,cortex-m3" - "arm,cortex-m4" - "arm,cortex-r4" - "arm,cortex-r5" - "arm,cortex-r7" - "brcm,brahma-b15" - "brcm,brahma-b53" - "brcm,vulcan" - "cavium,thunder" - "cavium,thunder2" - "faraday,fa526" - "intel,sa110" - "intel,sa1100" - "marvell,feroceon" - "marvell,mohawk" - "marvell,pj4a" - "marvell,pj4b" - "marvell,sheeva-v5" - "nvidia,tegra132-denver" - "nvidia,tegra186-denver" - "nvidia,tegra194-carmel" - "qcom,krait" - "qcom,kryo" - "qcom,kryo385" - "qcom,scorpion" - - enable-method - Value type: - Usage and definition depend on ARM architecture version. - # On ARM v8 64-bit this property is required and must - be one of: - "psci" - "spin-table" - # On ARM 32-bit systems this property is optional and - can be one of: - "actions,s500-smp" - "allwinner,sun6i-a31" - "allwinner,sun8i-a23" - "allwinner,sun9i-a80-smp" - "amlogic,meson8-smp" - "amlogic,meson8b-smp" - "arm,realview-smp" - "brcm,bcm11351-cpu-method" - "brcm,bcm23550" - "brcm,bcm2836-smp" - "brcm,bcm-nsp-smp" - "brcm,brahma-b15" - "marvell,armada-375-smp" - "marvell,armada-380-smp" - "marvell,armada-390-smp" - "marvell,armada-xp-smp" - "marvell,98dx3236-smp" - "mediatek,mt6589-smp" - "mediatek,mt81xx-tz-smp" - "qcom,gcc-msm8660" - "qcom,kpss-acc-v1" - "qcom,kpss-acc-v2" - "renesas,apmu" - "renesas,r9a06g032-smp" - "rockchip,rk3036-smp" - "rockchip,rk3066-smp" - "ste,dbx500-smp" - - - cpu-release-addr - Usage: required for systems that have an "enable-method" - property value of "spin-table". - Value type: - Definition: - # On ARM v8 64-bit systems must be a two cell - property identifying a 64-bit zero-initialised - memory location. - - - qcom,saw - Usage: required for systems that have an "enable-method" - property value of "qcom,kpss-acc-v1" or - "qcom,kpss-acc-v2" - Value type: - Definition: Specifies the SAW[1] node associated with this CPU. - - - qcom,acc - Usage: required for systems that have an "enable-method" - property value of "qcom,kpss-acc-v1" or - "qcom,kpss-acc-v2" - Value type: - Definition: Specifies the ACC[2] node associated with this CPU. - - - cpu-idle-states - Usage: Optional - Value type: - Definition: - # List of phandles to idle state nodes supported - by this cpu [3]. - - - capacity-dmips-mhz - Usage: Optional - Value type: - Definition: - # u32 value representing CPU capacity [4] in - DMIPS/MHz, relative to highest capacity-dmips-mhz - in the system. - - - rockchip,pmu - Usage: optional for systems that have an "enable-method" - property value of "rockchip,rk3066-smp" - While optional, it is the preferred way to get access to - the cpu-core power-domains. - Value type: - Definition: Specifies the syscon node controlling the cpu core - power domains. - - - dynamic-power-coefficient - Usage: optional - Value type: - Definition: A u32 value that represents the running time dynamic - power coefficient in units of uW/MHz/V^2. The - coefficient can either be calculated from power - measurements or derived by analysis. - - The dynamic power consumption of the CPU is - proportional to the square of the Voltage (V) and - the clock frequency (f). The coefficient is used to - calculate the dynamic power as below - - - Pdyn = dynamic-power-coefficient * V^2 * f - - where voltage is in V, frequency is in MHz. - -Example 1 (dual-cluster big.LITTLE system 32-bit): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - }; - }; - -Example 2 (Cortex-A8 uniprocessor 32-bit system): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - }; - }; - -Example 3 (ARM 926EJ-S uniprocessor 32-bit system): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - reg = <0x0>; - }; - }; - -Example 4 (ARM Cortex-A57 64-bit system): - -cpus { - #size-cells = <0>; - #address-cells = <2>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; -}; - --- -[1] arm/msm/qcom,saw2.txt -[2] arm/msm/qcom,kpss-acc.txt -[3] ARM Linux kernel documentation - idle states bindings - Documentation/devicetree/bindings/arm/idle-states.txt -[4] ARM Linux kernel documentation - cpu capacity bindings - Documentation/devicetree/bindings/arm/cpu-capacity.txt diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml new file mode 100644 index 000000000000..298c17b327c6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -0,0 +1,507 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM CPUs bindings + +maintainers: + - Lorenzo Pieralisi + +description: |+ + The device tree allows to describe the layout of CPUs in a system through + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") + defining properties for every cpu. + + Bindings for CPU nodes follow the Devicetree Specification, available from: + + https://www.devicetree.org/specifications/ + + with updates for 32-bit and 64-bit ARM systems provided in this document. + + ================================ + Convention used in this document + ================================ + + This document follows the conventions described in the Devicetree + Specification, with the addition: + + - square brackets define bitfields, eg reg[7:0] value of the bitfield in + the reg property contained in bits 7 down to 0 + + ===================================== + cpus and cpu node bindings definition + ===================================== + + The ARM architecture, in accordance with the Devicetree Specification, + requires the cpus and cpu nodes to be present and contain the properties + described below. + +properties: + $nodename: + const: cpus + description: Container of cpu nodes + + '#address-cells': + enum: [1, 2] + description: | + Definition depends on ARM architecture version and configuration: + + On uniprocessor ARM architectures previous to v7 + value must be 1, to enable a simple enumeration + scheme for processors that do not have a HW CPU + identification register. + On 32-bit ARM 11 MPcore, ARM v7 or later systems + value must be 1, that corresponds to CPUID/MPIDR + registers sizes. + On ARM v8 64-bit systems value should be set to 2, + that corresponds to the MPIDR_EL1 register size. + If MPIDR_EL1[63:32] value is equal to 0 on all CPUs + in the system, #address-cells can be set to 1, since + MPIDR_EL1[63:32] bits are not used for CPUs + identification. + + '#size-cells': + const: 0 + +patternProperties: + '^cpu@[0-9a-f]+$': + properties: + device_type: + const: cpu + + reg: + maxItems: 1 + description: | + Usage and definition depend on ARM architecture version and + configuration: + + On uniprocessor ARM architectures previous to v7 + this property is required and must be set to 0. + + On ARM 11 MPcore based systems this property is + required and matches the CPUID[11:0] register bits. + + Bits [11:0] in the reg cell must be set to + bits [11:0] in CPU ID register. + + All other bits in the reg cell must be set to 0. + + On 32-bit ARM v7 or later systems this property is + required and matches the CPU MPIDR[23:0] register + bits. + + Bits [23:0] in the reg cell must be set to + bits [23:0] in MPIDR. + + All other bits in the reg cell must be set to 0. + + On ARM v8 64-bit systems this property is required + and matches the MPIDR_EL1 register affinity bits. + + * If cpus node's #address-cells property is set to 2 + + The first reg cell bits [7:0] must be set to + bits [39:32] of MPIDR_EL1. + + The second reg cell bits [23:0] must be set to + bits [23:0] of MPIDR_EL1. + + * If cpus node's #address-cells property is set to 1 + + The reg cell bits [23:0] must be set to bits [23:0] + of MPIDR_EL1. + + All other bits in the reg cells must be set to 0. + + compatible: + items: + - enum: + - arm,arm710t + - arm,arm720t + - arm,arm740t + - arm,arm7ej-s + - arm,arm7tdmi + - arm,arm7tdmi-s + - arm,arm9es + - arm,arm9ej-s + - arm,arm920t + - arm,arm922t + - arm,arm925 + - arm,arm926e-s + - arm,arm926ej-s + - arm,arm940t + - arm,arm946e-s + - arm,arm966e-s + - arm,arm968e-s + - arm,arm9tdmi + - arm,arm1020e + - arm,arm1020t + - arm,arm1022e + - arm,arm1026ej-s + - arm,arm1136j-s + - arm,arm1136jf-s + - arm,arm1156t2-s + - arm,arm1156t2f-s + - arm,arm1176jzf + - arm,arm1176jz-s + - arm,arm1176jzf-s + - arm,arm11mpcore + - arm,armv8 # Only for s/w models + - arm,cortex-a5 + - arm,cortex-a7 + - arm,cortex-a8 + - arm,cortex-a9 + - arm,cortex-a12 + - arm,cortex-a15 + - arm,cortex-a17 + - arm,cortex-a53 + - arm,cortex-a57 + - arm,cortex-a72 + - arm,cortex-a73 + - arm,cortex-m0 + - arm,cortex-m0+ + - arm,cortex-m1 + - arm,cortex-m3 + - arm,cortex-m4 + - arm,cortex-r4 + - arm,cortex-r5 + - arm,cortex-r7 + - brcm,brahma-b15 + - brcm,brahma-b53 + - brcm,vulcan + - cavium,thunder + - cavium,thunder2 + - faraday,fa526 + - intel,sa110 + - intel,sa1100 + - marvell,feroceon + - marvell,mohawk + - marvell,pj4a + - marvell,pj4b + - marvell,sheeva-v5 + - marvell,sheeva-v7 + - nvidia,tegra132-denver + - nvidia,tegra186-denver + - nvidia,tegra194-carmel + - qcom,krait + - qcom,kryo + - qcom,kryo385 + - qcom,scorpion + + enable-method: + allOf: + - $ref: '/schemas/types.yaml#/definitions/string' + - oneOf: + # On ARM v8 64-bit this property is required + - enum: + - psci + - spin-table + # On ARM 32-bit systems this property is optional + - enum: + - actions,s500-smp + - allwinner,sun6i-a31 + - allwinner,sun8i-a23 + - allwinner,sun9i-a80-smp + - allwinner,sun8i-a83t-smp + - amlogic,meson8-smp + - amlogic,meson8b-smp + - arm,realview-smp + - brcm,bcm11351-cpu-method + - brcm,bcm23550 + - brcm,bcm2836-smp + - brcm,bcm63138 + - brcm,bcm-nsp-smp + - brcm,brahma-b15 + - marvell,armada-375-smp + - marvell,armada-380-smp + - marvell,armada-390-smp + - marvell,armada-xp-smp + - marvell,98dx3236-smp + - mediatek,mt6589-smp + - mediatek,mt81xx-tz-smp + - qcom,gcc-msm8660 + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + - renesas,apmu + - renesas,r9a06g032-smp + - rockchip,rk3036-smp + - rockchip,rk3066-smp + - ste,dbx500-smp + + cpu-release-addr: + $ref: '/schemas/types.yaml#/definitions/uint64' + + description: + Required for systems that have an "enable-method" + property value of "spin-table". + On ARM v8 64-bit systems must be a two cell + property identifying a 64-bit zero-initialised + memory location. + + cpu-idle-states: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: | + List of phandles to idle state nodes supported + by this cpu (see ./idle-states.txt). + + capacity-dmips-mhz: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + u32 value representing CPU capacity (see ./cpu-capacity.txt) in + DMIPS/MHz, relative to highest capacity-dmips-mhz + in the system. + + dynamic-power-coefficient: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + A u32 value that represents the running time dynamic + power coefficient in units of uW/MHz/V^2. The + coefficient can either be calculated from power + measurements or derived by analysis. + + The dynamic power consumption of the CPU is + proportional to the square of the Voltage (V) and + the clock frequency (f). The coefficient is used to + calculate the dynamic power as below - + + Pdyn = dynamic-power-coefficient * V^2 * f + + where voltage is in V, frequency is in MHz. + + qcom,saw: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the SAW* node associated with this CPU. + + Required for systems that have an "enable-method" property + value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" + + * arm/msm/qcom,saw2.txt + + qcom,acc: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the ACC* node associated with this CPU. + + Required for systems that have an "enable-method" property + value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" + + * arm/msm/qcom,kpss-acc.txt + + rockchip,pmu: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the syscon node controlling the cpu core power domains. + + Optional for systems that have an "enable-method" + property value of "rockchip,rk3066-smp" + While optional, it is the preferred way to get access to + the cpu-core power-domains. + + required: + - device_type + - reg + - compatible + + dependencies: + cpu-release-addr: [enable-method] + rockchip,pmu: [enable-method] + +required: + - '#address-cells' + - '#size-cells' + +examples: + - | + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + }; + }; + + - | + // Example 2 (Cortex-A8 uniprocessor 32-bit system): + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + }; + }; + + - | + // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + - | + // Example 4 (ARM Cortex-A57 64-bit system): + cpus { + #size-cells = <0>; + #address-cells = <2>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + }; +... -- cgit v1.2.3 From d3c207eeb9059cf055a887f15e5f41b096386448 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:42:04 -0500 Subject: dt-bindings: arm: Convert primecell binding to json-schema Convert ARM Primecell binding to DT schema format using json-schema. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/primecell.txt | 46 ---------------------- .../devicetree/bindings/arm/primecell.yaml | 36 +++++++++++++++++ 2 files changed, 36 insertions(+), 46 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/primecell.txt create mode 100644 Documentation/devicetree/bindings/arm/primecell.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt deleted file mode 100644 index 0df6acacfaea..000000000000 --- a/Documentation/devicetree/bindings/arm/primecell.txt +++ /dev/null @@ -1,46 +0,0 @@ -* ARM Primecell Peripherals - -ARM, Ltd. Primecell peripherals have a standard id register that can be used to -identify the peripheral type, vendor, and revision. This value can be used for -driver matching. - -Required properties: - -- compatible : should be a specific name for the peripheral and - "arm,primecell". The specific name will match the ARM - engineering name for the logic block in the form: "arm,pl???" - -Optional properties: - -- arm,primecell-periphid : Value to override the h/w value with -- clocks : From common clock binding. First clock is phandle to clock for apb - pclk. Additional clocks are optional and specific to those peripherals. -- clock-names : From common clock binding. Shall be "apb_pclk" for first clock. -- dmas : From common DMA binding. If present, refers to one or more dma channels. -- dma-names : From common DMA binding, needs to match the 'dmas' property. - Devices with exactly one receive and transmit channel shall name - these "rx" and "tx", respectively. -- pinctrl- : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt -- pinctrl-names : Names corresponding to the numbered pinctrl states -- interrupts : one or more interrupt specifiers -- interrupt-names : names corresponding to the interrupts properties - -Example: - -serial@fff36000 { - compatible = "arm,pl011", "arm,primecell"; - arm,primecell-periphid = <0x00341011>; - - clocks = <&pclk>; - clock-names = "apb_pclk"; - - dmas = <&dma-controller 4>, <&dma-controller 5>; - dma-names = "rx", "tx"; - - pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>; - pinctrl-1 = <&uart0_sleep_mode>; - pinctrl-names = "default","sleep"; - - interrupts = <0 11 0x4>; -}; - diff --git a/Documentation/devicetree/bindings/arm/primecell.yaml b/Documentation/devicetree/bindings/arm/primecell.yaml new file mode 100644 index 000000000000..5aae37f1c563 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/primecell.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/primecell.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Primecell Peripherals + +maintainers: + - Rob Herring + +description: |+ + ARM, Ltd. Primecell peripherals have a standard id register that can be used to + identify the peripheral type, vendor, and revision. This value can be used for + driver matching. + +properties: + compatible: + contains: + const: arm,primecell + description: + Should be a specific name for the peripheral followed by "arm,primecell". + The specific name will match the ARM engineering name for the logic block + in the form "arm,pl???" + + arm,primecell-periphid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Value to override the h/w ID value + clocks: + minItems: 1 + maxItems: 32 + clock-names: + contains: + const: apb_pclk + additionalItems: true +... -- cgit v1.2.3 From f8139316cab4f3e5cf31b65157b27e785e05965b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:46:53 -0500 Subject: dt-bindings: arm: Convert Altera board/soc bindings to json-schema Convert Altera SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Acked-by: Dinh Nguyen Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/altera.txt | 14 -------------- Documentation/devicetree/bindings/arm/altera.yaml | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 14 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/altera.txt create mode 100644 Documentation/devicetree/bindings/arm/altera.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/altera.txt b/Documentation/devicetree/bindings/arm/altera.txt deleted file mode 100644 index 558735aacca8..000000000000 --- a/Documentation/devicetree/bindings/arm/altera.txt +++ /dev/null @@ -1,14 +0,0 @@ -Altera's SoCFPGA platform device tree bindings ---------------------------------------------- - -Boards with Cyclone 5 SoC: -Required root node properties: -compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - -Boards with Arria 5 SoC: -Required root node properties: -compatible = "altr,socfpga-arria5", "altr,socfpga"; - -Boards with Arria 10 SoC: -Required root node properties: -compatible = "altr,socfpga-arria10", "altr,socfpga"; diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml new file mode 100644 index 000000000000..49e0362ddc11 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/altera.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera's SoCFPGA platform device tree bindings + +maintainers: + - Dinh Nguyen + +properties: + compatible: + items: + - enum: + - altr,socfpga-cyclone5 + - altr,socfpga-arria5 + - altr,socfpga-arria10 + - const: altr,socfpga +... -- cgit v1.2.3 From c2dacddc5f6772f38bf04c950967fe41bb5c9600 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:47:39 -0500 Subject: dt-bindings: arm: Convert Calxeda board/soc bindings to json-schema Convert Calxeda SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/calxeda.txt | 15 --------------- Documentation/devicetree/bindings/arm/calxeda.yaml | 22 ++++++++++++++++++++++ 2 files changed, 22 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt create mode 100644 Documentation/devicetree/bindings/arm/calxeda.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt deleted file mode 100644 index 25fcf96795ca..000000000000 --- a/Documentation/devicetree/bindings/arm/calxeda.txt +++ /dev/null @@ -1,15 +0,0 @@ -Calxeda Platforms Device Tree Bindings ------------------------------------------------ - -Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the -following properties. - -Required root node properties: - - compatible = "calxeda,highbank"; - - -Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following -properties. - -Required root node properties: - - compatible = "calxeda,ecx-2000"; diff --git a/Documentation/devicetree/bindings/arm/calxeda.yaml b/Documentation/devicetree/bindings/arm/calxeda.yaml new file mode 100644 index 000000000000..aa5571d23c39 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/calxeda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Platforms Device Tree Bindings + +maintainers: + - Rob Herring +description: |+ + Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC + or Cortex-A15 based ECX-2000 SOCs + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - calxeda,highbank + - calxeda,ecx-2000 -- cgit v1.2.3 From fdb0436c35b86759da6d7fce27323e3cdced0e13 Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Tue, 11 Dec 2018 17:17:07 +0200 Subject: dt-bindings: mfd: axp20x: add support for regulator-ramp-delay for AXP209 The AXP209 supports ramping up voltages on several regulators such as DCDC2 and LDO3, therefore we can use the standard 'regulator-ramp-delay' property for those 2 regulators. Note that the voltage ramp only works when the regulator is already enabled. E.g. when going from say 0.7 V to 3.6 V. When turning on the regulator, no voltage ramp is performed in hardware. What this means, is that if the bootloader brings up the voltage at 0.7 V, the ramp delay property is properly applied. If however, the bootloader leaves the power off, no ramp delay is applied when the power is enabled by the regulator framework. Signed-off-by: Olliver Schinagl Signed-off-by: Priit Laes Acked-for-MFD-by: Lee Jones Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/mfd/axp20x.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt index 188f0373d441..c6266052d23f 100644 --- a/Documentation/devicetree/bindings/mfd/axp20x.txt +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt @@ -32,6 +32,12 @@ Required properties: - interrupt-controller: The PMIC has its own internal IRQs - #interrupt-cells: Should be set to 1 +Supported common regulator properties, see ../regulator/regulator.txt for +more information: +- regulator-ramp-delay: sets the ramp up delay in uV/us + AXP20x/DCDC2: 1600, 800 + AXP20x/LDO3: 1600, 800 + Optional properties: - x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz AXP152/20X: range: 750-1875, Default: 1.5 MHz -- cgit v1.2.3 From eb51c6eb9775d5e7ef810327dbc84bb0d15f72b5 Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Tue, 11 Dec 2018 17:17:09 +0200 Subject: dt-bindings: mfd: axp20x: Add software based soft_start for AXP209 LDO3 In the past, there have been words on various lists that if LDO3 is disabled in u-boot, but enabled in the DTS, the axp209 driver would fail to continue/hang. Several enable/disable patches have been issues to devicetree's in both the kernel and u-boot to address this issue. What really happened however, was that the AXP209 shuts down without a notice and without setting an interrupt. This is caused when LDO3 gets overloaded, for example with large capacitors on the LDO3 output. Normally, we would expect that AXP209 would source 200 mA as per datasheet and set and trigger an interrupt when being overloaded. For some reason however, this does not happen. As a work-around, implement software-based 'regulator-soft-start' property for AXP209 LDO3 regulator, which is used to first bring up the LDO3 to the lowest possible voltage and then enable the LDO. After that, we can set the requested voltage as usual. Combining this setting with the regulator-ramp-delay allows LDO3 to come up slowly and staggered, potentially reducing overall inrush current. Signed-off-by: Olliver Schinagl Signed-off-by: Priit Laes Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/mfd/axp20x.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt index c6266052d23f..2af4ff95d6bc 100644 --- a/Documentation/devicetree/bindings/mfd/axp20x.txt +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt @@ -37,6 +37,9 @@ more information: - regulator-ramp-delay: sets the ramp up delay in uV/us AXP20x/DCDC2: 1600, 800 AXP20x/LDO3: 1600, 800 +- regulator-soft-start: enable the output at the lowest possible voltage and + only then set the desired voltage + AXP20x/LDO3: software-based implementation Optional properties: - x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz -- cgit v1.2.3 From 5afa43780f7c735ee83a015db69821b45a011ef6 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:49:44 -0500 Subject: dt-bindings: arm: Convert TI davinci board/soc bindings to json-schema Convert TI Davinci SoC bindings to DT schema format using json-schema. Reviewed-by: Sekhar Nori Cc: Kevin Hilman Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/davinci.txt | 25 --------------------- .../devicetree/bindings/arm/ti/ti,davinci.yaml | 26 ++++++++++++++++++++++ 2 files changed, 26 insertions(+), 25 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/davinci.txt create mode 100644 Documentation/devicetree/bindings/arm/ti/ti,davinci.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/davinci.txt b/Documentation/devicetree/bindings/arm/davinci.txt deleted file mode 100644 index 715622c36260..000000000000 --- a/Documentation/devicetree/bindings/arm/davinci.txt +++ /dev/null @@ -1,25 +0,0 @@ -Texas Instruments DaVinci Platforms Device Tree Bindings --------------------------------------------------------- - -DA850/OMAP-L138/AM18x Evaluation Module (EVM) board -Required root node properties: - - compatible = "ti,da850-evm", "ti,da850"; - -DA850/OMAP-L138/AM18x L138/C6748 Development Kit (LCDK) board -Required root node properties: - - compatible = "ti,da850-lcdk", "ti,da850"; - -EnBW AM1808 based CMC board -Required root node properties: - - compatible = "enbw,cmc", "ti,da850; - -LEGO MINDSTORMS EV3 (AM1808 based) -Required root node properties: - - compatible = "lego,ev3", "ti,da850"; - -Generic DaVinci Boards ----------------------- - -DA850/OMAP-L138/AM18x generic board -Required root node properties: - - compatible = "ti,da850"; diff --git a/Documentation/devicetree/bindings/arm/ti/ti,davinci.yaml b/Documentation/devicetree/bindings/arm/ti/ti,davinci.yaml new file mode 100644 index 000000000000..4326d2cfa15d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ti/ti,davinci.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ti/davinci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DaVinci Platforms Device Tree Bindings + +maintainers: + - Sekhar Nori + +description: + DA850/OMAP-L138/AM18x based boards + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - ti,da850-evm # DA850/OMAP-L138/AM18x Evaluation Module (EVM) board + - ti,da850-lcdk # DA850/OMAP-L138/AM18x L138/C6748 Development Kit (LCDK) board + - enbw,cmc # EnBW AM1808 based CMC board + - lego,ev3 # LEGO MINDSTORMS EV3 (AM1808 based) + - const: ti,da850 +... -- cgit v1.2.3 From da5faf32ad2d74144c14f1c8212e0063a3dc1d0b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:52:51 -0500 Subject: dt-bindings: arm: Convert TI nspire board/soc bindings to json-schema Convert TI NSpire SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/nspire.txt | 14 ------------- .../devicetree/bindings/arm/ti/nspire.yaml | 24 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 14 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/nspire.txt create mode 100644 Documentation/devicetree/bindings/arm/ti/nspire.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/nspire.txt b/Documentation/devicetree/bindings/arm/nspire.txt deleted file mode 100644 index 4d08518bd176..000000000000 --- a/Documentation/devicetree/bindings/arm/nspire.txt +++ /dev/null @@ -1,14 +0,0 @@ -TI-NSPIRE calculators - -Required properties: -- compatible: Compatible property value should contain "ti,nspire". - CX models should have "ti,nspire-cx" - Touchpad models should have "ti,nspire-tp" - Clickpad models should have "ti,nspire-clp" - -Example: - -/ { - model = "TI-NSPIRE CX"; - compatible = "ti,nspire-cx"; - ... diff --git a/Documentation/devicetree/bindings/arm/ti/nspire.yaml b/Documentation/devicetree/bindings/arm/ti/nspire.yaml new file mode 100644 index 000000000000..e372b43da62f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ti/nspire.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ti/nspire.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-NSPIRE calculators + +maintainers: + - Daniel Tang + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + # CX models + - ti,nspire-cx + # Touchpad models + - ti,nspire-tp + # Clickpad models + - ti,nspire-clp +... -- cgit v1.2.3 From 9d3ef77fe5688b761bdee91803af0c613717b52e Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:53:47 -0500 Subject: dt-bindings: arm: Convert QCom board/soc bindings to json-schema Convert QCom SoC bindings to DT schema format using json-schema. Acked-by: Andy Gross Cc: David Brown Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/qcom.txt | 57 ----------- Documentation/devicetree/bindings/arm/qcom.yaml | 125 ++++++++++++++++++++++++ 2 files changed, 125 insertions(+), 57 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/qcom.txt create mode 100644 Documentation/devicetree/bindings/arm/qcom.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt deleted file mode 100644 index ee532e705d6c..000000000000 --- a/Documentation/devicetree/bindings/arm/qcom.txt +++ /dev/null @@ -1,57 +0,0 @@ -QCOM device tree bindings -------------------------- - -Some qcom based bootloaders identify the dtb blob based on a set of -device properties like SoC and platform and revisions of those components. -To support this scheme, we encode this information into the board compatible -string. - -Each board must specify a top-level board compatible string with the following -format: - - compatible = "qcom,[-][-]-[/][-]" - -The 'SoC' and 'board' elements are required. All other elements are optional. - -The 'SoC' element must be one of the following strings: - - apq8016 - apq8074 - apq8084 - apq8096 - msm8916 - msm8974 - msm8992 - msm8994 - msm8996 - mdm9615 - ipq8074 - sdm845 - -The 'board' element must be one of the following strings: - - cdp - liquid - dragonboard - mtp - sbc - hk01 - -The 'soc_version' and 'board_version' elements take the form of v. -where the minor number may be omitted when it's zero, i.e. v1.0 is the same -as v1. If all versions of the 'board_version' elements match, then a -wildcard '*' should be used, e.g. 'v*'. - -The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9. - -Examples: - - "qcom,msm8916-v1-cdp-pm8916-v2.1" - -A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version -2.1. - - "qcom,apq8074-v2.0-2-dragonboard/1-v0.1" - -A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in -foundry 2. diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml new file mode 100644 index 000000000000..f6316ab66385 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/qcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QCOM device tree bindings + +maintainers: + - Stephen Boyd + +description: | + Some qcom based bootloaders identify the dtb blob based on a set of + device properties like SoC and platform and revisions of those components. + To support this scheme, we encode this information into the board compatible + string. + + Each board must specify a top-level board compatible string with the following + format: + + compatible = "qcom,[-][-]-[/][-]" + + The 'SoC' and 'board' elements are required. All other elements are optional. + + The 'SoC' element must be one of the following strings: + + apq8016 + apq8074 + apq8084 + apq8096 + msm8916 + msm8974 + msm8992 + msm8994 + msm8996 + mdm9615 + ipq8074 + sdm845 + + The 'board' element must be one of the following strings: + + cdp + liquid + dragonboard + mtp + sbc + hk01 + + The 'soc_version' and 'board_version' elements take the form of v. + where the minor number may be omitted when it's zero, i.e. v1.0 is the same + as v1. If all versions of the 'board_version' elements match, then a + wildcard '*' should be used, e.g. 'v*'. + + The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9. + + Examples: + + "qcom,msm8916-v1-cdp-pm8916-v2.1" + + A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version + 2.1. + + "qcom,apq8074-v2.0-2-dragonboard/1-v0.1" + + A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in + foundry 2. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,apq8016-sbc + - const: qcom,apq8016 + + - items: + - enum: + - qcom,apq8064-cm-qs600 + - qcom,apq8064-ifc6410 + - const: qcom,apq8064 + + - items: + - enum: + - qcom,apq8074-dragonboard + - const: qcom,apq8074 + + - items: + - enum: + - qcom,apq8060-dragonboard + - qcom,msm8660-surf + - const: qcom,msm8660 + + - items: + - enum: + - qcom,apq8084-mtp + - qcom,apq8084-sbc + - const: qcom,apq8084 + + - items: + - enum: + - qcom,msm8960-cdp + - const: qcom,msm8960 + + - items: + - const: qcom,msm8916-mtp/1 + - const: qcom,msm8916-mtp + - const: qcom,msm8916 + + - items: + - const: qcom,msm8996-mtp + + - items: + - const: qcom,ipq4019 + + - items: + - enum: + - qcom,ipq8064-ap148 + - const: qcom,ipq8064 + + - items: + - enum: + - qcom,ipq8074-hk01 + - const: qcom,ipq8074 + +... -- cgit v1.2.3 From cf7e48dad101d648e8d569d84247cd20163871ff Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:55:23 -0500 Subject: dt-bindings: arm: Convert CSR SiRF board/soc bindings to json-schema Convert CSR SiRF SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Barry Song Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/sirf.txt | 11 ---------- Documentation/devicetree/bindings/arm/sirf.yaml | 27 +++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 11 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/sirf.txt create mode 100644 Documentation/devicetree/bindings/arm/sirf.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/sirf.txt b/Documentation/devicetree/bindings/arm/sirf.txt deleted file mode 100644 index 7b28ee6fee91..000000000000 --- a/Documentation/devicetree/bindings/arm/sirf.txt +++ /dev/null @@ -1,11 +0,0 @@ -CSR SiRFprimaII and SiRFmarco device tree bindings. -======================================== - -Required root node properties: - - compatible: - - "sirf,atlas6-cb" : atlas6 "cb" evaluation board - - "sirf,atlas6" : atlas6 device based board - - "sirf,atlas7-cb" : atlas7 "cb" evaluation board - - "sirf,atlas7" : atlas7 device based board - - "sirf,prima2-cb" : prima2 "cb" evaluation board - - "sirf,prima2" : prima2 device based board diff --git a/Documentation/devicetree/bindings/arm/sirf.yaml b/Documentation/devicetree/bindings/arm/sirf.yaml new file mode 100644 index 000000000000..0b597032c923 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sirf.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sirf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CSR SiRFprimaII and SiRFmarco device tree bindings. + +maintainers: + - Binghua Duan + - Barry Song + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: sirf,atlas6-cb + - const: sirf,atlas6 + - items: + - const: sirf,atlas7-cb + - const: sirf,atlas7 + - items: + - const: sirf,prima2-cb + - const: sirf,prima2 +... -- cgit v1.2.3 From 26282485aedd93528b15bc3f7e1d03d3ca9a3d98 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:56:08 -0500 Subject: dt-bindings: arm: Convert SPEAr board/soc bindings to json-schema Convert SPEAr SoC bindings to DT schema format using json-schema. Cc: Shiraz Hashim Cc: Mark Rutland Cc: devicetree@vger.kernel.org Acked-by: Viresh Kumar Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/spear.txt | 26 ------------------------ Documentation/devicetree/bindings/arm/spear.yaml | 25 +++++++++++++++++++++++ 2 files changed, 25 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/spear.txt create mode 100644 Documentation/devicetree/bindings/arm/spear.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt deleted file mode 100644 index 0d42949df6c2..000000000000 --- a/Documentation/devicetree/bindings/arm/spear.txt +++ /dev/null @@ -1,26 +0,0 @@ -ST SPEAr Platforms Device Tree Bindings ---------------------------------------- - -Boards with the ST SPEAr600 SoC shall have the following properties: -Required root node property: -compatible = "st,spear600"; - -Boards with the ST SPEAr300 SoC shall have the following properties: -Required root node property: -compatible = "st,spear300"; - -Boards with the ST SPEAr310 SoC shall have the following properties: -Required root node property: -compatible = "st,spear310"; - -Boards with the ST SPEAr320 SoC shall have the following properties: -Required root node property: -compatible = "st,spear320"; - -Boards with the ST SPEAr1310 SoC shall have the following properties: -Required root node property: -compatible = "st,spear1310"; - -Boards with the ST SPEAr1340 SoC shall have the following properties: -Required root node property: -compatible = "st,spear1340"; diff --git a/Documentation/devicetree/bindings/arm/spear.yaml b/Documentation/devicetree/bindings/arm/spear.yaml new file mode 100644 index 000000000000..f6ec731c9531 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/spear.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/spear.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST SPEAr Platforms Device Tree Bindings + +maintainers: + - Viresh Kumar + - Stefan Roese + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - st,spear600 + - st,spear300 + - st,spear310 + - st,spear320 + - st,spear1310 + - st,spear1340 +... -- cgit v1.2.3 From c74acbf039ca5b68363f804971cd63d0e78e8529 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:56:27 -0500 Subject: dt-bindings: arm: Convert ST STi board/soc bindings to json-schema Convert ST STi SoC bindings to DT schema format using json-schema. Acked-by: Patrice Chotard Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/sti.txt | 23 ----------------------- Documentation/devicetree/bindings/arm/sti.yaml | 23 +++++++++++++++++++++++ 2 files changed, 23 insertions(+), 23 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/sti.txt create mode 100644 Documentation/devicetree/bindings/arm/sti.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/sti.txt b/Documentation/devicetree/bindings/arm/sti.txt deleted file mode 100644 index 8d27f6b084c7..000000000000 --- a/Documentation/devicetree/bindings/arm/sti.txt +++ /dev/null @@ -1,23 +0,0 @@ -ST STi Platforms Device Tree Bindings ---------------------------------------- - -Boards with the ST STiH415 SoC shall have the following properties: -Required root node property: -compatible = "st,stih415"; - -Boards with the ST STiH416 SoC shall have the following properties: -Required root node property: -compatible = "st,stih416"; - -Boards with the ST STiH407 SoC shall have the following properties: -Required root node property: -compatible = "st,stih407"; - -Boards with the ST STiH410 SoC shall have the following properties: -Required root node property: -compatible = "st,stih410"; - -Boards with the ST STiH418 SoC shall have the following properties: -Required root node property: -compatible = "st,stih418"; - diff --git a/Documentation/devicetree/bindings/arm/sti.yaml b/Documentation/devicetree/bindings/arm/sti.yaml new file mode 100644 index 000000000000..47f9b8eebaa0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sti.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sti.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST STi Platforms Device Tree Bindings + +maintainers: + - Patrice Chotard + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - st,stih415 + - st,stih416 + - st,stih407 + - st,stih410 + - st,stih418 +... -- cgit v1.2.3 From f3fb5732e3bde702f9ae0aef6c96ee60799459b5 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:57:10 -0500 Subject: dt-bindings: arm: Convert VIA board/soc bindings to json-schema Convert VIA SoC bindings to DT schema format using json-schema. Cc: Tony Prisk Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/vt8500.txt | 22 ---------------------- Documentation/devicetree/bindings/arm/vt8500.yaml | 23 +++++++++++++++++++++++ 2 files changed, 23 insertions(+), 22 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/vt8500.txt create mode 100644 Documentation/devicetree/bindings/arm/vt8500.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/vt8500.txt b/Documentation/devicetree/bindings/arm/vt8500.txt deleted file mode 100644 index 87dc1ddf4770..000000000000 --- a/Documentation/devicetree/bindings/arm/vt8500.txt +++ /dev/null @@ -1,22 +0,0 @@ -VIA/Wondermedia VT8500 Platforms Device Tree Bindings ---------------------------------------- - -Boards with the VIA VT8500 SoC shall have the following properties: -Required root node property: -compatible = "via,vt8500"; - -Boards with the Wondermedia WM8505 SoC shall have the following properties: -Required root node property: -compatible = "wm,wm8505"; - -Boards with the Wondermedia WM8650 SoC shall have the following properties: -Required root node property: -compatible = "wm,wm8650"; - -Boards with the Wondermedia WM8750 SoC shall have the following properties: -Required root node property: -compatible = "wm,wm8750"; - -Boards with the Wondermedia WM8850 SoC shall have the following properties: -Required root node property: -compatible = "wm,wm8850"; diff --git a/Documentation/devicetree/bindings/arm/vt8500.yaml b/Documentation/devicetree/bindings/arm/vt8500.yaml new file mode 100644 index 000000000000..7b25b6fa34e9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/vt8500.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/vt8500.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA/Wondermedia VT8500 Platforms Device Tree Bindings + +maintainers: + - Tony Prisk +description: test + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - via,vt8500 + - wm,wm8505 + - wm,wm8650 + - wm,wm8750 + - wm,wm8850 -- cgit v1.2.3 From c808c7b950ce0e106e8d6eef8d54ec409483c319 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 20 Mar 2018 05:38:45 -0500 Subject: dt-bindings: arm: Convert Xilinx board/soc bindings to json-schema Convert Xilinx SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Acked-by: Michal Simek Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 83 ----------------------- Documentation/devicetree/bindings/arm/xilinx.yaml | 82 ++++++++++++++++++++++ 2 files changed, 82 insertions(+), 83 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/xilinx.txt create mode 100644 Documentation/devicetree/bindings/arm/xilinx.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt deleted file mode 100644 index 26fe5ecc4332..000000000000 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ /dev/null @@ -1,83 +0,0 @@ -Xilinx Zynq Platforms Device Tree Bindings - -Boards with Zynq-7000 SOC based on an ARM Cortex A9 processor -shall have the following properties. - -Required root node properties: - - compatible = "xlnx,zynq-7000"; - -Additional compatible strings: - -- Adapteva Parallella board - "adapteva,parallella" - -- Avnet MicroZed board - "avnet,zynq-microzed" - "xlnx,zynq-microzed" - -- Avnet ZedBoard board - "avnet,zynq-zed" - "xlnx,zynq-zed" - -- Digilent Zybo board - "digilent,zynq-zybo" - -- Digilent Zybo Z7 board - "digilent,zynq-zybo-z7" - -- Xilinx CC108 internal board - "xlnx,zynq-cc108" - -- Xilinx ZC702 internal board - "xlnx,zynq-zc702" - -- Xilinx ZC706 internal board - "xlnx,zynq-zc706" - -- Xilinx ZC770 internal board, with different FMC cards - "xlnx,zynq-zc770-xm010" - "xlnx,zynq-zc770-xm011" - "xlnx,zynq-zc770-xm012" - "xlnx,zynq-zc770-xm013" - ---------------------------------------------------------------- - -Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings - -Boards with ZynqMP SOC based on an ARM Cortex A53 processor -shall have the following properties. - -Required root node properties: - - compatible = "xlnx,zynqmp"; - - -Additional compatible strings: - -- Xilinx internal board zc1232 - "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232" - -- Xilinx internal board zc1254 - "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254" - -- Xilinx internal board zc1275 - "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275" - -- Xilinx internal board zc1751 - "xlnx,zynqmp-zc1751" - -- Xilinx 96boards compatible board zcu100 - "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100" - -- Xilinx evaluation board zcu102 - "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102" - "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102" - "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102" - -- Xilinx evaluation board zcu104 - "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104" - -- Xilinx evaluation board zcu106 - "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106" - -- Xilinx evaluation board zcu111 - "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111" diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml new file mode 100644 index 000000000000..64cd21b737af --- /dev/null +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/xilinx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynq Platforms Device Tree Bindings + +maintainers: + - Michal Simek + +description: | + Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - adapteva,parallella + - digilent,zynq-zybo + - digilent,zynq-zybo-z7 + - xlnx,zynq-cc108 + - xlnx,zynq-zc702 + - xlnx,zynq-zc706 + - xlnx,zynq-zc770-xm010 + - xlnx,zynq-zc770-xm011 + - xlnx,zynq-zc770-xm012 + - xlnx,zynq-zc770-xm013 + - const: xlnx,zynq-7000 + + - items: + - const: avnet,zynq-microzed + - const: xlnx,zynq-microzed + - const: xlnx,zynq-7000 + + - items: + - const: avnet,zynq-zed + - const: xlnx,zynq-zed + - const: xlnx,zynq-7000 + + - items: + - enum: + - xlnx,zynqmp-zc1751 + - const: xlnx,zynqmp + + - description: Xilinx internal board zc1232 + items: + - const: xlnx,zynqmp-zc1232-revA + - const: xlnx,zynqmp-zc1232 + - const: xlnx,zynqmp + + - description: Xilinx internal board zc1254 + items: + - const: xlnx,zynqmp-zc1254-revA + - const: xlnx,zynqmp-zc1254 + - const: xlnx,zynqmp + + - description: Xilinx internal board zc1275 + items: + - const: xlnx,zynqmp-zc1275-revA + - const: xlnx,zynqmp-zc1275 + - const: xlnx,zynqmp + + - description: Xilinx 96boards compatible board zcu100 + items: + - const: xlnx,zynqmp-zcu100-revC + - const: xlnx,zynqmp-zcu100 + - const: xlnx,zynqmp + + - description: Xilinx evaluation board zcu102 + items: + - enum: + - xlnx,zynqmp-zcu102-revA + - xlnx,zynqmp-zcu102-revB + - xlnx,zynqmp-zcu102-rev1.0 + - const: xlnx,zynqmp-zcu102 + - const: xlnx,zynqmp + +... -- cgit v1.2.3 From 3da3d9be44954d5b0b5d0fdfc0aafaa2a905d206 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 8 Nov 2018 14:28:54 +0100 Subject: dt-bindings: arm: Add missing Xilinx boards Add missing description for Ultra96, zcu104, zcu106 and zcu111. Signed-off-by: Michal Simek Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.yaml | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml index 64cd21b737af..c73b1f5c7f49 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.yaml +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml @@ -70,6 +70,14 @@ properties: - const: xlnx,zynqmp-zcu100 - const: xlnx,zynqmp + - description: Xilinx 96boards compatible board Ultra96 + items: + - const: avnet,ultra96-rev1 + - const: avnet,ultra96 + - const: xlnx,zynqmp-zcu100-revC + - const: xlnx,zynqmp-zcu100 + - const: xlnx,zynqmp + - description: Xilinx evaluation board zcu102 items: - enum: @@ -79,4 +87,28 @@ properties: - const: xlnx,zynqmp-zcu102 - const: xlnx,zynqmp + - description: Xilinx evaluation board zcu104 + items: + - enum: + - xlnx,zynqmp-zcu104-revA + - xlnx,zynqmp-zcu104-rev1.0 + - const: xlnx,zynqmp-zcu104 + - const: xlnx,zynqmp + + - description: Xilinx evaluation board zcu106 + items: + - enum: + - xlnx,zynqmp-zcu106-revA + - xlnx,zynqmp-zcu106-rev1.0 + - const: xlnx,zynqmp-zcu106 + - const: xlnx,zynqmp + + - description: Xilinx evaluation board zcu111 + items: + - enum: + - xlnx,zynqmp-zcu111-revA + - xlnx,zynqmp-zcu11-rev1.0 + - const: xlnx,zynqmp-zcu111 + - const: xlnx,zynqmp + ... -- cgit v1.2.3 From 738d57f23c2b3193aa187d7ecdaa1e83985af8e3 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:57:35 -0500 Subject: dt-bindings: arm: Convert ZTE board/soc bindings to json-schema Convert ZTE SoC bindings to DT schema format using json-schema. Cc: Jun Nie Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Acked-by: Shawn Guo Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/zte.txt | 14 -------------- Documentation/devicetree/bindings/arm/zte.yaml | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 14 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/zte.txt create mode 100644 Documentation/devicetree/bindings/arm/zte.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/zte.txt b/Documentation/devicetree/bindings/arm/zte.txt deleted file mode 100644 index 340612794a37..000000000000 --- a/Documentation/devicetree/bindings/arm/zte.txt +++ /dev/null @@ -1,14 +0,0 @@ -ZTE platforms device tree bindings - ---------------------------------------- -- ZX296702 board: - Required root node properties: - - compatible = "zte,zx296702-ad1", "zte,zx296702" - ---------------------------------------- -- ZX296718 SoC: - Required root node properties: - - compatible = "zte,zx296718" - -ZX296718 EVB board: - - "zte,zx296718-evb" diff --git a/Documentation/devicetree/bindings/arm/zte.yaml b/Documentation/devicetree/bindings/arm/zte.yaml new file mode 100644 index 000000000000..2d3fefdccdff --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zte.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/zte.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE platforms device tree bindings + +maintainers: + - Jun Nie + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - zte,zx296702-ad1 + - const: zte,zx296702 + - items: + - enum: + - zte,zx296718-evb + - const: zte,zx296718 + +... -- cgit v1.2.3 From f4d1577e9bc66b3699c7c43b98735e1dcc0a83d0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 May 2018 18:56:50 -0500 Subject: dt-bindings: arm: Convert Tegra board/soc bindings to json-schema Convert Tegra SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Jonathan Hunter Cc: devicetree@vger.kernel.org Cc: linux-tegra@vger.kernel.org Acked-by: Thierry Reding Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/tegra.txt | 65 --------------- Documentation/devicetree/bindings/arm/tegra.yaml | 101 +++++++++++++++++++++++ 2 files changed, 101 insertions(+), 65 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt deleted file mode 100644 index c59b15f64346..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ /dev/null @@ -1,65 +0,0 @@ -NVIDIA Tegra device tree bindings -------------------------------------------- - -SoCs -------------------------------------------- - -Each device tree must specify which Tegra SoC it uses, using one of the -following compatible values: - - nvidia,tegra20 - nvidia,tegra30 - nvidia,tegra114 - nvidia,tegra124 - nvidia,tegra132 - nvidia,tegra210 - nvidia,tegra186 - nvidia,tegra194 - -Boards -------------------------------------------- - -Each device tree must specify which one or more of the following -board-specific compatible values: - - ad,medcom-wide - ad,plutux - ad,tamonten - ad,tec - compal,paz00 - compulab,trimslice - nvidia,beaver - nvidia,cardhu - nvidia,cardhu-a02 - nvidia,cardhu-a04 - nvidia,dalmore - nvidia,harmony - nvidia,jetson-tk1 - nvidia,norrin - nvidia,p2371-0000 - nvidia,p2371-2180 - nvidia,p2571 - nvidia,p2771-0000 - nvidia,p2972-0000 - nvidia,roth - nvidia,seaboard - nvidia,tn7 - nvidia,ventana - toradex,apalis_t30 - toradex,apalis_t30-eval - toradex,apalis_t30-v1.1 - toradex,apalis_t30-v1.1-eval - toradex,apalis-tk1 - toradex,apalis-tk1-eval - toradex,apalis-tk1-v1.2 - toradex,apalis-tk1-v1.2-eval - toradex,colibri_t20 - toradex,colibri_t20-eval-v3 - toradex,colibri_t20-iris - toradex,colibri_t30 - toradex,colibri_t30-eval-v3 - -Trusted Foundations -------------------------------------------- -Tegra supports the Trusted Foundation secure monitor. See the -"tlm,trusted-foundations" binding's documentation for more details. diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml new file mode 100644 index 000000000000..fbcde8a7e067 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra device tree bindings + +maintainers: + - Thierry Reding + - Jonathan Hunter + +properties: + compatible: + oneOf: + - items: + - enum: + - compal,paz00 + - compulab,trimslice + - nvidia,harmony + - nvidia,seaboard + - nvidia,ventana + - const: nvidia,tegra20 + - items: + - enum: + - ad,medcom-wide + - ad,plutux + - ad,tec + - const: ad,tamonten + - const: nvidia,tegra20 + - items: + - enum: + - toradex,colibri_t20-eval-v3 + - toradex,colibri_t20-iris + - const: toradex,colibri_t20 + - const: nvidia,tegra20 + - items: + - enum: + - nvidia,beaver + - const: nvidia,tegra30 + - items: + - enum: + - nvidia,cardhu-a02 + - nvidia,cardhu-a04 + - const: nvidia,cardhu + - const: nvidia,tegra30 + - items: + - const: toradex,apalis_t30-eval + - const: toradex,apalis_t30 + - const: nvidia,tegra30 + - items: + - const: toradex,apalis_t30-eval-v1.1 + - const: toradex,apalis_t30-eval + - const: toradex,apalis_t30-v1.1 + - const: toradex,apalis_t30 + - const: nvidia,tegra30 + - items: + - enum: + - toradex,colibri_t30-eval-v3 + - const: toradex,colibri_t30 + - const: nvidia,tegra30 + - items: + - enum: + - nvidia,dalmore + - nvidia,roth + - nvidia,tn7 + - const: nvidia,tegra114 + - items: + - enum: + - nvidia,jetson-tk1 + - nvidia,venice2 + - const: nvidia,tegra124 + - items: + - const: toradex,apalis-tk1-eval + - const: toradex,apalis-tk1 + - const: nvidia,tegra124 + - items: + - const: toradex,apalis-tk1-v1.2-eval + - const: toradex,apalis-tk1-eval + - const: toradex,apalis-tk1-v1.2 + - const: toradex,apalis-tk1 + - const: nvidia,tegra124 + - items: + - enum: + - nvidia,norrin + - const: nvidia,tegra132 + - const: nvidia,tegra124 + - items: + - enum: + - nvidia,p2371-0000 + - nvidia,p2371-2180 + - nvidia,p2571 + - const: nvidia,tegra210 + - items: + - enum: + - nvidia,p2771-0000 + - const: nvidia,tegra186 + - items: + - enum: + - nvidia,p2972-0000 + - const: nvidia,tegra194 -- cgit v1.2.3 From cd1cc0bef46fc8d8f9ebe82d2064d4f4bd5ecf16 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 2 Dec 2018 12:40:08 +0100 Subject: dt-bindings: arm: mrvl: amend Browstone compatible string The Brownstone board is compatible with "mrvl,mmp2". The actual DTS already contains the string -- add it to the binding doc as well. Signed-off-by: Lubomir Rintel Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/mrvl/mrvl.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt index 117d741a2e4f..951687528efb 100644 --- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt +++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt @@ -11,4 +11,4 @@ Required root node properties: MMP2 Brownstone Board Required root node properties: - - compatible = "mrvl,mmp2-brownstone"; + - compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2"; -- cgit v1.2.3 From 2c9b0b00af23cdc70d28d82e077dc1d280bcb84a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 26 Apr 2018 16:08:29 -0500 Subject: dt-bindings: Convert trivial-devices.txt to json-schema Convert trivial-devices.txt to DT schema format using json-schema. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/trivial-devices.txt | 190 ---------- .../devicetree/bindings/trivial-devices.yaml | 392 +++++++++++++++++++++ 2 files changed, 392 insertions(+), 190 deletions(-) delete mode 100644 Documentation/devicetree/bindings/trivial-devices.txt create mode 100644 Documentation/devicetree/bindings/trivial-devices.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt deleted file mode 100644 index 6ab001fa1ed4..000000000000 --- a/Documentation/devicetree/bindings/trivial-devices.txt +++ /dev/null @@ -1,190 +0,0 @@ -This is a list of trivial i2c devices that have simple device tree -bindings, consisting only of a compatible field, an address and -possibly an interrupt line. - -If a device needs more specific bindings, such as properties to -describe some aspect of it, there needs to be a specific binding -document for it just like any other devices. - - -Compatible Vendor / Chip -========== ============= -abracon,abb5zes3 AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface -ad,ad7414 SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin -ad,adm9240 ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems -adi,adt7461 +/-1C TDM Extended Temp Range I.C -adt7461 +/-1C TDM Extended Temp Range I.C -adi,adt7473 +/-1C TDM Extended Temp Range I.C -adi,adt7475 +/-1C TDM Extended Temp Range I.C -adi,adt7476 +/-1C TDM Extended Temp Range I.C -adi,adt7490 +/-1C TDM Extended Temp Range I.C -adi,adxl345 Three-Axis Digital Accelerometer -adi,adxl346 Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too) -ams,iaq-core AMS iAQ-Core VOC Sensor -at,24c08 i2c serial eeprom (24cxx) -atmel,at97sc3204t i2c trusted platform module (TPM) -capella,cm32181 CM32181: Ambient Light Sensor -capella,cm3232 CM3232: Ambient Light Sensor -dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output -dallas,ds1631 High-Precision Digital Thermometer -dallas,ds1672 Dallas DS1672 Real-time Clock -dallas,ds1682 Total-Elapsed-Time Recorder with Alarm -dallas,ds1775 Tiny Digital Thermometer and Thermostat -dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM -dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O -dallas,ds75 Digital Thermometer and Thermostat -devantech,srf02 Devantech SRF02 ultrasonic ranger in I2C mode -devantech,srf08 Devantech SRF08 ultrasonic ranger -devantech,srf10 Devantech SRF10 ultrasonic ranger -dlg,da9053 DA9053: flexible system level PMIC with multicore support -dlg,da9063 DA9063: system PMIC for quad-core application processors -domintech,dmard09 DMARD09: 3-axis Accelerometer -domintech,dmard10 DMARD10: 3-axis Accelerometer -epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE -epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE -emmicro,em3027 EM Microelectronic EM3027 Real-time Clock -fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer -fsl,mma7660 MMA7660FC: 3-Axis Orientation/Motion Detection Sensor -fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer -fsl,mpl3115 MPL3115: Absolute Digital Pressure Sensor -fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller -fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec -gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface -infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) -infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) -infineon,tlv493d-a1b6 Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor -isil,isl1208 Intersil ISL1208 Low Power RTC with Battery Backed SRAM -isil,isl1218 Intersil ISL1218 Low Power RTC with Battery Backed SRAM -isil,isl12022 Intersil ISL12022 Real-time Clock -isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor -isil,isl29030 Intersil ISL29030 Ambient Light and Proximity Sensor -maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator -maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs -maxim,max6621 PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion -maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface -mcube,mc3230 mCube 3-axis 8-bit digital accelerometer -memsic,mxc6225 MEMSIC 2-axis 8-bit digital accelerometer -microchip,mcp4017-502 Microchip 7-bit Single I2C Digital POT (5k) -microchip,mcp4017-103 Microchip 7-bit Single I2C Digital POT (10k) -microchip,mcp4017-503 Microchip 7-bit Single I2C Digital POT (50k) -microchip,mcp4017-104 Microchip 7-bit Single I2C Digital POT (100k) -microchip,mcp4018-502 Microchip 7-bit Single I2C Digital POT (5k) -microchip,mcp4018-103 Microchip 7-bit Single I2C Digital POT (10k) -microchip,mcp4018-503 Microchip 7-bit Single I2C Digital POT (50k) -microchip,mcp4018-104 Microchip 7-bit Single I2C Digital POT (100k) -microchip,mcp4019-502 Microchip 7-bit Single I2C Digital POT (5k) -microchip,mcp4019-103 Microchip 7-bit Single I2C Digital POT (10k) -microchip,mcp4019-503 Microchip 7-bit Single I2C Digital POT (50k) -microchip,mcp4019-104 Microchip 7-bit Single I2C Digital POT (100k) -microchip,mcp4531-502 Microchip 7-bit Single I2C Digital Potentiometer (5k) -microchip,mcp4531-103 Microchip 7-bit Single I2C Digital Potentiometer (10k) -microchip,mcp4531-503 Microchip 7-bit Single I2C Digital Potentiometer (50k) -microchip,mcp4531-104 Microchip 7-bit Single I2C Digital Potentiometer (100k) -microchip,mcp4532-502 Microchip 7-bit Single I2C Digital Potentiometer (5k) -microchip,mcp4532-103 Microchip 7-bit Single I2C Digital Potentiometer (10k) -microchip,mcp4532-503 Microchip 7-bit Single I2C Digital Potentiometer (50k) -microchip,mcp4532-104 Microchip 7-bit Single I2C Digital Potentiometer (100k) -microchip,mcp4541-502 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4541-103 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4541-503 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4541-104 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4542-502 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4542-103 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4542-503 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4542-104 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4551-502 Microchip 8-bit Single I2C Digital Potentiometer (5k) -microchip,mcp4551-103 Microchip 8-bit Single I2C Digital Potentiometer (10k) -microchip,mcp4551-503 Microchip 8-bit Single I2C Digital Potentiometer (50k) -microchip,mcp4551-104 Microchip 8-bit Single I2C Digital Potentiometer (100k) -microchip,mcp4552-502 Microchip 8-bit Single I2C Digital Potentiometer (5k) -microchip,mcp4552-103 Microchip 8-bit Single I2C Digital Potentiometer (10k) -microchip,mcp4552-503 Microchip 8-bit Single I2C Digital Potentiometer (50k) -microchip,mcp4552-104 Microchip 8-bit Single I2C Digital Potentiometer (100k) -microchip,mcp4561-502 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4561-103 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4561-503 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4561-104 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4562-502 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4562-103 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4562-503 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4562-104 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4631-502 Microchip 7-bit Dual I2C Digital Potentiometer (5k) -microchip,mcp4631-103 Microchip 7-bit Dual I2C Digital Potentiometer (10k) -microchip,mcp4631-503 Microchip 7-bit Dual I2C Digital Potentiometer (50k) -microchip,mcp4631-104 Microchip 7-bit Dual I2C Digital Potentiometer (100k) -microchip,mcp4632-502 Microchip 7-bit Dual I2C Digital Potentiometer (5k) -microchip,mcp4632-103 Microchip 7-bit Dual I2C Digital Potentiometer (10k) -microchip,mcp4632-503 Microchip 7-bit Dual I2C Digital Potentiometer (50k) -microchip,mcp4632-104 Microchip 7-bit Dual I2C Digital Potentiometer (100k) -microchip,mcp4641-502 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4641-103 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4641-503 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4641-104 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4642-502 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4642-103 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4642-503 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4642-104 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4651-502 Microchip 8-bit Dual I2C Digital Potentiometer (5k) -microchip,mcp4651-103 Microchip 8-bit Dual I2C Digital Potentiometer (10k) -microchip,mcp4651-503 Microchip 8-bit Dual I2C Digital Potentiometer (50k) -microchip,mcp4651-104 Microchip 8-bit Dual I2C Digital Potentiometer (100k) -microchip,mcp4652-502 Microchip 8-bit Dual I2C Digital Potentiometer (5k) -microchip,mcp4652-103 Microchip 8-bit Dual I2C Digital Potentiometer (10k) -microchip,mcp4652-503 Microchip 8-bit Dual I2C Digital Potentiometer (50k) -microchip,mcp4652-104 Microchip 8-bit Dual I2C Digital Potentiometer (100k) -microchip,mcp4661-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4661-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4661-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4661-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4662-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4662-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4662-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4662-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) -microchip,tc654 PWM Fan Speed Controller With Fan Fault Detection -microchip,tc655 PWM Fan Speed Controller With Fan Fault Detection -microcrystal,rv3029 Real Time Clock Module with I2C-Bus -miramems,da226 MiraMEMS DA226 2-axis 14-bit digital accelerometer -miramems,da280 MiraMEMS DA280 3-axis 14-bit digital accelerometer -miramems,da311 MiraMEMS DA311 3-axis 12-bit digital accelerometer -national,lm63 Temperature sensor with integrated fan control -national,lm75 I2C TEMP SENSOR -national,lm80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor -national,lm85 Temperature sensor with integrated fan control -national,lm92 ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface -nuvoton,npct501 i2c trusted platform module (TPM) -nuvoton,npct601 i2c trusted platform module (TPM2) -nuvoton,w83773g Nuvoton Temperature Sensor -nxp,pca9556 Octal SMBus and I2C registered interface -nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset -nxp,pcf2127 Real-time clock -nxp,pcf2129 Real-time clock -nxp,pcf8523 Real-time Clock -nxp,pcf8563 Real-time clock/calendar -nxp,pcf85063 Tiny Real-Time Clock -oki,ml86v7667 OKI ML86V7667 video decoder -ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus -pericom,pt7c4338 Real-time Clock Module -plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch -pulsedlight,lidar-lite-v2 Pulsedlight LIDAR range-finding sensor -ricoh,r2025sd I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,r2221tl I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rs5c372b I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rv5c386 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rv5c387a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) -sgx,vz89x SGX Sensortech VZ89X Sensors -sii,s35390a 2-wire CMOS real-time clock -silabs,si7020 Relative Humidity and Temperature Sensors -skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply -st,24c256 i2c serial eeprom (24cxx) -taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface -ti,ads7828 8-Channels, 12-bit ADC -ti,ads7830 8-Channels, 8-bit ADC -ti,amc6821 Temperature Monitoring and Fan Control -ti,tsc2003 I2C Touch-Screen Controller -ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface -ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface -ti,tmp275 Digital Temperature Sensor -winbond,w83793 Winbond/Nuvoton H/W Monitor -winbond,wpct301 i2c trusted platform module (TPM) diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml new file mode 100644 index 000000000000..c5d31754a354 --- /dev/null +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -0,0 +1,392 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/trivial-devices.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trivial I2C and SPI devices that have simple device tree bindings + +maintainers: + - Rob Herring + +description: | + This is a list of trivial I2C and SPI devices that have simple device tree + bindings, consisting only of a compatible field, an address and possibly an + interrupt line. + + If a device needs more specific bindings, such as properties to + describe some aspect of it, there needs to be a specific binding + document for it just like any other devices. + +properties: + reg: + maxItems: 1 + interrupts: + maxItems: 1 + compatible: + items: + - enum: + # AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface + - abracon,abb5zes3 + # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin + - ad,ad7414 + # ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems + - ad,adm9240 + # +/-1C TDM Extended Temp Range I.C + - adi,adt7461 + # +/-1C TDM Extended Temp Range I.C + - adt7461 + # +/-1C TDM Extended Temp Range I.C + - adi,adt7473 + # +/-1C TDM Extended Temp Range I.C + - adi,adt7475 + # +/-1C TDM Extended Temp Range I.C + - adi,adt7476 + # +/-1C TDM Extended Temp Range I.C + - adi,adt7490 + # Three-Axis Digital Accelerometer + - adi,adxl345 + # Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too) + - adi,adxl346 + # AMS iAQ-Core VOC Sensor + - ams,iaq-core + # i2c serial eeprom (24cxx) + - at,24c08 + # i2c trusted platform module (TPM) + - atmel,at97sc3204t + # CM32181: Ambient Light Sensor + - capella,cm32181 + # CM3232: Ambient Light Sensor + - capella,cm3232 + # I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output + - dallas,ds1374 + # High-Precision Digital Thermometer + - dallas,ds1631 + # Dallas DS1672 Real-time Clock + - dallas,ds1672 + # Total-Elapsed-Time Recorder with Alarm + - dallas,ds1682 + # Tiny Digital Thermometer and Thermostat + - dallas,ds1775 + # Extremely Accurate I²C RTC with Integrated Crystal and SRAM + - dallas,ds3232 + # CPU Supervisor with Nonvolatile Memory and Programmable I/O + - dallas,ds4510 + # Digital Thermometer and Thermostat + - dallas,ds75 + # Devantech SRF02 ultrasonic ranger in I2C mode + - devantech,srf02 + # Devantech SRF08 ultrasonic ranger + - devantech,srf08 + # Devantech SRF10 ultrasonic ranger + - devantech,srf10 + # DA9053: flexible system level PMIC with multicore support + - dlg,da9053 + # DA9063: system PMIC for quad-core application processors + - dlg,da9063 + # DMARD09: 3-axis Accelerometer + - domintech,dmard09 + # DMARD10: 3-axis Accelerometer + - domintech,dmard10 + # I2C-BUS INTERFACE REAL TIME CLOCK MODULE + - epson,rx8010 + # I2C-BUS INTERFACE REAL TIME CLOCK MODULE + - epson,rx8581 + # EM Microelectronic EM3027 Real-time Clock + - emmicro,em3027 + # MAG3110: Xtrinsic High Accuracy, 3D Magnetometer + - fsl,mag3110 + # MMA7660FC: 3-Axis Orientation/Motion Detection Sensor + - fsl,mma7660 + # MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer + - fsl,mma8450 + # MPL3115: Absolute Digital Pressure Sensor + - fsl,mpl3115 + # MPR121: Proximity Capacitive Touch Sensor Controller + - fsl,mpr121 + # SGTL5000: Ultra Low-Power Audio Codec + - fsl,sgtl5000 + # G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface + - gmt,g751 + # Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) + - infineon,slb9635tt + # Infineon SLB9645 I2C TPM (new protocol, max 400khz) + - infineon,slb9645tt + # Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor + - infineon,tlv493d-a1b6 + # Intersil ISL1208 Low Power RTC with Battery Backed SRAM + - isil,isl1208 + # Intersil ISL1218 Low Power RTC with Battery Backed SRAM + - isil,isl1218 + # Intersil ISL12022 Real-time Clock + - isil,isl12022 + # Intersil ISL29028 Ambient Light and Proximity Sensor + - isil,isl29028 + # Intersil ISL29030 Ambient Light and Proximity Sensor + - isil,isl29030 + # 5 Bit Programmable, Pulse-Width Modulator + - maxim,ds1050 + # Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs + - maxim,max1237 + # PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion + - maxim,max6621 + # 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface + - maxim,max6625 + # mCube 3-axis 8-bit digital accelerometer + - mcube,mc3230 + # MEMSIC 2-axis 8-bit digital accelerometer + - memsic,mxc6225 + # Microchip 7-bit Single I2C Digital POT (5k) + - microchip,mcp4017-502 + # Microchip 7-bit Single I2C Digital POT (10k) + - microchip,mcp4017-103 + # Microchip 7-bit Single I2C Digital POT (50k) + - microchip,mcp4017-503 + # Microchip 7-bit Single I2C Digital POT (100k) + - microchip,mcp4017-104 + # Microchip 7-bit Single I2C Digital POT (5k) + - microchip,mcp4018-502 + # Microchip 7-bit Single I2C Digital POT (10k) + - microchip,mcp4018-103 + # Microchip 7-bit Single I2C Digital POT (50k) + - microchip,mcp4018-503 + # Microchip 7-bit Single I2C Digital POT (100k) + - microchip,mcp4018-104 + # Microchip 7-bit Single I2C Digital POT (5k) + - microchip,mcp4019-502 + # Microchip 7-bit Single I2C Digital POT (10k) + - microchip,mcp4019-103 + # Microchip 7-bit Single I2C Digital POT (50k) + - microchip,mcp4019-503 + # Microchip 7-bit Single I2C Digital POT (100k) + - microchip,mcp4019-104 + # Microchip 7-bit Single I2C Digital Potentiometer (5k) + - microchip,mcp4531-502 + # Microchip 7-bit Single I2C Digital Potentiometer (10k) + - microchip,mcp4531-103 + # Microchip 7-bit Single I2C Digital Potentiometer (50k) + - microchip,mcp4531-503 + # Microchip 7-bit Single I2C Digital Potentiometer (100k) + - microchip,mcp4531-104 + # Microchip 7-bit Single I2C Digital Potentiometer (5k) + - microchip,mcp4532-502 + # Microchip 7-bit Single I2C Digital Potentiometer (10k) + - microchip,mcp4532-103 + # Microchip 7-bit Single I2C Digital Potentiometer (50k) + - microchip,mcp4532-503 + # Microchip 7-bit Single I2C Digital Potentiometer (100k) + - microchip,mcp4532-104 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4541-502 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4541-103 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4541-503 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4541-104 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4542-502 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4542-103 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4542-503 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4542-104 + # Microchip 8-bit Single I2C Digital Potentiometer (5k) + - microchip,mcp4551-502 + # Microchip 8-bit Single I2C Digital Potentiometer (10k) + - microchip,mcp4551-103 + # Microchip 8-bit Single I2C Digital Potentiometer (50k) + - microchip,mcp4551-503 + # Microchip 8-bit Single I2C Digital Potentiometer (100k) + - microchip,mcp4551-104 + # Microchip 8-bit Single I2C Digital Potentiometer (5k) + - microchip,mcp4552-502 + # Microchip 8-bit Single I2C Digital Potentiometer (10k) + - microchip,mcp4552-103 + # Microchip 8-bit Single I2C Digital Potentiometer (50k) + - microchip,mcp4552-503 + # Microchip 8-bit Single I2C Digital Potentiometer (100k) + - microchip,mcp4552-104 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4561-502 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4561-103 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4561-503 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4561-104 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4562-502 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4562-103 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4562-503 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4562-104 + # Microchip 7-bit Dual I2C Digital Potentiometer (5k) + - microchip,mcp4631-502 + # Microchip 7-bit Dual I2C Digital Potentiometer (10k) + - microchip,mcp4631-103 + # Microchip 7-bit Dual I2C Digital Potentiometer (50k) + - microchip,mcp4631-503 + # Microchip 7-bit Dual I2C Digital Potentiometer (100k) + - microchip,mcp4631-104 + # Microchip 7-bit Dual I2C Digital Potentiometer (5k) + - microchip,mcp4632-502 + # Microchip 7-bit Dual I2C Digital Potentiometer (10k) + - microchip,mcp4632-103 + # Microchip 7-bit Dual I2C Digital Potentiometer (50k) + - microchip,mcp4632-503 + # Microchip 7-bit Dual I2C Digital Potentiometer (100k) + - microchip,mcp4632-104 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4641-502 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4641-103 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4641-503 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4641-104 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4642-502 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4642-103 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4642-503 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4642-104 + # Microchip 8-bit Dual I2C Digital Potentiometer (5k) + - microchip,mcp4651-502 + # Microchip 8-bit Dual I2C Digital Potentiometer (10k) + - microchip,mcp4651-103 + # Microchip 8-bit Dual I2C Digital Potentiometer (50k) + - microchip,mcp4651-503 + # Microchip 8-bit Dual I2C Digital Potentiometer (100k) + - microchip,mcp4651-104 + # Microchip 8-bit Dual I2C Digital Potentiometer (5k) + - microchip,mcp4652-502 + # Microchip 8-bit Dual I2C Digital Potentiometer (10k) + - microchip,mcp4652-103 + # Microchip 8-bit Dual I2C Digital Potentiometer (50k) + - microchip,mcp4652-503 + # Microchip 8-bit Dual I2C Digital Potentiometer (100k) + - microchip,mcp4652-104 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4661-502 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4661-103 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4661-503 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4661-104 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4662-502 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4662-103 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4662-503 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4662-104 + # PWM Fan Speed Controller With Fan Fault Detection + - microchip,tc654 + # PWM Fan Speed Controller With Fan Fault Detection + - microchip,tc655 + # Real Time Clock Module with I2C-Bus + - microcrystal,rv3029 + # MiraMEMS DA226 2-axis 14-bit digital accelerometer + - miramems,da226 + # MiraMEMS DA280 3-axis 14-bit digital accelerometer + - miramems,da280 + # MiraMEMS DA311 3-axis 12-bit digital accelerometer + - miramems,da311 + # Temperature sensor with integrated fan control + - national,lm63 + # I2C TEMP SENSOR + - national,lm75 + # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor + - national,lm80 + # Temperature sensor with integrated fan control + - national,lm85 + # ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface + - national,lm92 + # i2c trusted platform module (TPM) + - nuvoton,npct501 + # i2c trusted platform module (TPM2) + - nuvoton,npct601 + # Nuvoton Temperature Sensor + - nuvoton,w83773g + # Octal SMBus and I2C registered interface + - nxp,pca9556 + # 8-bit I2C-bus and SMBus I/O port with reset + - nxp,pca9557 + # Real-time clock + - nxp,pcf2127 + # Real-time clock + - nxp,pcf2129 + # Real-time Clock + - nxp,pcf8523 + # Real-time clock/calendar + - nxp,pcf8563 + # Tiny Real-Time Clock + - nxp,pcf85063 + # OKI ML86V7667 video decoder + - oki,ml86v7667 + # OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus + - ovti,ov5642 + # Real-time Clock Module + - pericom,pt7c4338 + # 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch + - plx,pex8648 + # Pulsedlight LIDAR range-finding sensor + - pulsedlight,lidar-lite-v2 + # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC + - ricoh,r2025sd + # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC + - ricoh,r2221tl + # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC + - ricoh,rs5c372a + # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC + - ricoh,rs5c372b + # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC + - ricoh,rv5c386 + # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC + - ricoh,rv5c387a + # S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) + - samsung,24ad0xd1 + # SGX Sensortech VZ89X Sensors + - sgx,vz89x + # 2-wire CMOS real-time clock + - sii,s35390a + # Relative Humidity and Temperature Sensors + - silabs,si7020 + # Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply + - skyworks,sky81452 + # i2c serial eeprom (24cxx) + - st,24c256 + # Ambient Light Sensor with SMBUS/Two Wire Serial Interface + - taos,tsl2550 + # 8-Channels, 12-bit ADC + - ti,ads7828 + # 8-Channels, 8-bit ADC + - ti,ads7830 + # Temperature Monitoring and Fan Control + - ti,amc6821 + # I2C Touch-Screen Controller + - ti,tsc2003 + # Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface + - ti,tmp102 + # Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface + - ti,tmp103 + # Digital Temperature Sensor + - ti,tmp275 + # Winbond/Nuvoton H/W Monitor + - winbond,w83793 + # i2c trusted platform module (TPM) + - winbond,wpct301 + +required: + - compatible + - reg + +... -- cgit v1.2.3 From 7c813152cf9ba1901a4d621ebba1edbac910095e Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 10 Dec 2018 13:56:30 +0000 Subject: dt-bindings/gic-v3: Add msm8996 compatible string Access to GICR_WAKER is restricted on msm8996 SoC in Hypervisor. There are many devices out there with this restriction in place and there has been no update to this firmware since last few years, making those devices totally unusable for upstream development. IIDR register value conflicts with other SoCs, using compatible seems to be the only way to apply quirks required for msm8996 based SoCs. Without this quirk many qcom SoCs (atleast 3 that I know) are unable to boot mainline. Reviewed-by: Rob Herring Signed-off-by: Srinivas Kandagatla Signed-off-by: Marc Zyngier --- Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 3ea78c4ef887..b83bb8249074 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -7,7 +7,9 @@ Interrupts (LPI). Main node required properties: -- compatible : should at least contain "arm,gic-v3". +- compatible : should at least contain "arm,gic-v3" or either + "qcom,msm8996-gic-v3", "arm,gic-v3" for msm8996 SoCs + to address SoC specific bugs/quirks - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. Must be a single cell with a value of at least 3. -- cgit v1.2.3 From 0f5ab411f5878274b41839bad8bdcc7af1fcaa27 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Thu, 13 Dec 2018 01:08:06 +0000 Subject: dt-bindings: clock: add imx8qxp lpcg clock binding The Low-Power Clock Gate (LPCG) modules contain a local programming model to control the clock gates for the peripherals. An LPCG module is used to locally gate the clocks for the associated peripheral. Note: This level of clock gating is provided after the clocks are generated by the SCU resources and clock controls. Thus even if the clock is enabled by these control bits, it might still not be running based on the base resource. Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/imx8qxp-lpcg.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt new file mode 100644 index 000000000000..965cfa42e025 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt @@ -0,0 +1,51 @@ +* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings + +The Low-Power Clock Gate (LPCG) modules contain a local programming +model to control the clock gates for the peripherals. An LPCG module +is used to locally gate the clocks for the associated peripheral. + +Note: +This level of clock gating is provided after the clocks are generated +by the SCU resources and clock controls. Thus even if the clock is +enabled by these control bits, it might still not be running based +on the base resource. + +Required properties: +- compatible: Should be one of: + "fsl,imx8qxp-lpcg-adma", + "fsl,imx8qxp-lpcg-conn", + "fsl,imx8qxp-lpcg-dc", + "fsl,imx8qxp-lpcg-dsp", + "fsl,imx8qxp-lpcg-gpu", + "fsl,imx8qxp-lpcg-hsio", + "fsl,imx8qxp-lpcg-img", + "fsl,imx8qxp-lpcg-lsio", + "fsl,imx8qxp-lpcg-vpu" +- reg: Address and length of the register set +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. +See the full list of clock IDs from: +include/dt-bindings/clock/imx8qxp-clock.h + +Examples: + +#include + +conn_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg-conn"; + reg = <0x5b200000 0xb0000>; + #clock-cells = <1>; +}; + +usdhc1: mmc@5b010000 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x5b010000 0x10000>; + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; + clock-names = "ipg", "per", "ahb"; +}; -- cgit v1.2.3 From 91a531e48b20677c1f820f3bbd4237abd8144919 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 14 Dec 2018 11:32:06 +0900 Subject: ASoC: audio-graph-card: merge audio-graph-scu-card on Doc audio-graph-card and audio-graph-scu-card are very similar driver, but the former is supporting normal sound card, the latter is supporting DPCM sound card. We couldn't use normal sound and DPCM sound in same sound card by audio-graph-card. This patch merges both feature into it on Documentation. Now we can use both feature on same driver. Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/audio-graph-card.txt | 205 +++++++++++++++++++++ 1 file changed, 205 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/audio-graph-card.txt b/Documentation/devicetree/bindings/sound/audio-graph-card.txt index 7e63e53a901c..269682619a70 100644 --- a/Documentation/devicetree/bindings/sound/audio-graph-card.txt +++ b/Documentation/devicetree/bindings/sound/audio-graph-card.txt @@ -32,7 +32,9 @@ Required properties: Optional properties: - pa-gpios: GPIO used to control external amplifier. +----------------------- Example: Single DAI case +----------------------- sound_card { compatible = "audio-graph-card"; @@ -61,7 +63,9 @@ Example: Single DAI case }; }; +----------------------- Example: Multi DAI case +----------------------- sound-card { compatible = "audio-graph-card"; @@ -130,3 +134,204 @@ Example: Multi DAI case }; }; + +----------------------- +Example: Sampling Rate Conversion +----------------------- + + sound_card { + compatible = "audio-graph-card"; + + label = "sound-card"; + prefix = "codec"; + routing = "codec Playback", "DAI0 Playback", + "DAI0 Capture", "codec Capture"; + convert-rate = <48000>; + + dais = <&cpu_port>; + }; + + audio-codec { + ... + port { + codec_endpoint: endpoint { + remote-endpoint = <&cpu_endpoint>; + }; + }; + }; + + dai-controller { + ... + cpu_port: port { + cpu_endpoint: endpoint { + remote-endpoint = <&codec_endpoint>; + + dai-format = "left_j"; + ... + }; + }; + }; + +----------------------- +Example: 2 CPU 1 Codec (Mixing) +----------------------- + + sound_card { + compatible = "audio-graph-card"; + + label = "sound-card"; + routing = "codec Playback", "DAI0 Playback", + "codec Playback", "DAI1 Playback", + "DAI0 Capture", "codec Capture"; + + dais = <&cpu_port>; + }; + + audio-codec { + ... + + audio-graph-card,prefix = "codec"; + audio-graph-card,convert-rate = <48000>; + port { + reg = <0>; + codec_endpoint0: endpoint@0 { + remote-endpoint = <&cpu_endpoint0>; + }; + codec_endpoint1: endpoint@1 { + remote-endpoint = <&cpu_endpoint1>; + }; + }; + }; + + dai-controller { + ... + cpu_port: port { + cpu_endpoint0: endpoint@0 { + remote-endpoint = <&codec_endpoint0>; + + dai-format = "left_j"; + ... + }; + cpu_endpoint1: endpoint@1 { + remote-endpoint = <&codec_endpoint1>; + + dai-format = "left_j"; + ... + }; + }; + }; + +----------------------- +Example: Multi DAI with DPCM +----------------------- + + CPU0 ------ ak4613 + CPU1 ------ HDMI + CPU2 ------ PCM3168A-p /* DPCM 1ch/2ch */ + CPU3 --/ /* DPCM 3ch/4ch */ + CPU4 --/ /* DPCM 5ch/6ch */ + CPU5 --/ /* DPCM 7ch/8ch */ + CPU6 ------ PCM3168A-c + + sound_card: sound { + compatible = "audio-graph-card"; + + label = "sound-card"; + + routing = "pcm3168a Playback", "DAI2 Playback", + "pcm3168a Playback", "DAI3 Playback", + "pcm3168a Playback", "DAI4 Playback", + "pcm3168a Playback", "DAI5 Playback"; + + dais = <&snd_port0 /* ak4613 */ + &snd_port1 /* HDMI0 */ + &snd_port2 /* pcm3168a playback */ + &snd_port3 /* pcm3168a capture */ + >; + }; + + ak4613: codec@10 { + ... + port { + ak4613_endpoint: endpoint { + remote-endpoint = <&rsnd_endpoint0>; + }; + }; + }; + + pcm3168a: audio-codec@44 { + ... + audio-graph-card,prefix = "pcm3168a"; + audio-graph-card,convert-channels = <8>; /* TDM Split */ + ports { + port@0 { + reg = <0>; + pcm3168a_endpoint_p1: endpoint@1 { + remote-endpoint = <&rsnd_endpoint2>; + ... + }; + pcm3168a_endpoint_p2: endpoint@2 { + remote-endpoint = <&rsnd_endpoint3>; + ... + }; + pcm3168a_endpoint_p3: endpoint@3 { + remote-endpoint = <&rsnd_endpoint4>; + ... + }; + pcm3168a_endpoint_p4: endpoint@4 { + remote-endpoint = <&rsnd_endpoint5>; + ... + }; + }; + port@1 { + reg = <1>; + pcm3168a_endpoint_c: endpoint { + remote-endpoint = <&rsnd_endpoint6>; + ... + }; + }; + }; + }; + + &sound { + ports { + snd_port0: port@0 { + rsnd_endpoint0: endpoint { + remote-endpoint = <&ak4613_endpoint>; + ... + }; + }; + snd_port1: port@1 { + rsnd_endpoint1: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + ... + }; + }; + snd_port2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + rsnd_endpoint2: endpoint@2 { + remote-endpoint = <&pcm3168a_endpoint_p1>; + ... + }; + rsnd_endpoint3: endpoint@3 { + remote-endpoint = <&pcm3168a_endpoint_p2>; + ... + }; + rsnd_endpoint4: endpoint@4 { + remote-endpoint = <&pcm3168a_endpoint_p3>; + ... + }; + rsnd_endpoint5: endpoint@5 { + remote-endpoint = <&pcm3168a_endpoint_p4>; + ... + }; + }; + snd_port3: port@6 { + rsnd_endpoint6: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c>; + ... + }; + }; + }; + }; -- cgit v1.2.3 From c4e8ebb9f2624da8302b6683ecb5ead7108ccb79 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 14 Dec 2018 11:35:05 +0900 Subject: ASoC: simple-card: merge simple-scu-card on Doc simple-card and simple-scu-card are very similar driver, but the former is supporting normal sound card, the latter is supporting DPCM sound card. We couldn't use normal sound and DPCM sound in same time by one sound card. This patch merges both sound card into simple-card. Now we can use both feature on same driver. simple-card is now supporting .compatible = "simple-scu-audio-card". Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/simple-card.txt | 137 +++++++++++++++++++++ 1 file changed, 137 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/simple-card.txt b/Documentation/devicetree/bindings/sound/simple-card.txt index a4c72d09cd45..4629c8f8a6b6 100644 --- a/Documentation/devicetree/bindings/sound/simple-card.txt +++ b/Documentation/devicetree/bindings/sound/simple-card.txt @@ -95,7 +95,9 @@ Optional CPU/CODEC subnodes properties: initialization. It is useful for some aCPUs with fixed clocks. +------------------------------------------- Example 1 - single DAI link: +------------------------------------------- sound { compatible = "simple-audio-card"; @@ -138,7 +140,9 @@ sh_fsi2: sh_fsi2@ec230000 { interrupts = <0 146 0x4>; }; +------------------------------------------- Example 2 - many DAI links: +------------------------------------------- sound { compatible = "simple-audio-card"; @@ -176,8 +180,10 @@ sound { }; }; +------------------------------------------- Example 3 - route audio from IMX6 SSI2 through TLV320DAC3100 codec through TPA6130A2 amplifier to headphones: +------------------------------------------- &i2c0 { codec: tlv320dac3100@18 { @@ -210,3 +216,134 @@ sound { clocks = ... }; }; + +------------------------------------------- +Example 4. Sampling Rate Conversion +------------------------------------------- + +sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "rsnd-ak4643"; + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + simple-audio-card,convert-rate = <48000>; + + simple-audio-card,prefix = "ak4642"; + simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback", + "DAI0 Capture", "ak4642 Capture"; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + system-clock-frequency = <11289600>; + }; +}; + +------------------------------------------- +Example 5. 2 CPU 1 Codec (Mixing) +------------------------------------------- +sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "rsnd-ak4643"; + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&dpcmcpu>; + simple-audio-card,frame-master = <&dpcmcpu>; + + simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback", + "ak4642 Playback", "DAI1 Playback"; + + dpcmcpu: cpu@0 { + sound-dai = <&rcar_sound 0>; + }; + + cpu@1 { + sound-dai = <&rcar_sound 1>; + }; + + codec { + prefix = "ak4642"; + sound-dai = <&ak4643>; + clocks = <&audio_clock>; + }; +}; + +------------------------------------------- +Example 6 - many DAI links with DPCM: +------------------------------------------- + +CPU0 ------ ak4613 +CPU1 ------ PCM3168A-p /* DPCM 1ch/2ch */ +CPU2 --/ /* DPCM 3ch/4ch */ +CPU3 --/ /* DPCM 5ch/6ch */ +CPU4 --/ /* DPCM 7ch/8ch */ +CPU5 ------ PCM3168A-c + +sound { + compatible = "simple-audio-card"; + + simple-audio-card,routing = + "pcm3168a Playback", "DAI1 Playback", + "pcm3168a Playback", "DAI2 Playback", + "pcm3168a Playback", "DAI3 Playback", + "pcm3168a Playback", "DAI4 Playback"; + + simple-audio-card,dai-link@0 { + format = "left_j"; + bitclock-master = <&sndcpu0>; + frame-master = <&sndcpu0>; + + sndcpu0: cpu { + sound-dai = <&rcar_sound 0>; + }; + codec { + sound-dai = <&ak4613>; + }; + }; + simple-audio-card,dai-link@1 { + format = "i2s"; + bitclock-master = <&sndcpu1>; + frame-master = <&sndcpu1>; + + convert-channels = <8>; /* TDM Split */ + + sndcpu1: cpu@0 { + sound-dai = <&rcar_sound 1>; + }; + cpu@1 { + sound-dai = <&rcar_sound 2>; + }; + cpu@2 { + sound-dai = <&rcar_sound 3>; + }; + cpu@3 { + sound-dai = <&rcar_sound 4>; + }; + codec { + mclk-fs = <512>; + prefix = "pcm3168a"; + dai-tdm-slot-num = <8>; + sound-dai = <&pcm3168a 0>; + }; + }; + simple-audio-card,dai-link@2 { + format = "i2s"; + bitclock-master = <&sndcpu2>; + frame-master = <&sndcpu2>; + + sndcpu2: cpu { + sound-dai = <&rcar_sound 5>; + }; + codec { + mclk-fs = <512>; + prefix = "pcm3168a"; + sound-dai = <&pcm3168a 1>; + }; + }; +}; -- cgit v1.2.3 From ae38d267417291db40de7439f2b0b690ab615f0e Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:20:06 +0000 Subject: ASoC: rsnd: Add r8a774c0 support Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro Acked-by: Kuninori Morimoto Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index 4d19d2bd6286..648d43e1b1e9 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -267,6 +267,7 @@ Required properties: - "renesas,rcar_sound-r8a7744" (RZ/G1N) - "renesas,rcar_sound-r8a7745" (RZ/G1E) - "renesas,rcar_sound-r8a774a1" (RZ/G2M) + - "renesas,rcar_sound-r8a774c0" (RZ/G2E) - "renesas,rcar_sound-r8a7778" (R-Car M1A) - "renesas,rcar_sound-r8a7779" (R-Car H1) - "renesas,rcar_sound-r8a7790" (R-Car H2) -- cgit v1.2.3 From 079e7f8709bb41cd0dc13efaffb24a0f17841955 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:19:57 +0000 Subject: spi: sh-msiof: Add r8a774c0 support Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index 4b836ad17b19..37cf69586d10 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt @@ -5,6 +5,7 @@ Required properties: "renesas,msiof-r8a7744" (RZ/G1N) "renesas,msiof-r8a7745" (RZ/G1E) "renesas,msiof-r8a774a1" (RZ/G2M) + "renesas,msiof-r8a774c0" (RZ/G2E) "renesas,msiof-r8a7790" (R-Car H2) "renesas,msiof-r8a7791" (R-Car M2-W) "renesas,msiof-r8a7792" (R-Car V2H) -- cgit v1.2.3 From ee23cf37fd586769febab95e2fbbbb50da5f9f2d Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 15 Nov 2018 18:13:22 +0000 Subject: ASoC: q6asm-dai: dt-bindings: Add support to compress dais This patch adds board specific bindings required for dais, In particular for compressed dais and dai direction. Board specific setup involves setting up some of dais as compressed dais and also specify direction of any dai. Some of the dais might only support capture/playback depending on the board level wiring. These two new dt properties will allow such flexibilty at board level dts. Signed-off-by: Srinivas Kandagatla Reviewed-by: Vinod Koul Reviewed-by: Rob Herring Acked-by: Vinod Koul Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/qcom,q6asm.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/qcom,q6asm.txt b/Documentation/devicetree/bindings/sound/qcom,q6asm.txt index f9c7bd8c1bc0..9f5378c51686 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6asm.txt +++ b/Documentation/devicetree/bindings/sound/qcom,q6asm.txt @@ -27,6 +27,28 @@ used by the apr service device. Value type: Definition: Must be 1 +== ASM DAI is subnode of "dais" and represent a dai, it includes board specific +configuration of each dai. Must contain the following properties. + +- reg + Usage: required + Value type: + Definition: Must be dai id + +- direction: + Usage: Required for Compress offload dais + Value type: + Definition: Specifies the direction of the dai stream + 0 for both tx and rx + 1 for only tx (Capture/Encode) + 2 for only rx (Playback/Decode) + +- is-compress-dai: + Usage: Required for Compress offload dais + Value type: + Definition: present for Compress offload dais + + = EXAMPLE q6asm@7 { @@ -35,5 +57,10 @@ q6asm@7 { q6asmdai: dais { compatible = "qcom,q6asm-dais"; #sound-dai-cells = <1>; + mm@0 { + reg = <0>; + direction = <2>; + is-compress-dai; + }; }; }; -- cgit v1.2.3 From 1811caa0cf91320baff40c82cbb157c772cfd365 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:18:34 +0000 Subject: dt-bindings: net: ravb: Add support for r8a774c0 SoC Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Sergei Shtylyov Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt index 3530256a879c..7ad36213093e 100644 --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt @@ -18,6 +18,7 @@ Required properties: R-Car Gen2 and RZ/G1 devices. - "renesas,etheravb-r8a774a1" for the R8A774A1 SoC. + - "renesas,etheravb-r8a774c0" for the R8A774C0 SoC. - "renesas,etheravb-r8a7795" for the R8A7795 SoC. - "renesas,etheravb-r8a7796" for the R8A7796 SoC. - "renesas,etheravb-r8a77965" for the R8A77965 SoC. -- cgit v1.2.3 From 05cf4fe738242183f1237f1b3a28b4479348c0a1 Mon Sep 17 00:00:00 2001 From: Marcelo Schmitt Date: Sat, 8 Dec 2018 16:19:59 -0200 Subject: staging: iio: ad5933: add binding doc for ad5933 Add a devicetree documentation for the ad5933 and ad5934 impedance converter, network analyzer. Signed-off-by: Marcelo Schmitt Signed-off-by: Gabriel Capella Co-Developed-by: Gabriel Capella Signed-off-by: Jonathan Cameron --- .../bindings/iio/impedance-analyzer/ad5933.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/impedance-analyzer/ad5933.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/impedance-analyzer/ad5933.txt b/Documentation/devicetree/bindings/iio/impedance-analyzer/ad5933.txt new file mode 100644 index 000000000000..5ff38728ff91 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/impedance-analyzer/ad5933.txt @@ -0,0 +1,26 @@ +Analog Devices AD5933/AD5934 Impedance Converter, Network Analyzer + +https://www.analog.com/media/en/technical-documentation/data-sheets/AD5933.pdf +https://www.analog.com/media/en/technical-documentation/data-sheets/AD5934.pdf + +Required properties: + - compatible : should be one of + "adi,ad5933" + "adi,ad5934" + - reg : the I2C address. + - vdd-supply : The regulator supply for DVDD, AVDD1 and AVDD2 when they + are connected together. + +Optional properties: +- clocks : external clock reference. +- clock-names : must be "mclk" if clocks is set. + +Example for a I2C device node: + + impedance-analyzer@0d { + compatible = "adi,adxl345"; + reg = <0x0d>; + vdd-supply = <&vdd_supply>; + clocks = <&ref_clk>; + clock-names = "mclk"; + }; -- cgit v1.2.3 From bf81deacc6facb6fada5b3bb31a832ef77cf7e87 Mon Sep 17 00:00:00 2001 From: Tomasz Duszynski Date: Fri, 14 Dec 2018 19:28:03 +0100 Subject: dt-bindings: iio: chemical: sps30: add device tree support Add device tree support for Sensirion SPS30 particulate matter sensor. Signed-off-by: Tomasz Duszynski Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/chemical/sensirion,sps30.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.txt b/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.txt new file mode 100644 index 000000000000..6eee2709b5b6 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.txt @@ -0,0 +1,12 @@ +* Sensirion SPS30 particulate matter sensor + +Required properties: +- compatible: must be "sensirion,sps30" +- reg: the I2C address of the sensor + +Example: + +sps30@69 { + compatible = "sensirion,sps30"; + reg = <0x69>; +}; -- cgit v1.2.3 From 25bbdccfcd8c07c44feb74700f556546ef340f0f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 7 Nov 2018 16:47:08 +0100 Subject: dt-bindings: hwmon: tmp108: add optional interrupts and #thermal-sensor-cells The tmp108 does have an alert output that can be used as interrupt source and can of course also be used as part of a thermal sensor setup for things like thermal-based cpu frequencies, so document the necessary properties. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/tmp108.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/tmp108.txt b/Documentation/devicetree/bindings/hwmon/tmp108.txt index 8c4b10df86d9..54d4beed4ee5 100644 --- a/Documentation/devicetree/bindings/hwmon/tmp108.txt +++ b/Documentation/devicetree/bindings/hwmon/tmp108.txt @@ -7,6 +7,10 @@ Requires node properties: - compatible : "ti,tmp108" - reg : the I2C address of the device. This is 0x48, 0x49, 0x4a, or 0x4b. +Optional properties: +- interrupts: Reference to the TMP108 alert interrupt. +- #thermal-sensor-cells: should be set to 0. + Example: tmp108@48 { compatible = "ti,tmp108"; -- cgit v1.2.3 From e1fd3be613e9d00c4b04ba0e9de1a6233fceedf2 Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Sat, 17 Nov 2018 12:12:57 +0000 Subject: dt-bindings: hwmon: (ntc_thermistor) add B57891S0103 thermistor from Epcos These are Negative Temperature Coefficient thermistors, like the others in the list. Signed-off-by: Peter Rosin Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt index c3b9c4cfe8df..37f18d684f6a 100644 --- a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt +++ b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt @@ -4,6 +4,7 @@ NTC Thermistor hwmon sensors Requires node properties: - "compatible" value : one of "epcos,b57330v2103" + "epcos,b57891s0103" "murata,ncp15wb473" "murata,ncp18wb473" "murata,ncp21wb473" -- cgit v1.2.3 From 48049e205e7071c733508e12b036c3845d0e84a9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 23 Nov 2018 13:08:46 +0100 Subject: dt-bindings: hwmon: (lm90) Document ti,tmp451 compatible string The TI TMP451 temperature sensors are compatible with the National LM90 temperature sensors. Signed-off-by: Thierry Reding Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/lm90.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/lm90.txt b/Documentation/devicetree/bindings/hwmon/lm90.txt index 97581266e329..c76a7ac47c34 100644 --- a/Documentation/devicetree/bindings/hwmon/lm90.txt +++ b/Documentation/devicetree/bindings/hwmon/lm90.txt @@ -23,6 +23,7 @@ Required node properties: "onnn,nct1008" "winbond,w83l771" "nxp,sa56004" + "ti,tmp451" - reg: I2C bus address of the device -- cgit v1.2.3 From 3eaba568b54e572187a3f4a08d5582d4d623e7e3 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:21:31 +0000 Subject: dt-bindings: dmaengine: usb-dmac: Add binding for r8a774c0 This patch adds bindings for the r8a774c0 (RZ/G2E). Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt index 5e2c7e84c43e..372f0eeb5a2a 100644 --- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt @@ -8,6 +8,7 @@ Required Properties: - "renesas,r8a7745-usb-dmac" (RZ/G1E) - "renesas,r8a77470-usb-dmac" (RZ/G1C) - "renesas,r8a774a1-usb-dmac" (RZ/G2M) + - "renesas,r8a774c0-usb-dmac" (RZ/G2E) - "renesas,r8a7790-usb-dmac" (R-Car H2) - "renesas,r8a7791-usb-dmac" (R-Car M2-W) - "renesas,r8a7793-usb-dmac" (R-Car M2-N) -- cgit v1.2.3 From 47ec4cf405e238dac55df5e380bfe97842e0be68 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:17:43 +0000 Subject: dmaengine: rcar-dmac: Document R8A774C0 bindings Renesas' RZ/G2E (R8A774C0) SoC has DMA controllers compatible with this driver, therefore document RZ/G2E specific bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt index cdf32b2b77f9..5a512c5ea76a 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt @@ -21,6 +21,7 @@ Required Properties: - "renesas,dmac-r8a7745" (RZ/G1E) - "renesas,dmac-r8a77470" (RZ/G1C) - "renesas,dmac-r8a774a1" (RZ/G2M) + - "renesas,dmac-r8a774c0" (RZ/G2E) - "renesas,dmac-r8a7790" (R-Car H2) - "renesas,dmac-r8a7791" (R-Car M2-W) - "renesas,dmac-r8a7792" (R-Car V2H) -- cgit v1.2.3 From c42160d8efd885b54e681893b615e31b38e3d207 Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Thu, 18 Oct 2018 18:19:24 +0000 Subject: dt-bindings: mmc: fsl-imx-esdhc: add imx8qxp compatible string Add imx8qxp compatible string Cc: Rob Herring Cc: Mark Rutland Cc: Ulf Hansson Cc: linux-serial@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-mmc@vger.kernel.org Cc: Haibo Chen Signed-off-by: Dong Aisheng Reviewed-by: Rob Herring Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 3e29050ec769..9201a7d8d7b0 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -16,6 +16,7 @@ Required properties: "fsl,imx6sl-usdhc" "fsl,imx6sx-usdhc" "fsl,imx7d-usdhc" + "fsl,imx8qxp-usdhc" Optional properties: - fsl,wp-controller : Indicate to use controller internal write protection -- cgit v1.2.3 From bb16956e239e8d859b18a008e783550d6200aa7c Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Wed, 24 Oct 2018 17:23:01 -0500 Subject: dt-bindings: mmc: tmio_mmc: Document Renesas R7S9210 Document support for the RZ/A2 (R7S9210) SoC. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Reviewed-by: Simon Horman Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt index 27f2eab2981d..9391ae9a1d9d 100644 --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt @@ -13,6 +13,7 @@ Required properties: - compatible: should contain one or more of the following: "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC + "renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC @@ -56,7 +57,7 @@ Required properties: "core" and "cd". If the controller only has 1 clock, naming is not required. Devices which have more than 1 clock are listed below: - 2: R7S72100 + 2: R7S72100, R7S9210 Optional properties: - pinctrl-names: should be "default", "state_uhs" -- cgit v1.2.3 From 247cb8b7a79670ff37b992012431b7f5ec0e196d Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Mon, 12 Nov 2018 12:22:16 +0530 Subject: dt-bindings: mmc: sdhci-msm: Add SoC-specific compatible strings Add SoC-specific compatible strings for qcom-sdhci controller. Signed-off-by: Veerabhadrarao Badiganti Reviewed-by: Rob Herring Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index 502b3b851ebb..b72871ac90cb 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -4,12 +4,25 @@ This file documents differences between the core properties in mmc.txt and the properties used by the sdhci-msm driver. Required properties: -- compatible: Should contain: +- compatible: Should contain a SoC-specific string and a IP version string: + version strings: "qcom,sdhci-msm-v4" for sdcc versions less than 5.0 - "qcom,sdhci-msm-v5" for sdcc versions >= 5.0 + "qcom,sdhci-msm-v5" for sdcc version 5.0 For SDCC version 5.0.0, MCI registers are removed from SDCC interface and some registers are moved to HC. New compatible string is added to support this change - "qcom,sdhci-msm-v5". + full compatible strings with SoC and version: + "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4" + "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4" + "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4" + "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4" + "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4" + "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5" + "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5" + NOTE that some old device tree files may be floating around that only + have the string "qcom,sdhci-msm-v4" without the SoC compatible string + but doing that should be considered a deprecated practice. + - reg: Base address and length of the register in the following order: - Host controller register map (required) - SD Core register map (required) @@ -29,7 +42,7 @@ Required properties: Example: sdhc_1: sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; interrupts = <0 123 0>; bus-width = <8>; @@ -46,7 +59,7 @@ Example: }; sdhc_2: sdhci@f98a4900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; interrupts = <0 125 0>; bus-width = <4>; -- cgit v1.2.3 From 67b4ff9fb796d8e572a9bb82d851639a81812aa9 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Wed, 28 Nov 2018 14:34:26 -0800 Subject: dt-bindings: mmc: sdhci-msm: Clarify register requirements In sdhci-msm-v5 and beyond, the MCI registers are removed, so there is only one register region required. Signed-off-by: Evan Green Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index b72871ac90cb..da4edb146a98 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -25,7 +25,7 @@ Required properties: - reg: Base address and length of the register in the following order: - Host controller register map (required) - - SD Core register map (required) + - SD Core register map (required for msm-v4 and below) - interrupts: Should contain an interrupt-specifiers for the interrupts: - Host controller interrupt (required) - pinctrl-names: Should contain only one value - "default". -- cgit v1.2.3 From f98b4f98bbc823d2f376f2c6c33d21bde20423cf Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Tue, 11 Dec 2018 00:05:05 +0530 Subject: dt-bindings: mmc: sdhci-am654: Document bindings for the host controllers on TI's AM654 SOCs Add binding documentation for mmc host controllers present on TI's AM654 SOCs. Signed-off-by: Faiz Abbas Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/sdhci-am654.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-am654.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.txt b/Documentation/devicetree/bindings/mmc/sdhci-am654.txt new file mode 100644 index 000000000000..15dbbbace27e --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-am654.txt @@ -0,0 +1,36 @@ +Device Tree Bindings for the SDHCI Controllers present on TI's AM654 SOCs + +The bindings follow the mmc[1], clock[2] and interrupt[3] bindings. +Only deviations are documented here. + + [1] Documentation/devicetree/bindings/mmc/mmc.txt + [2] Documentation/devicetree/bindings/clock/clock-bindings.txt + [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + +Required Properties: + - compatible: should be "ti,am654-sdhci-5.1" + - reg: Must be two entries. + - The first should be the sdhci register space + - The second should the subsystem/phy register space + - clocks: Handles to the clock inputs. + - clock-names: Tuple including "clk_xin" and "clk_ahb" + - interrupts: Interrupt specifiers + - ti,otap-del-sel: Output Tap Delay select + - ti,trm-icp: DLL trim select + - ti,driver-strength-ohm: driver strength in ohms. + Valid values are 33, 40, 50, 66 and 100 ohms. + +Example: + + sdhci0: sdhci@4f80000 { + compatible = "ti,am654-sdhci-5.1"; + reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; + power-domains = <&k3_pds 47>; + clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; + clock-names = "clk_ahb", "clk_xin"; + interrupts = ; + sdhci-caps-mask = <0x80000007 0x0>; + mmc-ddr-1_8v; + ti,otap-del-sel = <0x2>; + ti,trm-icp = <0x8>; + }; -- cgit v1.2.3 From 49d14adb0031e380e6a0d52d2b853a7f8db3f65f Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Tue, 11 Dec 2018 00:05:06 +0530 Subject: dt-bindings: mmc: sdhci-of-arasan: Add deprecated message for AM65 Commit 26a4f38d1316 ("dt-bindings: mmc: sdhci-of-arasan: Add new compatible for AM654 MMC PHY") added a new compatible for supporting controllers on TI's AM65x SOCs. It turns out that the controller is not compatible with the arasan driver's phy and consumer model as it requires some phy registers for core sdhci functionality. This calls for the binding to branch out to a new driver. Therefore, add a deprecated message for the ti,am654-sdhci-5.1 binding. Signed-off-by: Faiz Abbas Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index e2effe17f05e..1edbb049cccb 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -16,6 +16,10 @@ Required Properties: - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY For this device it is strongly suggested to include arasan,soc-ctl-syscon. - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY + Note: This binding has been deprecated and moved to [5]. + + [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt + - reg: From mmc bindings: Register location and length. - clocks: From clock bindings: Handles to clock inputs. - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" -- cgit v1.2.3 From 58fe8bbacd285af44831f68da1d2d50f0e2fc9a9 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Tue, 11 Dec 2018 19:52:52 +0530 Subject: dt-bindings: sdhci-omap: Add note for cpu_thermal The driver fetches a thermal zone using the string "cpu_thermal" for tuning operation. Add a note for the same. Signed-off-by: Faiz Abbas Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-omap.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt b/Documentation/devicetree/bindings/mmc/sdhci-omap.txt index 393848c2138e..72c4dec7e1db 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-omap.txt @@ -2,6 +2,8 @@ Refer to mmc.txt for standard MMC bindings. +For UHS devices which require tuning, the device tree should have a "cpu_thermal" node which maps to the appropriate thermal zone. This is used to get the temperature of the zone during tuning. + Required properties: - compatible: Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers Should be "ti,k2g-sdhci" for K2G -- cgit v1.2.3 From ab409be2be555e61516214885537dcb619f12e9e Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:22:09 +0000 Subject: dt-bindings: mmc: renesas_sdhi: Add r8a774c0 support Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt index 9391ae9a1d9d..2b4f17ca9087 100644 --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt @@ -20,6 +20,7 @@ Required properties: "renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC "renesas,sdhi-r8a774a1" - SDHI IP on R8A774A1 SoC + "renesas,sdhi-r8a774c0" - SDHI IP on R8A774C0 SoC "renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC "renesas,sdhi-mmc-r8a77470" - SDHI/MMC IP on R8A77470 SoC "renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC -- cgit v1.2.3 From 69d24c6ed67c1e15f76284fccd62feffe77c8d38 Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Thu, 13 Dec 2018 14:35:07 +0530 Subject: dt-bindings: arm-smmu: Add binding doc for Qcom smmu-500 Qcom's implementation of arm,mmu-500 works well with current arm-smmu driver implementation. Adding a soc specific compatible along with arm,mmu-500 makes the bindings future safe. Signed-off-by: Vivek Gautam Reviewed-by: Rob Herring Cc: Will Deacon Acked-by: Will Deacon Signed-off-by: Joerg Roedel --- Documentation/devicetree/bindings/iommu/arm,smmu.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index a6504b37cc21..3133f3ba7567 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -27,6 +27,10 @@ conditions. "qcom,msm8996-smmu-v2", "qcom,smmu-v2", "qcom,sdm845-smmu-v2", "qcom,smmu-v2". + Qcom SoCs implementing "arm,mmu-500" must also include, + as below, SoC-specific compatibles: + "qcom,sdm845-smmu-500", "arm,mmu-500" + - reg : Base address and size of the SMMU. - #global-interrupts : The number of global interrupts exposed by the -- cgit v1.2.3 From a6cf933a359f6cf0c642580602a0f5afc40d991a Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:19:28 +0000 Subject: dt-bindings: iommu: ipmmu-vmsa: Add r8a774c0 support Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Joerg Roedel --- Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt index e285c8ad1b39..b6bfbec3a849 100644 --- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt @@ -15,6 +15,7 @@ Required Properties: - "renesas,ipmmu-r8a7744" for the R8A7744 (RZ/G1N) IPMMU. - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU. - "renesas,ipmmu-r8a774a1" for the R8A774A1 (RZ/G2M) IPMMU. + - "renesas,ipmmu-r8a774c0" for the R8A774C0 (RZ/G2E) IPMMU. - "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU. - "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU. - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU. -- cgit v1.2.3 From bdb48e4c7d0796850d4c1a24fe1386677e8a922c Mon Sep 17 00:00:00 2001 From: Darwin Dingel Date: Mon, 10 Dec 2018 11:27:39 +1300 Subject: dt-bindings: serial: 8250: Add rate limit for serial port input overruns When a serial port continuously experiences input overrun from (1) continuous receive characters from remote and or (2) hardware issues, its interrupt handler can preempt other tasks especially when the system is busy (ie. boot up period). This can cause other tasks to get starved of processing time from the CPU. When this dts binding is enabled and input overrun on the serial port is detected, serial port receive will be throttled to give some breathing room for processing other tasks. Value provided will be in milliseconds. &serial0{ overrun-throttle-ms = <500>; }; Signed-off-by: Darwin Dingel Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/8250.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/8250.txt b/Documentation/devicetree/bindings/serial/8250.txt index aeb6db4e35c3..da50321da34d 100644 --- a/Documentation/devicetree/bindings/serial/8250.txt +++ b/Documentation/devicetree/bindings/serial/8250.txt @@ -51,6 +51,7 @@ Optional properties: - tx-threshold: Specify the TX FIFO low water indication for parts with programmable TX FIFO thresholds. - resets : phandle + reset specifier pairs +- overrun-throttle-ms : how long to pause uart rx when input overrun is encountered. Note: * fsl,ns16550: -- cgit v1.2.3 From b5c8f358ce7c0cd1bd821962ccb2c7fd050e9339 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 17 Dec 2018 04:47:40 +0000 Subject: dt-bindings: iio: magnetometer: add dt-bindings for freescale mag3110 Add Freescale MAG3110 dt-bindings and remove it from trivial-devices dt-bingding doc. Signed-off-by: Anson Huang [robh: fixup trivial-devices.txt change for trivial-devices.yaml] Signed-off-by: Rob Herring --- .../bindings/iio/magnetometer/mag3110.txt | 27 ++++++++++++++++++++++ .../devicetree/bindings/trivial-devices.yaml | 2 -- 2 files changed, 27 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/magnetometer/mag3110.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/magnetometer/mag3110.txt b/Documentation/devicetree/bindings/iio/magnetometer/mag3110.txt new file mode 100644 index 000000000000..bdd40bcaaa1f --- /dev/null +++ b/Documentation/devicetree/bindings/iio/magnetometer/mag3110.txt @@ -0,0 +1,27 @@ +* FREESCALE MAG3110 magnetometer sensor + +Required properties: + + - compatible : should be "fsl,mag3110" + - reg : the I2C address of the magnetometer + +Optional properties: + + - interrupts: the sole interrupt generated by the device + + Refer to interrupt-controller/interrupts.txt for generic interrupt client + node bindings. + + - vdd-supply: phandle to the regulator that provides power to the sensor. + - vddio-supply: phandle to the regulator that provides power to the sensor's IO. + +Example: + +magnetometer@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_mag3110_int>; + interrupt-parent = <&gpio3>; + interrupts = <16 IRQ_TYPE_EDGE_RISING>; +}; diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 0f4632e05e16..cc64ec63a6ad 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -80,8 +80,6 @@ properties: - domintech,dmard09 # DMARD10: 3-axis Accelerometer - domintech,dmard10 - # MAG3110: Xtrinsic High Accuracy, 3D Magnetometer - - fsl,mag3110 # MMA7660FC: 3-Axis Orientation/Motion Detection Sensor - fsl,mma7660 # MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer -- cgit v1.2.3 From 12d6dd06989171ba9486790116832a65c5316fb1 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:18:14 +0000 Subject: dt-bindings: gpio: rcar: Add r8a774c0 (RZ/G2E) support Document Renesas' RZ/G2E (R8A774C0) GPIO blocks compatibility within the relevant dt-bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt index 2889bbcd7416..f3f2c468c1b6 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt @@ -8,6 +8,7 @@ Required Properties: - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller. - "renesas,gpio-r8a77470": for R8A77470 (RZ/G1C) compatible GPIO controller. - "renesas,gpio-r8a774a1": for R8A774A1 (RZ/G2M) compatible GPIO controller. + - "renesas,gpio-r8a774c0": for R8A774C0 (RZ/G2E) compatible GPIO controller. - "renesas,gpio-r8a7778": for R8A7778 (R-Car M1) compatible GPIO controller. - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. -- cgit v1.2.3 From 3f74383f29ca2e0c7d9362c4c65a7c2cb4e1fd5f Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 08:41:47 +0000 Subject: dt-bindings: i2c: sh_mobile: Add r8a774c0 support Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt index bc876b71d1e4..202602e6e837 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt @@ -8,6 +8,7 @@ Required properties: - "renesas,iic-r8a7744" (RZ/G1N) - "renesas,iic-r8a7745" (RZ/G1E) - "renesas,iic-r8a774a1" (RZ/G2M) + - "renesas,iic-r8a774c0" (RZ/G2E) - "renesas,iic-r8a7790" (R-Car H2) - "renesas,iic-r8a7791" (R-Car M2-W) - "renesas,iic-r8a7792" (R-Car V2H) @@ -32,10 +33,10 @@ Required properties: When compatible with "renesas,rmobile-iic" it should be the last compatibility string listed. - The r8a77990 (R-Car E3) controller is not - considered compatible with "renesas,rcar-gen3-iic" - or "renesas,rmobile-iic" due to the absence of - automatic transmission registers. + The r8a77990 (R-Car E3) and r8a774c0 (RZ/G2E) + controllers are not considered compatible with + "renesas,rcar-gen3-iic" or "renesas,rmobile-iic" + due to the absence of automatic transmission registers. - reg : address start and address range size of device - interrupts : interrupt of device -- cgit v1.2.3 From 1ccf1980e3e4853ecf11804774ef6ac071911150 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:19:02 +0000 Subject: dt-bindings: i2c: rcar: Add r8a774c0 support Document RZ/G2E (R8A774C0) I2C compatibility with the relevant device dt-bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt index 30c0485b167b..3ee5e8f6ee01 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt @@ -7,6 +7,7 @@ Required properties: "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC. "renesas,i2c-r8a77470" if the device is a part of a R8A77470 SoC. "renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC. + "renesas,i2c-r8a774c0" if the device is a part of a R8A774C0 SoC. "renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC. "renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC. "renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC. -- cgit v1.2.3 From f2bb7d6a82da32bfd59c65540758fd2a01cccf74 Mon Sep 17 00:00:00 2001 From: Honghui Zhang Date: Fri, 14 Dec 2018 09:25:40 +0800 Subject: dt-bindings: PCI: MediaTek: Remove un-used property The "num-lanes" property is not used, remove it. Signed-off-by: Honghui Zhang Signed-off-by: Lorenzo Pieralisi --- Documentation/devicetree/bindings/pci/mediatek-pcie.txt | 8 -------- 1 file changed, 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt index 20227a875ac8..92437a366e5f 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt @@ -65,7 +65,6 @@ Required properties: explanation. - ranges: Sub-ranges distributed from the PCIe controller node. An empty property is sufficient. -- num-lanes: Number of lanes to use for this port. Examples for MT7623: @@ -118,7 +117,6 @@ Examples for MT7623: interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; ranges; - num-lanes = <1>; }; pcie@1,0 { @@ -129,7 +127,6 @@ Examples for MT7623: interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; ranges; - num-lanes = <1>; }; pcie@2,0 { @@ -140,7 +137,6 @@ Examples for MT7623: interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; ranges; - num-lanes = <1>; }; }; @@ -172,7 +168,6 @@ Examples for MT2712: #size-cells = <2>; #interrupt-cells = <1>; ranges; - num-lanes = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc0 0>, <0 0 0 2 &pcie_intc0 1>, @@ -191,7 +186,6 @@ Examples for MT2712: #size-cells = <2>; #interrupt-cells = <1>; ranges; - num-lanes = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc1 0>, <0 0 0 2 &pcie_intc1 1>, @@ -245,7 +239,6 @@ Examples for MT7622: #size-cells = <2>; #interrupt-cells = <1>; ranges; - num-lanes = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc0 0>, <0 0 0 2 &pcie_intc0 1>, @@ -264,7 +257,6 @@ Examples for MT7622: #size-cells = <2>; #interrupt-cells = <1>; ranges; - num-lanes = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc1 0>, <0 0 0 2 &pcie_intc1 1>, -- cgit v1.2.3 From ff63495eff8139af1d33e9733d74b399fc8a84e7 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 17 Dec 2018 15:01:19 +0100 Subject: dt-bindings/irq: Add binding for Freescale IRQSTEER multiplexer This adds the DT binding for the Freescale IRQSTEER interrupt multiplexer found in the i.MX8 familiy SoCs. Reviewed-by: Rob Herring Signed-off-by: Lucas Stach Signed-off-by: Marc Zyngier --- .../bindings/interrupt-controller/fsl,irqsteer.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt new file mode 100644 index 000000000000..45790ce6f5b9 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt @@ -0,0 +1,34 @@ +Freescale IRQSTEER Interrupt multiplexer + +Required properties: + +- compatible: should be: + - "fsl,imx8m-irqsteer" + - "fsl,imx-irqsteer" +- reg: Physical base address and size of registers. +- interrupts: Should contain the parent interrupt line used to multiplex the + input interrupts. +- clocks: Should contain one clock for entry in clock-names + see Documentation/devicetree/bindings/clock/clock-bindings.txt +- clock-names: + - "ipg": main logic clock +- interrupt-controller: Identifies the node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- fsl,channel: The output channel that all input IRQs should be steered into. +- fsl,irq-groups: Number of IRQ groups managed by this controller instance. + Each group manages 64 input interrupts. + +Example: + + interrupt-controller@32e2d000 { + compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; + reg = <0x32e2d000 0x1000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,irq-groups = <1>; + interrupt-controller; + #interrupt-cells = <1>; + }; -- cgit v1.2.3 From 897898a69451dc31950d200c0fcdba24428a6482 Mon Sep 17 00:00:00 2001 From: Benjamin Gaignard Date: Mon, 17 Dec 2018 15:22:13 +0100 Subject: dt-bindings: interrupt-controller: stm32: Document hwlock properties Add hwlocks as optional property Reviewed-by: Rob Herring Signed-off-by: Benjamin Gaignard Signed-off-by: Marc Zyngier --- .../devicetree/bindings/interrupt-controller/st,stm32-exti.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt index 6a36bf66d932..cd01b2292ec6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt @@ -14,6 +14,10 @@ Required properties: (only needed for exti controller with multiple exti under same parent interrupt: st,stm32-exti and st,stm32h7-exti) +Optional properties: + +- hwlocks: reference to a phandle of a hardware spinlock provider node. + Example: exti: interrupt-controller@40013c00 { -- cgit v1.2.3 From f9135ffa8a272bde9928e75ce14d02d4496159ae Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 26 Oct 2018 09:01:44 +0100 Subject: dt-bindings: timer: renesas, cmt: Document r8a7796 CMT support Document SoC specific bindings for R-Car M3-W (r8a7796) SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 33992679a8bd..6de27b60b51a 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -36,6 +36,8 @@ Required Properties: - "renesas,r8a7793-cmt1" for the 48-bit CMT1 device included in r8a7793. - "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794. - "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794. + - "renesas,r8a7796-cmt0" for the 32-bit CMT0 device included in r8a7796. + - "renesas,r8a7796-cmt1" for the 48-bit CMT1 device included in r8a7796. - "renesas,r8a77970-cmt0" for the 32-bit CMT0 device included in r8a77970. - "renesas,r8a77970-cmt1" for the 48-bit CMT1 device included in r8a77970. - "renesas,r8a77980-cmt0" for the 32-bit CMT0 device included in r8a77980. -- cgit v1.2.3 From 2bbaf54216448486def1153486778a975a73041d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 26 Oct 2018 09:36:13 +0100 Subject: dt-bindings: timer: renesas, cmt: Document r8a77470 CMT support Document SoC specific compatible strings for r8a77470. No driver change is needed as the fallback strings will activate the right code. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 6de27b60b51a..eb602c599341 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -28,6 +28,8 @@ Required Properties: - "renesas,r8a7744-cmt1" for the 48-bit CMT1 device included in r8a7744. - "renesas,r8a7745-cmt0" for the 32-bit CMT0 device included in r8a7745. - "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745. + - "renesas,r8a77470-cmt0" for the 32-bit CMT0 device included in r8a77470. + - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470. - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. -- cgit v1.2.3 From e5a805202c8ebb3b27cd8ad1b227158ae9cb9464 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 19 Nov 2018 16:14:13 +0000 Subject: dt-bindings: timer: renesas, cmt: Document r8a774a1 CMT support Document SoC specific bindings for RZ/G2M (r8a774a1) SoC. Signed-off-by: Biju Das Reviewed-by: Simon Horman Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index eb602c599341..862a80f0380a 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -30,6 +30,8 @@ Required Properties: - "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745. - "renesas,r8a77470-cmt0" for the 32-bit CMT0 device included in r8a77470. - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470. + - "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1. + - "renesas,r8a774a1-cmt1" for the 48-bit CMT1 device included in r8a774a1. - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. @@ -51,9 +53,12 @@ Required Properties: and RZ/G1. These are fallbacks for r8a73a4, R-Car Gen2 and RZ/G1 entries listed above. - - "renesas,rcar-gen3-cmt0" for 32-bit CMT0 devices included in R-Car Gen3. - - "renesas,rcar-gen3-cmt1" for 48-bit CMT1 devices included in R-Car Gen3. - These are fallbacks for R-Car Gen3 entries listed above. + - "renesas,rcar-gen3-cmt0" for 32-bit CMT0 devices included in R-Car Gen3 + and RZ/G2. + - "renesas,rcar-gen3-cmt1" for 48-bit CMT1 devices included in R-Car Gen3 + and RZ/G2. + These are fallbacks for R-Car Gen3 and RZ/G2 entries listed + above. - reg: base address and length of the registers block for the timer module. - interrupts: interrupt-specifier for the timer, one per channel. -- cgit v1.2.3 From 3c3d71013c7655b9cc4043c9f8845f0c4402d71d Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 18 Dec 2018 22:42:23 +0100 Subject: rtc: pcf2123: Add Microcrystal rv2123 Add a compatible string for Microcrystal rv2123 as the reset procedure seem to be differing. However, the current driver works just fine. Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/nxp,rtc-2123.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/nxp,rtc-2123.txt b/Documentation/devicetree/bindings/rtc/nxp,rtc-2123.txt index 811124a36d16..1994f601800a 100644 --- a/Documentation/devicetree/bindings/rtc/nxp,rtc-2123.txt +++ b/Documentation/devicetree/bindings/rtc/nxp,rtc-2123.txt @@ -2,6 +2,7 @@ NXP PCF2123 SPI Real Time Clock Required properties: - compatible: should be: "nxp,rtc-pcf2123" + or "microcrystal,rv2123" - reg: should be the SPI slave chipselect address Optional properties: -- cgit v1.2.3 From 0a3b0c7f979563c97a136c51e43ef724121e83ed Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 14 Dec 2018 09:40:23 +0530 Subject: dt-bindings: cpufreq: Introduce QCOM cpufreq firmware bindings Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's SoCs. This is required for managing the cpu frequency transitions which are controlled by the hardware engine. Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd Acked-by: Viresh Kumar Tested-by: Amit Kucheria Reviewed-by: Rob Herring Signed-off-by: Rafael J. Wysocki --- .../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 +++++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt new file mode 100644 index 000000000000..33856947c561 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt @@ -0,0 +1,172 @@ +Qualcomm Technologies, Inc. CPUFREQ Bindings + +CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) +SoCs to manage frequency in hardware. It is capable of controlling frequency +for multiple clusters. + +Properties: +- compatible + Usage: required + Value type: + Definition: must be "qcom,cpufreq-hw". + +- clocks + Usage: required + Value type: From common clock binding. + Definition: clock handle for XO clock and GPLL0 clock. + +- clock-names + Usage: required + Value type: From common clock binding. + Definition: must be "xo", "alternate". + +- reg + Usage: required + Value type: + Definition: Addresses and sizes for the memory of the HW bases in + each frequency domain. +- reg-names + Usage: Optional + Value type: + Definition: Frequency domain name i.e. + "freq-domain0", "freq-domain1". + +- #freq-domain-cells: + Usage: required. + Definition: Number of cells in a freqency domain specifier. + +* Property qcom,freq-domain +Devices supporting freq-domain must set their "qcom,freq-domain" property with +phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. + + +Example: + +Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch +DCVS state together. + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + }; + + soc { + cpufreq_hw: cpufreq@17d43000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; +} -- cgit v1.2.3 From 6ae81eebdef97109c32e545e90865bc5b14178f1 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 17 Dec 2018 12:04:35 +0800 Subject: dt-bindings: net: broadcom-bluetooth: Fix external clock names The Broadcom Bluetooth controllers can take up to two external clocks: an external frequency reference, substituting the main crystal, and a LPO clock at 32.768 kHz substituting the internal LPO clock. In particular, the external LPO clock must be used when the controller does not have NVRAM connected, and the main reference frequency is not the default 20 MHz. This is described in detail in the datasheet. The original "extclk" clock name is ambiguous as to which of these it refers to, and some designs might even require both. This patch deprecates the existing name, and adds "txco" and "lpo". Tested-by: Ondrej Jirman Signed-off-by: Chen-Yu Tsai Signed-off-by: Marcel Holtmann --- Documentation/devicetree/bindings/net/broadcom-bluetooth.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt index 4194ff7e6ee6..711c75ac2bb5 100644 --- a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt +++ b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt @@ -18,8 +18,11 @@ Optional properties: - shutdown-gpios: GPIO specifier, used to enable the BT module - device-wakeup-gpios: GPIO specifier, used to wakeup the controller - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor - - clocks: clock specifier if external clock provided to the controller - - clock-names: should be "extclk" + - clocks: 1 or 2 clocks as defined in clock-names below, in that order + - clock-names: names for clock inputs, matching the clocks given + - "extclk": deprecated, replaced by "txco" + - "txco": external reference clock (not a standalone crystal) + - "lpo": external low power 32.768 kHz clock Example: -- cgit v1.2.3 From 061a8aaf4c0f2885f1fa1dd6bf8ea27ab5059fa9 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 17 Dec 2018 12:04:36 +0800 Subject: dt-bindings: net: broadcom-bluetooth: Add VBAT and VDDIO supplies The Broadcom Bluetooth chips have two power inputs, VBAT and VDDIO. The former provides overall power for the chip, while the latter powers the I/O pins and buffers. This patch adds properties for the two so we can describe the power supply relationships. Reviewed-by: Rob Herring Tested-by: Ondrej Jirman Signed-off-by: Chen-Yu Tsai Signed-off-by: Marcel Holtmann --- Documentation/devicetree/bindings/net/broadcom-bluetooth.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt index 711c75ac2bb5..78cfa0fbece9 100644 --- a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt +++ b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt @@ -23,6 +23,8 @@ Optional properties: - "extclk": deprecated, replaced by "txco" - "txco": external reference clock (not a standalone crystal) - "lpo": external low power 32.768 kHz clock + - vbat-supply: phandle to regulator supply for VBAT + - vddio-supply: phandle to regulator supply for VDDIO Example: -- cgit v1.2.3 From bfbc47bd5901168f0fdb337e9be1759bedf8ff4e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 17 Dec 2018 12:04:37 +0800 Subject: dt-bindings: net: broadcom-bluetooth: Add BCM20702A1 compatible string The BCM20702A1 is a Bluetooth 4.0 chip from Broadcom. It is found in the Ampak AP6210 WiFi+BT module, identified from the read verbose config info command response. However the Bluetooth firmware provided by vendors uses the name BCM20710. This patch elects to use the chip ID returned by the chip for the compatible string. Reviewed-by: Rob Herring Tested-by: Ondrej Jirman Signed-off-by: Chen-Yu Tsai Signed-off-by: Marcel Holtmann --- Documentation/devicetree/bindings/net/broadcom-bluetooth.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt index 78cfa0fbece9..d9d734a07faf 100644 --- a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt +++ b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt @@ -10,6 +10,7 @@ device the slave device is attached to. Required properties: - compatible: should contain one of the following: + * "brcm,bcm20702a1" * "brcm,bcm43438-bt" Optional properties: -- cgit v1.2.3 From 31f20f5f6d14ffe8d9a87c0ef58ee7ed72a3db63 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 17 Dec 2018 12:04:38 +0800 Subject: dt-bindings: net: broadcom-bluetooth: Add BCM4330 compatible string The BCM4330 is a 802.11 a/b/g/n WiFi + Bluetooth 4.0 chip from Broadcom. It is found in the Ampak AP6330 WiFi+BT module. The partiular one I have identifies as BCM4330B1 for Bluetooth and BCM4330/4 for WiFi. It is unclear if the AP6330 module uses this revision of the BCM4330, or if there are multiple revisions. The module does not have revision markings. This patch elects to use just BCM4330 for the compatible string. Reviewed-by: Rob Herring Signed-off-by: Chen-Yu Tsai Signed-off-by: Marcel Holtmann --- Documentation/devicetree/bindings/net/broadcom-bluetooth.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt index d9d734a07faf..c26f4e11037c 100644 --- a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt +++ b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt @@ -11,6 +11,7 @@ Required properties: - compatible: should contain one of the following: * "brcm,bcm20702a1" + * "brcm,bcm4330-bt" * "brcm,bcm43438-bt" Optional properties: -- cgit v1.2.3 From 9d84d3e6bd6871a0c410fc1c0571fa025236bf7e Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Mon, 17 Dec 2018 15:00:51 +0000 Subject: dt-bindings: serial: lpuart: add imx8qxp compatible string Add imx8qxp compatible string Cc: Mark Rutland Cc: linux-serial@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: Greg Kroah-Hartman Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index 6bd3f2e93d61..21483ba820bc 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -8,6 +8,8 @@ Required properties: on LS1021A SoC with 32-bit big-endian register organization - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated on i.MX7ULP SoC with 32-bit little-endian register organization + - "fsl,imx8qxp-lpuart" for lpuart compatible with the one integrated + on i.MX8QXP SoC with 32-bit little-endian register organization - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names -- cgit v1.2.3 From 2e64d317e197ec390e3914773489fcade7bbbf15 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 10 Dec 2018 23:05:44 +0530 Subject: dt-bindings: timer: Document RDA8810PL SoC timer Document RDA Micro RDA8810PL SoC timer. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/rda,8810pl-timer.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/rda,8810pl-timer.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/rda,8810pl-timer.txt b/Documentation/devicetree/bindings/timer/rda,8810pl-timer.txt new file mode 100644 index 000000000000..4db542c9a0fd --- /dev/null +++ b/Documentation/devicetree/bindings/timer/rda,8810pl-timer.txt @@ -0,0 +1,20 @@ +RDA Micro RDA8810PL Timer + +Required properties: +- compatible : "rda,8810pl-timer" +- reg : Offset and length of the register set for the device. +- interrupts : Should contain two interrupts. +- interrupt-names : Should be "hwtimer", "ostimer". + +Example: + + apb@20900000 { + compatible = "simple-bus"; + ... + timer@10000 { + compatible = "rda,8810pl-timer"; + reg = <0x10000 0x1000>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>, + <17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hwtimer", "ostimer"; + }; -- cgit v1.2.3 From 6c4d975812677fdacfe657b8a1fae11de2fb4a37 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 19 Dec 2018 10:06:24 +0000 Subject: dt-bindings: serial: sh-sci: Document r8a774a1 bindings RZ/G2M (R8A774A1) SoC also has the R-Car Gen3 compatible SCIF and HSCIF ports, so document the SoC specific bindings. While at it, update the RZ/G1 and RZ/G2 family specific strings description as outdated. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Rob Herring Reviewed-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/serial/renesas,sci-serial.txt | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index e52e16c6bc57..21526e8ed502 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -24,6 +24,8 @@ Required properties: - "renesas,hscif-r8a7745" for R8A7745 (RZ/G1E) HSCIF compatible UART. - "renesas,scif-r8a77470" for R8A77470 (RZ/G1C) SCIF compatible UART. - "renesas,hscif-r8a77470" for R8A77470 (RZ/G1C) HSCIF compatible UART. + - "renesas,scif-r8a774a1" for R8A774A1 (RZ/G2M) SCIF compatible UART. + - "renesas,hscif-r8a774a1" for R8A774A1 (RZ/G2M) HSCIF compatible UART. - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART. - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART. - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART. @@ -61,13 +63,13 @@ Required properties: - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART. - "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART. - "renesas,rcar-gen1-scif" for R-Car Gen1 SCIF compatible UART, - - "renesas,rcar-gen2-scif" for R-Car Gen2 SCIF compatible UART, - - "renesas,rcar-gen3-scif" for R-Car Gen3 SCIF compatible UART, - - "renesas,rcar-gen2-scifa" for R-Car Gen2 SCIFA compatible UART, - - "renesas,rcar-gen2-scifb" for R-Car Gen2 SCIFB compatible UART, + - "renesas,rcar-gen2-scif" for R-Car Gen2 and RZ/G1 SCIF compatible UART, + - "renesas,rcar-gen3-scif" for R-Car Gen3 and RZ/G2 SCIF compatible UART, + - "renesas,rcar-gen2-scifa" for R-Car Gen2 and RZ/G1 SCIFA compatible UART, + - "renesas,rcar-gen2-scifb" for R-Car Gen2 and RZ/G1 SCIFB compatible UART, - "renesas,rcar-gen1-hscif" for R-Car Gen1 HSCIF compatible UART, - - "renesas,rcar-gen2-hscif" for R-Car Gen2 HSCIF compatible UART, - - "renesas,rcar-gen3-hscif" for R-Car Gen3 HSCIF compatible UART, + - "renesas,rcar-gen2-hscif" for R-Car Gen2 and RZ/G1 HSCIF compatible UART, + - "renesas,rcar-gen3-hscif" for R-Car Gen3 and RZ/G2 HSCIF compatible UART, - "renesas,scif" for generic SCIF compatible UART. - "renesas,scifa" for generic SCIFA compatible UART. - "renesas,scifb" for generic SCIFB compatible UART. -- cgit v1.2.3 From a88c4736ea36396f4a7b1460202a8caa434238db Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 19 Dec 2018 10:06:25 +0000 Subject: dt-bindings: serial: sh-sci: Document r8a774c0 bindings RZ/G2E (R8A774C0) SoC also has the R-Car Gen3 compatible SCIF and HSCIF ports, so document the SoC specific bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 21526e8ed502..20232ad05d89 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -26,6 +26,8 @@ Required properties: - "renesas,hscif-r8a77470" for R8A77470 (RZ/G1C) HSCIF compatible UART. - "renesas,scif-r8a774a1" for R8A774A1 (RZ/G2M) SCIF compatible UART. - "renesas,hscif-r8a774a1" for R8A774A1 (RZ/G2M) HSCIF compatible UART. + - "renesas,scif-r8a774c0" for R8A774C0 (RZ/G2E) SCIF compatible UART. + - "renesas,hscif-r8a774c0" for R8A774C0 (RZ/G2E) HSCIF compatible UART. - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART. - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART. - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART. -- cgit v1.2.3 From 7cd2103911018ecc6f3d2e6239ab5e00fb684d76 Mon Sep 17 00:00:00 2001 From: Yue Wang Date: Tue, 18 Dec 2018 16:04:45 +0800 Subject: dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds documentation for the DT bindings in Meson PCIe controller. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt new file mode 100644 index 000000000000..12b18f82d441 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt @@ -0,0 +1,70 @@ +Amlogic Meson AXG DWC PCIE SoC controller + +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. +It shares common functions with the PCIe DesignWare core driver and +inherits common properties defined in +Documentation/devicetree/bindings/pci/designware-pci.txt. + +Additional properties are described here: + +Required properties: +- compatible: + should contain "amlogic,axg-pcie" to identify the core. +- reg: + should contain the configuration address space. +- reg-names: Must be + - "elbi" External local bus interface registers + - "cfg" Meson specific registers + - "phy" Meson PCIE PHY registers + - "config" PCIe configuration space +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. +- clocks: Must contain an entry for each entry in clock-names. +- clock-names: Must include the following entries: + - "pclk" PCIe GEN 100M PLL clock + - "port" PCIe_x(A or B) RC clock gate + - "general" PCIe Phy clock + - "mipi" PCIe_x(A or B) 100M ref clock gate +- resets: phandle to the reset lines. +- reset-names: must contain "phy" "port" and "apb" + - "phy" Share PHY reset + - "port" Port A or B reset + - "apb" Share APB reset +- device_type: + should be "pci". As specified in designware-pcie.txt + + +Example configuration: + + pcie: pcie@f9800000 { + compatible = "amlogic,axg-pcie", "snps,dw-pcie"; + reg = <0x0 0xf9800000 0x0 0x400000 + 0x0 0xff646000 0x0 0x2000 + 0x0 0xff644000 0x0 0x2000 + 0x0 0xf9f00000 0x0 0x100000>; + reg-names = "elbi", "cfg", "phy", "config"; + reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; + + clocks = <&clkc CLKID_USB + &clkc CLKID_MIPI_ENABLE + &clkc CLKID_PCIE_A + &clkc CLKID_PCIE_CML_EN0>; + clock-names = "general", + "mipi", + "pclk", + "port"; + resets = <&reset RESET_PCIE_PHY>, + <&reset RESET_PCIE_A>, + <&reset RESET_PCIE_APB>; + reset-names = "phy", + "port", + "apb"; + }; -- cgit v1.2.3 From db67cdb04234899d0c1a734beef4bfea4c38efef Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Fri, 7 Dec 2018 09:53:11 +0900 Subject: dt-bindings: PCI: Add UniPhier PCIe host controller description Add DT bindings for PCIe controller implemented in UniPhier SoCs when configured in Root Complex (host) mode. This controller is based on the DesignWare PCIe core. Signed-off-by: Kunihiko Hayashi Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/uniphier-pcie.txt | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/uniphier-pcie.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt new file mode 100644 index 000000000000..1fa2c5906d4d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -0,0 +1,81 @@ +Socionext UniPhier PCIe host controller bindings + +This describes the devicetree bindings for PCIe host controller implemented +on Socionext UniPhier SoCs. + +UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core. +It shares common functions with the PCIe DesignWare core driver and inherits +common properties defined in +Documentation/devicetree/bindings/pci/designware-pcie.txt. + +Required properties: +- compatible: Should be "socionext,uniphier-pcie". +- reg: Specifies offset and length of the register set for the device. + According to the reg-names, appropriate register sets are required. +- reg-names: Must include the following entries: + "dbi" - controller configuration registers + "link" - SoC-specific glue layer registers + "config" - PCIe configuration space +- clocks: A phandle to the clock gate for PCIe glue layer including + the host controller. +- resets: A phandle to the reset line for PCIe glue layer including + the host controller. +- interrupts: A list of interrupt specifiers. According to the + interrupt-names, appropriate interrupts are required. +- interrupt-names: Must include the following entries: + "dma" - DMA interrupt + "msi" - MSI interrupt + +Optional properties: +- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate + phys are required. +- phy-names: Must be "pcie-phy". + +Required sub-node: +- legacy-interrupt-controller: Specifies interrupt controller for legacy PCI + interrupts. + +Required properties for legacy-interrupt-controller: +- interrupt-controller: identifies the node as an interrupt controller. +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- interrupt-parent: Phandle to the parent interrupt controller. +- interrupts: An interrupt specifier for legacy interrupt. + +Example: + + pcie: pcie@66000000 { + compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; + status = "disabled"; + reg-names = "dbi", "link", "config"; + reg = <0x66000000 0x1000>, <0x66010000 0x10000>, + <0x2fff0000 0x10000>; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + num-lanes = <1>; + num-viewport = <1>; + bus-range = <0x0 0xff>; + device_type = "pci"; + ranges = + /* downstream I/O */ + <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000 + /* non-prefetchable memory */ + 0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>; + #interrupt-cells = <1>; + interrupt-names = "dma", "msi"; + interrupts = <0 224 4>, <0 225 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ + <0 0 0 2 &pcie_intc 1>, /* INTB */ + <0 0 0 3 &pcie_intc 2>, /* INTC */ + <0 0 0 4 &pcie_intc 3>; /* INTD */ + + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 226 4>; + }; + }; -- cgit v1.2.3 From a32ed90be22aa565cf623da5a211b4a968dec6e0 Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Wed, 19 Dec 2018 15:22:40 +0800 Subject: net-next: dt-binding: dwmac-mediatek: remove fine-tune property remove fine-tune property in device tree, modify the corresponding description in dt-binding. Signed-off-by: Biao Huang Signed-off-by: David S. Miller --- .../devicetree/bindings/net/mediatek-dwmac.txt | 31 ++++++++-------------- 1 file changed, 11 insertions(+), 20 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt index 4de479b4d44d..8a08621a5b54 100644 --- a/Documentation/devicetree/bindings/net/mediatek-dwmac.txt +++ b/Documentation/devicetree/bindings/net/mediatek-dwmac.txt @@ -22,33 +22,25 @@ Required properties: Optional properties: - mediatek,tx-delay-ps: TX clock delay macro value. Default is 0. - It should be defined for rgmii/rgmii-rxid/mii interface. + It should be defined for RGMII/MII interface. - mediatek,rx-delay-ps: RX clock delay macro value. Default is 0. - It should be defined for rgmii/rgmii-txid/mii/rmii interface. -Both delay properties need to be a multiple of 170 for fine-tune rgmii, -range 0~31*170. -Both delay properties need to be a multiple of 550 for coarse-tune rgmii, -range 0~31*550. -Both delay properties need to be a multiple of 550 for mii/rmii, -range 0~31*550. + It should be defined for RGMII/MII/RMII interface. +Both delay properties need to be a multiple of 170 for RGMII interface, +or will round down. Range 0~31*170. +Both delay properties need to be a multiple of 550 for MII/RMII interface, +or will round down. Range 0~31*550. -- mediatek,fine-tune: boolean property, if present indicates that fine delay - is selected for rgmii interface. - If present, tx-delay-ps/rx-delay-ps is 170+/-50ps per stage. - Else tx-delay-ps/rx-delay-ps of coarse delay macro is 0.55+/-0.2ns per stage. - This property do not apply to non-rgmii PHYs. - Only coarse-tune delay is supported for mii/rmii PHYs. -- mediatek,rmii-rxc: boolean property, if present indicates that the rmii +- mediatek,rmii-rxc: boolean property, if present indicates that the RMII reference clock, which is from external PHYs, is connected to RXC pin on MT2712 SoC. Otherwise, is connected to TXC pin. - mediatek,txc-inverse: boolean property, if present indicates that - 1. tx clock will be inversed in mii/rgmii case, + 1. tx clock will be inversed in MII/RGMII case, 2. tx clock inside MAC will be inversed relative to reference clock - which is from external PHYs in rmii case, and it rarely happen. + which is from external PHYs in RMII case, and it rarely happen. - mediatek,rxc-inverse: boolean property, if present indicates that - 1. rx clock will be inversed in mii/rgmii case. - 2. reference clock will be inversed when arrived at MAC in rmii case. + 1. rx clock will be inversed in MII/RGMII case. + 2. reference clock will be inversed when arrived at MAC in RMII case. - assigned-clocks: mac_main and ptp_ref clocks - assigned-clock-parents: parent clocks of the assigned clocks @@ -76,7 +68,6 @@ Example: mediatek,pericfg = <&pericfg>; mediatek,tx-delay-ps = <1530>; mediatek,rx-delay-ps = <1530>; - mediatek,fine-tune; mediatek,rmii-rxc; mediatek,txc-inverse; mediatek,rxc-inverse; -- cgit v1.2.3 From 2ea44ca1ffccf89cfb9e6755156843e278ec9645 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 20 Dec 2018 08:56:07 +0000 Subject: dt-bindings: fsl: scu: add rtc binding NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system controller, the system controller is in charge of system power, clock and secure RTC etc. management, Linux kernel has to communicate with system controller via MU (message unit) IPC to do RTC operation, this patch adds binding doc for i.MX system controller RTC driver. Signed-off-by: Anson Huang Reviewed-by: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 46d0af1f0872..0860346fc9eb 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -114,6 +114,12 @@ Required properties for Pinctrl sub nodes: [2] Documentation/devicetree/bindings/power/power_domain.txt [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt +RTC bindings based on SCU Message Protocol +------------------------------------------------------------ + +Required properties: +- compatible: should be "fsl,imx8qxp-sc-rtc"; + Example (imx8qxp): ------------- lsio_mu1: mailbox@5d1c0000 { @@ -169,6 +175,10 @@ firmware { }; ... }; + + rtc: rtc { + compatible = "fsl,imx8qxp-sc-rtc"; + }; }; }; -- cgit v1.2.3 From 5fac78aac91d89b4a04c1cbd92254f62935c2711 Mon Sep 17 00:00:00 2001 From: Govind Singh Date: Thu, 20 Dec 2018 14:24:10 +0200 Subject: dt: bindings: ath10k: add missing dt properties for WCN3990 wifi node Add missing optional properties in WCN3990 wifi node. Signed-off-by: Govind Singh Reviewed-by: Rob Herring Reviewed-by: Brian Norris Tested-by: Brian Norris Signed-off-by: Kalle Valo --- .../bindings/net/wireless/qcom,ath10k.txt | 57 +++++++++++++--------- 1 file changed, 35 insertions(+), 22 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt index 2196d1ab3c8c..51fcf93d743b 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt @@ -21,10 +21,22 @@ can be provided per device. SNOC based devices (i.e. wcn3990) uses compatible string "qcom,wcn3990-wifi". -Optional properties: - reg: Address and length of the register set for the device. - reg-names: Must include the list of following reg names, "membase" +- interrupts: reference to the list of 17 interrupt numbers for "qcom,ipq4019-wifi" + compatible target. + reference to the list of 12 interrupt numbers for "qcom,wcn3990-wifi" + compatible target. + Must contain interrupt-names property per entry for + "qcom,ath10k", "qcom,ipq4019-wifi" compatible targets. + +- interrupt-names: Must include the entries for MSI interrupt + names ("msi0" to "msi15") and legacy interrupt + name ("legacy") for "qcom,ath10k", "qcom,ipq4019-wifi" + compatible targets. + +Optional properties: - resets: Must contain an entry for each entry in reset-names. See ../reset/reseti.txt for details. - reset-names: Must include the list of following reset names, @@ -37,12 +49,9 @@ Optional properties: - clocks: List of clock specifiers, must contain an entry for each required entry in clock-names. - clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref", - "wifi_wcss_rtc". -- interrupts: List of interrupt lines. Must contain an entry - for each entry in the interrupt-names property. -- interrupt-names: Must include the entries for MSI interrupt - names ("msi0" to "msi15") and legacy interrupt - name ("legacy"), + "wifi_wcss_rtc" for "qcom,ipq4019-wifi" compatible target and + "cxo_ref_clk_pin" for "qcom,wcn3990-wifi" + compatible target. - qcom,msi_addr: MSI interrupt address. - qcom,msi_base: Base value to add before writing MSI data into MSI address register. @@ -55,7 +64,8 @@ Optional properties: - qcom,ath10k-pre-calibration-data : pre calibration data as an array, the length can vary between hw versions. - -supply: handle to the regulator device tree node - optional "supply-name" is "vdd-0.8-cx-mx". + optional "supply-name" are "vdd-0.8-cx-mx", + "vdd-1.8-xo", "vdd-1.3-rfa" and "vdd-3.3-ch0". - memory-region: Usage: optional Value type: @@ -138,21 +148,24 @@ wifi@18000000 { compatible = "qcom,wcn3990-wifi"; reg = <0x18800000 0x800000>; reg-names = "membase"; - clocks = <&clock_gcc clk_aggre2_noc_clk>; - clock-names = "smmu_aggre2_noc_clk" + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "cxo_ref_clk_pin"; interrupts = - <0 130 0 /* CE0 */ >, - <0 131 0 /* CE1 */ >, - <0 132 0 /* CE2 */ >, - <0 133 0 /* CE3 */ >, - <0 134 0 /* CE4 */ >, - <0 135 0 /* CE5 */ >, - <0 136 0 /* CE6 */ >, - <0 137 0 /* CE7 */ >, - <0 138 0 /* CE8 */ >, - <0 139 0 /* CE9 */ >, - <0 140 0 /* CE10 */ >, - <0 141 0 /* CE11 */ >; + , + , + , + , + , + , + , + , + , + , + , + ; vdd-0.8-cx-mx-supply = <&pm8998_l5>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; memory-region = <&wifi_msa_mem>; }; -- cgit v1.2.3 From a3542d0c73cec6a45bde512ea2b43666c05a8c54 Mon Sep 17 00:00:00 2001 From: Govind Singh Date: Thu, 20 Dec 2018 14:24:23 +0200 Subject: dt: bindings: ath10k: add bindings for wifi iommu node WCN3990 wifi module can optionally make use of the IOMMU. Add binding documentation for phandle to the IOMMU and the stream id of wifi iommu block. Signed-off-by: Govind Singh Reviewed-by: Rob Herring Reviewed-by: Brian Norris Tested-by: Brian Norris Signed-off-by: Kalle Valo --- Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt index 51fcf93d743b..09ae59470f64 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt @@ -71,6 +71,10 @@ Optional properties: Value type: Definition: reference to the reserved-memory for the msa region used by the wifi firmware running in Q6. +- iommus: + Usage: optional + Value type: + Definition: A list of phandle and IOMMU specifier pairs. Example (to supply the calibration data alone): @@ -168,4 +172,5 @@ wifi@18000000 { vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; memory-region = <&wifi_msa_mem>; + iommus = <&apps_smmu 0x0040 0x1>; }; -- cgit v1.2.3 From e5404969a335e25e3eb822649a7f40e9c5ba2446 Mon Sep 17 00:00:00 2001 From: Bhagavathi Perumal S Date: Thu, 20 Dec 2018 14:25:32 +0200 Subject: dt-bindings: net: ath10k: fix node name and device type in qcom ath10k example In qcom,ath10k documentation, ath10k is used as node name in the example of pci based device. Normally, node name should be class of device and not the model name, so fix it to node name "wifi". And remove the property device_type pci since only pci bridges should have this property. Signed-off-by: Bhagavathi Perumal S Reviewed-by: Rob Herring Signed-off-by: Kalle Valo --- Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt index 09ae59470f64..bd6b276d078e 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt @@ -88,9 +88,8 @@ pci { #address-cells = <3>; device_type = "pci"; - ath10k@0,0 { + wifi@0,0 { reg = <0 0 0 0 0>; - device_type = "pci"; qcom,ath10k-calibration-data = [ 01 02 03 ... ]; }; }; -- cgit v1.2.3 From f3f587995c5af69b92693c2f5d40e3448ab6113d Mon Sep 17 00:00:00 2001 From: Bhagavathi Perumal S Date: Thu, 20 Dec 2018 14:25:43 +0200 Subject: dt-bindings: net: ath10k: add new dt entry to identify external FEM This adds new dt entry ext-fem-name, it is used by ath10k driver to select correct timing parameters and configure it in target wifi hardware. The Front End Module(FEM) normally includes tx power amplifier(PA) and rx low noise amplifier(LNA). The default timing parameters like tx end to PA off timing values were fine tuned for internal FEM used in reference design. And these timing values can not be same if ODM modifies hardware design with different external FEM. This DT entry helps to choose correct timing values in driver if different external FEM hardware used. Signed-off-by: Bhagavathi Perumal S Reviewed-by: Rob Herring Signed-off-by: Kalle Valo --- Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt index bd6b276d078e..ae661e65354e 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt @@ -75,8 +75,14 @@ Optional properties: Usage: optional Value type: Definition: A list of phandle and IOMMU specifier pairs. +- ext-fem-name: + Usage: Optional + Value type: string + Definition: Name of external front end module used. Some valid FEM names + for example: "microsemi-lx5586", "sky85703-11" + and "sky85803" etc. -Example (to supply the calibration data alone): +Example (to supply PCI based wifi block details): In this example, the node is defined as child node of the PCI controller. @@ -91,6 +97,7 @@ pci { wifi@0,0 { reg = <0 0 0 0 0>; qcom,ath10k-calibration-data = [ 01 02 03 ... ]; + ext-fem-name = "microsemi-lx5586"; }; }; }; -- cgit v1.2.3 From 485773d3c5c7fa1462c0a6b36187922c2dcba914 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Mon, 3 Dec 2018 12:47:10 +0100 Subject: dt-bindings: mrvl,intc: fix a trivial typo s/whold/whole/. Signed-off-by: Lubomir Rintel Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt index 8b53273cb22f..608fee15a4cf 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt @@ -5,7 +5,7 @@ Required properties: "mrvl,mmp2-mux-intc" - reg : Address and length of the register set of the interrupt controller. If the interrupt controller is intc, address and length means the range - of the whold interrupt controller. If the interrupt controller is mux-intc, + of the whole interrupt controller. If the interrupt controller is mux-intc, address and length means one register. Since address of mux-intc is in the range of intc. mux-intc is secondary interrupt controller. - reg-names : Name of the register set of the interrupt controller. It's -- cgit v1.2.3 From 24ad02c48c69c37427cc3412f6597493091eca3c Mon Sep 17 00:00:00 2001 From: Andreas Klinger Date: Fri, 14 Dec 2018 20:48:25 +0100 Subject: gpio-omap.txt: add reg and interrupts properties Document properties reg and interrupts for OMAP GPIO controller bindings Also add unit address in node name of the example Signed-off-by: Andreas Klinger Acked-by: Linus Walleij Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/gpio/gpio-omap.txt | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-omap.txt b/Documentation/devicetree/bindings/gpio/gpio-omap.txt index 8d950522e7fa..e57b2cb28f6c 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-omap.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-omap.txt @@ -5,6 +5,8 @@ Required properties: - "ti,omap2-gpio" for OMAP2 controllers - "ti,omap3-gpio" for OMAP3 controllers - "ti,omap4-gpio" for OMAP4 controllers +- reg : Physical base address of the controller and length of memory mapped + region. - gpio-controller : Marks the device node as a GPIO controller. - #gpio-cells : Should be two. - first cell is the pin number @@ -18,6 +20,8 @@ Required properties: 2 = high-to-low edge triggered. 4 = active high level-sensitive. 8 = active low level-sensitive. +- interrupts : The interrupt the controller is rising as output when an + interrupt occures OMAP specific properties: - ti,hwmods: Name of the hwmod associated to the GPIO: @@ -29,11 +33,13 @@ OMAP specific properties: Example: -gpio4: gpio4 { +gpio0: gpio@44e07000 { compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio4"; + reg = <0x44e07000 0x1000>; + ti,hwmods = "gpio1"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + interrupts = <96>; }; -- cgit v1.2.3 From 6bd925a8b779b262b007d638171c80398cfbc217 Mon Sep 17 00:00:00 2001 From: "Andrei.Stefanescu@microchip.com" Date: Wed, 12 Dec 2018 11:57:11 +0000 Subject: dt-bindings: arm: atmel: describe SECUMOD usage as a GPIO controller This patch describes the Security Module's usage as a GPIO controller for its PIOBU pins. These pins have the special property of maintaining their voltage during suspend-to-mem. Signed-off-by: Andrei Stefanescu Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 4b96608ad692..14f319f694b7 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -158,14 +158,24 @@ Security Module (SECUMOD) The Security Module macrocell provides all necessary secure functions to avoid voltage, temperature, frequency and mechanical attacks on the chip. It also -embeds secure memories that can be scrambled +embeds secure memories that can be scrambled. + +The Security Module also offers the PIOBU pins which can be used as GPIO pins. +Note that they maintain their voltage during Backup/Self-refresh. required properties: - compatible: Should be "atmel,-secumod", "syscon". can be "sama5d2". - reg: Should contain registers location and length +- gpio-controller: Marks the port as GPIO controller. +- #gpio-cells: There are 2. The pin number is the + first, the second represents additional + parameters such as GPIO_ACTIVE_HIGH/LOW. + secumod@fc040000 { compatible = "atmel,sama5d2-secumod", "syscon"; reg = <0xfc040000 0x100>; + gpio-controller; + #gpio-cells = <2>; }; -- cgit v1.2.3 From b766470b876409b9d821c5773a08a90f8cc50c76 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 17 Dec 2018 14:16:26 +0100 Subject: dt-bindings: pinctrl: sunxi: Add supply properties The pinctrl node can have multiple regulators for each of its GPIO banks. Add the property descriptions. Signed-off-by: Maxime Ripard Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index a7f713344867..cf96b7c20e4d 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -44,6 +44,19 @@ Note: For backward compatibility reasons, the hosc and losc clocks are only required if you need to use the optional input-debounce property. Any new device tree should set them. +Each pin bank, depending on the SoC, can have an associated regulator: + +- vcc-pa-supply: for the A10, A20, A31, A31s, A80 and R40 SoCs +- vcc-pb-supply: for the A31, A31s, A80 and V3s SoCs +- vcc-pc-supply: for the A10, A20, A31, A31s, A64, A80, H5, R40 and V3s SoCs +- vcc-pd-supply: for the A23, A31, A31s, A64, A80, A83t, H3, H5 and R40 SoCs +- vcc-pe-supply: for the A10, A20, A31, A31s, A64, A80, R40 and V3s SoCs +- vcc-pf-supply: for the A10, A20, A31, A31s, A80, R40 and V3s SoCs +- vcc-pg-supply: for the A10, A20, A31, A31s, A64, A80, H3, H5, R40 and V3s SoCs +- vcc-ph-supply: for the A31, A31s and A80 SoCs +- vcc-pl-supply: for the r-pinctrl of the A64, A80 and A83t SoCs +- vcc-pm-supply: for the r-pinctrl of the A31, A31s and A80 SoCs + Optional properties: - input-debounce: Array of debouncing periods in microseconds. One period per irq bank found in the controller. 0 if no setup required. -- cgit v1.2.3 From e4b194aa0bf522dad9ecf0568eb0fdd598a2713b Mon Sep 17 00:00:00 2001 From: Jan Kotas Date: Tue, 18 Dec 2018 16:10:41 +0000 Subject: dt-bindings: gpio: Add bindings for Cadence GPIO This patch adds a DT binding documentation for Cadence GPIO controller. Signed-off-by: Jan Kotas Reviewed-by: Rob Herring [Removed interrupt-parent] Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/cdns,gpio.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/cdns,gpio.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.txt b/Documentation/devicetree/bindings/gpio/cdns,gpio.txt new file mode 100644 index 000000000000..706ef00f5c64 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/cdns,gpio.txt @@ -0,0 +1,43 @@ +Cadence GPIO controller bindings + +Required properties: +- compatible: should be "cdns,gpio-r1p02". +- reg: the register base address and size. +- #gpio-cells: should be 2. + * first cell is the GPIO number. + * second cell specifies the GPIO flags, as defined in + . Only the GPIO_ACTIVE_HIGH + and GPIO_ACTIVE_LOW flags are supported. +- gpio-controller: marks the device as a GPIO controller. +- clocks: should contain one entry referencing the peripheral clock driving + the GPIO controller. + +Optional properties: +- ngpios: integer number of gpio lines supported by this controller, up to 32. +- interrupts: interrupt specifier for the controllers interrupt. +- interrupt-controller: marks the device as an interrupt controller. When + defined, interrupts, interrupt-parent and #interrupt-cells + are required. +- interrupt-cells: should be 2. + * first cell is the GPIO number you want to use as an IRQ source. + * second cell specifies the IRQ type, as defined in + . + Currently only level sensitive IRQs are supported. + + +Example: + gpio0: gpio-controller@fd060000 { + compatible = "cdns,gpio-r1p02"; + reg =<0xfd060000 0x1000>; + + clocks = <&gpio_clk>; + + interrupt-parent = <&gic>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; -- cgit v1.2.3 From 2ae80900f239484069569380e1fc4340fd6e0089 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 18 Dec 2018 16:57:44 +0100 Subject: dt-bindings: pinctrl: bcm4708-pinmux: rework binding to use syscon MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As pointed by Rob, CRU is a kind of block that can't be guaranteed to have everything exposed as subnodes. It's a set of various registers that aren't tied to any single device. It could be described much more accurately as MFD (Multi-Function Device). Some hardware blocks may indeed want to access a register or two of the CRU which requires describing it as the "syscon". While at it replace exmple node name with the standard "pinctrl" (also pointed out by Rob). Signed-off-by: Rafał Miłecki Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt index 4fa9539070cb..8ab2d468dbdb 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt @@ -7,13 +7,15 @@ configure controller correctly. A list of pins varies across chipsets so few bindings are available. +Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon" +noce. + Required properties: - compatible: must be one of: "brcm,bcm4708-pinmux" "brcm,bcm4709-pinmux" "brcm,bcm53012-pinmux" -- reg: iomem address range of CRU (Central Resource Unit) pin registers -- reg-names: "cru_gpio_control" - the only needed & supported reg right now +- offset: offset of pin registers in the CRU block Functions and their groups available for all chipsets: - "spi": "spi_grp" @@ -37,16 +39,12 @@ Example: #size-cells = <1>; cru@100 { - compatible = "simple-bus"; + compatible = "syscon", "simple-mfd"; reg = <0x100 0x1a4>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - pin-controller@1c0 { + pinctrl { compatible = "brcm,bcm4708-pinmux"; - reg = <0x1c0 0x24>; - reg-names = "cru_gpio_control"; + offset = <0xc0>; spi-pins { function = "spi"; -- cgit v1.2.3 From da801ab56ad874897b0b255216767c983e665a4c Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 20 Dec 2018 15:44:31 +0100 Subject: pinctrl: ocelot: add MSCC Jaguar2 support Jaguar2 has the same register layout as Ocelot but it has 64 pins, meaning that there are 2 registers instead of one. Signed-off-by: Alexandre Belloni Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index 24a210e0c59a..32a8a8fa7805 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -2,7 +2,8 @@ Microsemi Ocelot pin controller Device Tree Bindings ---------------------------------------------------- Required properties: - - compatible : Should be "mscc,ocelot-pinctrl" + - compatible : Should be "mscc,ocelot-pinctrl" or + "mscc,jaguar2-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. -- cgit v1.2.3 From a6ee0c00a70b115e365d71eb5debcfb9de74dd1b Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Wed, 31 Oct 2018 14:57:36 +0800 Subject: clk: qoriq: add more compatibles strings Add more SoC compatible strings to support more chips. Signed-off-by: Yuantian Tang Reviewed-by: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Scott Wood --- Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 97f46adac85f..c655f28d5918 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -28,6 +28,12 @@ Required properties: * "fsl,p4080-clockgen" * "fsl,p5020-clockgen" * "fsl,p5040-clockgen" + * "fsl,t1023-clockgen" + * "fsl,t1024-clockgen" + * "fsl,t1040-clockgen" + * "fsl,t1042-clockgen" + * "fsl,t2080-clockgen" + * "fsl,t2081-clockgen" * "fsl,t4240-clockgen" * "fsl,b4420-clockgen" * "fsl,b4860-clockgen" -- cgit v1.2.3 From fed8b7e366e7c8f81e957ef91aa8f0a38e038c66 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 28 Nov 2018 10:54:12 +0100 Subject: dt-bindings: tegra186-hsp: Add shared mailboxes Shared mailboxes are a mechanism to transport data from one processor in the system to another. They are bidirectional links with both a producer and a consumer. Interrupts are used to let the consumer know when data was written to the mailbox by the producer, and to let the producer know when the consumer has read the data from the mailbox. These interrupts are mapped to one or more "shared interrupts". Typically each processor in the system owns one of these shared interrupts. Add documentation to the device tree bindings about how clients can use mailbox specifiers to request a specific shared mailbox and select which direction they drive. Also document how to specify the shared interrupts in addition to the existing doorbell interrupt. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Reviewed-by: Rob Herring Acked-by: Thierry Reding Signed-off-by: Thierry Reding Signed-off-by: Jassi Brar --- .../bindings/mailbox/nvidia,tegra186-hsp.txt | 30 ++++++++++++++++++---- 1 file changed, 25 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt index b99d25fc2f26..ff3eafc5a882 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt @@ -15,12 +15,15 @@ Required properties: Array of strings. one of: - "nvidia,tegra186-hsp" + - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp" - reg : Offset and length of the register set for the device. - interrupt-names Array of strings. Contains a list of names for the interrupts described by the interrupt property. May contain the following entries, in any order: - "doorbell" + - "sharedN", where 'N' is a number from zero up to the number of + external interrupts supported by the HSP instance minus one. Users of this binding MUST look up entries in the interrupt property by name, using this interrupt-names property to do so. - interrupts @@ -29,12 +32,29 @@ Required properties: in a matching order. - #mbox-cells : Should be 2. -The mbox specifier of the "mboxes" property in the client node should -contain two data. The first one should be the HSP type and the second -one should be the ID that the client is going to use. Those information -can be found in the following file. +The mbox specifier of the "mboxes" property in the client node should contain +two cells. The first cell determines the HSP type and the second cell is used +to identify the mailbox that the client is going to use. -- . +For doorbells, the second cell specifies the index of the doorbell to use. + +For shared mailboxes, the second cell is composed of two fields: +- bits 31..24: + A bit mask of flags that further specify how the shared mailbox will be + used. Valid flags are: + - bit 31: + Defines the direction of the mailbox. If set, the mailbox will be used + as a producer (i.e. used to send data). If cleared, the mailbox is the + consumer of data sent by a producer. + +- bits 23.. 0: + The index of the shared mailbox to use. The number of available mailboxes + may vary by instance of the HSP block and SoC generation. + +The following file contains definitions that can be used to construct mailbox +specifiers: + + Example: -- cgit v1.2.3 From 4d9c6e90166f1a4b0132e8d8520a2fcd6d081e6b Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Wed, 7 Nov 2018 15:10:36 +0800 Subject: dt-bindings: watchdog: update bindings for MT7629 SoC This updates dt-binding documentation for MT7629 SoC Signed-off-by: Ryder Lee Reviewed-by: Rob Herring Reviewed-by: Guenter Roeck Acked-by: Matthias Brugger Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 859dee167b91..8682d6a93e5b 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -8,6 +8,7 @@ Required properties: "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 + "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 - reg : Specifies base physical address and size of the registers. -- cgit v1.2.3 From 8d4d4f3267e1fcad56ca5aa4eabf72472e10965f Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 23 Nov 2018 09:44:37 +0100 Subject: dt-bindings: watchdog: Add Qualcomm PM8916 watchdog Document support for the Watchdog Timer (WDT) Controller in the Qualcomm PM8916 PMIC module. Signed-off-by: Loic Poulain Reviewed-by: Rob Herring Reviewed-by: Guenter Roeck Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- .../bindings/watchdog/qcom,pm8916-wdt.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/qcom,pm8916-wdt.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/qcom,pm8916-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom,pm8916-wdt.txt new file mode 100644 index 000000000000..6fb984f31982 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/qcom,pm8916-wdt.txt @@ -0,0 +1,28 @@ +QCOM PM8916 watchdog timer controller + +This pm8916 watchdog timer controller must be under pm8916-pon node. + +Required properties: +- compatible: should be "qcom,pm8916-wdt" + +Optional properties : +- interrupts : Watchdog pre-timeout (bark) interrupt. +- timeout-sec : Watchdog timeout value in seconds. + +Example: + + pm8916_0: pm8916@0 { + compatible = "qcom,pm8916", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + + pon@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x800>; + + watchdog { + compatible = "qcom,pm8916-wdt"; + interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>; + timeout-sec = <10>; + }; + }; + }; -- cgit v1.2.3 From 4535fa0576d2bb14060a7e80a710382414a93558 Mon Sep 17 00:00:00 2001 From: Andreas Brauchli Date: Thu, 13 Dec 2018 15:44:18 +0100 Subject: iio: chemical: sgp30: add device tree support Add device tree support for Sensirion SGP30/SGPC3 gas sensors. Signed-off-by: Andreas Brauchli Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/chemical/sensirion,sgp30.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/chemical/sensirion,sgp30.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/chemical/sensirion,sgp30.txt b/Documentation/devicetree/bindings/iio/chemical/sensirion,sgp30.txt new file mode 100644 index 000000000000..5844ed58173c --- /dev/null +++ b/Documentation/devicetree/bindings/iio/chemical/sensirion,sgp30.txt @@ -0,0 +1,15 @@ +* Sensirion SGP30/SGPC3 multi-pixel Gas Sensor + +Required properties: + + - compatible: must be one of + "sensirion,sgp30" + "sensirion,sgpc3" + - reg: the I2C address of the sensor + +Example: + +gas@58 { + compatible = "sensirion,sgp30"; + reg = <0x58>; +}; -- cgit v1.2.3 From e94b815524f83536415d7d59cc1833ad05934d97 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:20:15 +0000 Subject: dt-bindings: pwm: rcar: Add r8a774c0 support Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt index 7f31fe7e2093..fbd6a4f943ce 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt +++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt @@ -6,6 +6,7 @@ Required Properties: - "renesas,pwm-r8a7744": for RZ/G1N - "renesas,pwm-r8a7745": for RZ/G1E - "renesas,pwm-r8a774a1": for RZ/G2M + - "renesas,pwm-r8a774c0": for RZ/G2E - "renesas,pwm-r8a7778": for R-Car M1A - "renesas,pwm-r8a7779": for R-Car H1 - "renesas,pwm-r8a7790": for R-Car H2 -- cgit v1.2.3 From 6797f292e4f59211c1763de87a69c9a55fd9caef Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:18:53 +0000 Subject: dt-bindings: watchdog: renesas-wdt: Document r8a774c0 support RZ/G2E (R8A774C0) watchdog implementation is compatible with R-Car Gen3, therefore add relevant documentation. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Guenter Roeck Reviewed-by: Rob Herring Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/devicetree/bindings/watchdog/renesas-wdt.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt index a8ee29fd9ac8..ef2b97b72e08 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt @@ -9,6 +9,7 @@ Required properties: - "renesas,r8a7744-wdt" (RZ/G1N) - "renesas,r8a7745-wdt" (RZ/G1E) - "renesas,r8a774a1-wdt" (RZ/G2M) + - "renesas,r8a774c0-wdt" (RZ/G2E) - "renesas,r8a7790-wdt" (R-Car H2) - "renesas,r8a7791-wdt" (R-Car M2-W) - "renesas,r8a7792-wdt" (R-Car V2H) -- cgit v1.2.3 From 88cc9fc41c7318565bcf28a843b1e4e3f2acf894 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Tue, 18 Dec 2018 15:22:54 +0000 Subject: dt-bindings: arm: fsl-scu: add imx8qm pinctrl support Update binding doc to support imx8qm pinctrl. Cc: Rob Herring Cc: Stefan Agner Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Pengutronix Kernel Team Signed-off-by: Dong Aisheng Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 46d0af1f0872..831d5dfd24c8 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -96,13 +96,16 @@ Pinctrl bindings based on SCU Message Protocol This binding uses the i.MX common pinctrl binding[3]. Required properties: -- compatible: Should be "fsl,imx8qxp-iomuxc". +- compatible: Should be one of: + "fsl,imx8qm-iomuxc", + "fsl,imx8qxp-iomuxc". Required properties for Pinctrl sub nodes: - fsl,pins: Each entry consists of 3 integers which represents the mux and config setting for one pin. The first 2 integers are specified using a PIN_FUNC_ID macro, which can be found in + , . The last integer CONFIG is the pad setting value like pull-up on this pin. -- cgit v1.2.3 From 1def98f69807518e26dcb0ac70142dcbbd953dc6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 18 Dec 2018 20:32:28 +0530 Subject: dt-bindings: Add RDA Micro vendor prefix MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add vendor prefix for RDA Micro which now merged into Unisoc Communications Inc. Signed-off-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Acked-by: Arnd Bergmann Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 4b1a2a8fcc16..37826fac7684 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -320,6 +320,7 @@ ralink Mediatek/Ralink Technology Corp. ramtron Ramtron International raspberrypi Raspberry Pi Foundation raydium Raydium Semiconductor Corp. +rda Unisoc Communications, Inc. realtek Realtek Semiconductor Corp. renesas Renesas Electronics Corporation richtek Richtek Technology Corporation -- cgit v1.2.3 From 56f73e4bc145730c94894d5b5c557f19b89e073a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 18 Dec 2018 20:32:29 +0530 Subject: dt-bindings: arm: Document RDA8810PL and reference boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add bindings for RDA Micro RDA8810PL SoC and below reference boards: 1. Orange Pi 2G-IoT - http://www.orangepi.org/OrangePi2GIOT/ 2. Orange Pi i96 - https://www.96boards.org/product/orangepi-i96/ Cc: zhao_steven@263.net Signed-off-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Acked-by: Arnd Bergmann Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/arm/rda.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/rda.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rda.txt b/Documentation/devicetree/bindings/arm/rda.txt new file mode 100644 index 000000000000..43c80762c428 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rda.txt @@ -0,0 +1,17 @@ +RDA Micro platforms device tree bindings +---------------------------------------- + +RDA8810PL SoC +============= + +Required root node properties: + + - compatible : must contain "rda,8810pl" + + +Boards: + +Root node property compatible must contain, depending on board: + + - Orange Pi 2G-IoT: "xunlong,orangepi-2g-iot" + - Orange Pi i96: "xunlong,orangepi-i96" -- cgit v1.2.3 From 804584a61ca0d4547965630d5a433ad1c39e0b27 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 18 Dec 2018 20:32:35 +0530 Subject: dt-bindings: serial: Document RDA Micro UART MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an initial binding for the UART in RDA Micro RDA8810PL SoC. Signed-off-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Acked-by: Arnd Bergmann Signed-off-by: Olof Johansson --- .../devicetree/bindings/serial/rda,8810pl-uart.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/rda,8810pl-uart.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/rda,8810pl-uart.txt b/Documentation/devicetree/bindings/serial/rda,8810pl-uart.txt new file mode 100644 index 000000000000..a08df97a69e6 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/rda,8810pl-uart.txt @@ -0,0 +1,17 @@ +RDA Micro UART + +Required properties: +- compatible : "rda,8810pl-uart" for RDA8810PL SoCs. +- reg : Offset and length of the register set for the device. +- interrupts : Should contain UART interrupt. +- clocks : Phandle to the input clock. + + +Example: + + uart2: serial@20a90000 { + compatible = "rda,8810pl-uart"; + reg = <0x20a90000 0x1000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>; + }; -- cgit v1.2.3 From 24f1c13fa5f1599c373c53783f74de8a639f7999 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 7 Nov 2018 14:35:00 +0100 Subject: dt-bindings: thermal: rcar-gen3-thermal: All variants use 3 interrupts RZ/G2M also has 3 interrupts routed to the TSC, but the list was not updated to reflect this. Just drop the list, as this is the case for this TSC variant in all R-Car Gen3 and RZ/G2 SoCs. Fixes: be6af481f3b2d508 ("dt-bindings: thermal: rcar-gen3-thermal: Add r8a774a1 support") Signed-off-by: Geert Uytterhoeven Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Signed-off-by: Eduardo Valentin --- Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt index ad9a435afef4..b6ab60f6abbf 100644 --- a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt @@ -21,8 +21,7 @@ Required properties: Optional properties: -- interrupts : interrupts routed to the TSC (3 for H3, M3-W, M3-N, - and V3H) +- interrupts : interrupts routed to the TSC (must be 3). - power-domain : Must contain a reference to the power domain. This property is mandatory if the thermal sensor instance is part of a controllable power domain. -- cgit v1.2.3 From 199bc54b4a1f3848a62ccb1fa22e9c43c352b8fa Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 23 Nov 2018 13:18:37 +0100 Subject: dt-bindings: thermal: tegra-bpmp: Add Tegra194 support The thermal controller implementation on Tegra194 is very similar to the implementation on Tegra186. Add a compatible string for the new generation. Signed-off-by: Thierry Reding Signed-off-by: Eduardo Valentin --- .../devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt index 276387dd6815..e17c07be270b 100644 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt @@ -15,7 +15,8 @@ Required properties: - compatible: Array of strings. One of: - - "nvidia,tegra186-bpmp-thermal". + - "nvidia,tegra186-bpmp-thermal" + - "nvidia,tegra194-bpmp-thermal" - #thermal-sensor-cells: Cell for sensor index. Single-cell integer. Must be <1>. -- cgit v1.2.3 From 1bc7523817215f94d8597f4daccb17a394a5703a Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 12 Dec 2018 10:36:42 +0100 Subject: dt-bindings: ap806: document the thermal interrupt capabilities The thermal IP can produce interrupts on overheat situation. Describe them. Signed-off-by: Miquel Raynal Signed-off-by: Eduardo Valentin --- .../devicetree/bindings/arm/marvell/ap806-system-controller.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt index 3fd21bb7cb37..7b8b8eb0191f 100644 --- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt @@ -114,12 +114,17 @@ Documentation/devicetree/bindings/thermal/thermal.txt The thermal IP can probe the temperature all around the processor. It may feature several channels, each of them wired to one sensor. +It is possible to setup an overheat interrupt by giving at least one +critical point to any subnode of the thermal-zone node. + Required properties: - compatible: must be one of: * marvell,armada-ap806-thermal - reg: register range associated with the thermal functions. Optional properties: +- interrupts: overheat interrupt handle. Should point to line 18 of the + SEI irqchip. See interrupt-controller/interrupts.txt - #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer to this IP and represents the channel ID. There is one sensor per channel. O refers to the thermal IP internal channel, while positive @@ -133,6 +138,8 @@ ap_syscon1: system-controller@6f8000 { ap_thermal: thermal-sensor@80 { compatible = "marvell,armada-ap806-thermal"; reg = <0x80 0x10>; + interrupt-parent = <&sei>; + interrupts = <18>; #thermal-sensor-cells = <1>; }; }; -- cgit v1.2.3 From bf9ff83f93baf4f404b7e3a90037604f86bea854 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 12 Dec 2018 10:36:43 +0100 Subject: dt-bindings: cp110: document the thermal interrupt capabilities The thermal IP can produce interrupts on overheat situation. Describe them. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Signed-off-by: Eduardo Valentin --- .../devicetree/bindings/arm/marvell/cp110-system-controller.txt | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt index 81ce742d2760..4db4119a6d19 100644 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt @@ -199,6 +199,9 @@ Thermal: The thermal IP can probe the temperature all around the processor. It may feature several channels, each of them wired to one sensor. +It is possible to setup an overheat interrupt by giving at least one +critical point to any subnode of the thermal-zone node. + For common binding part and usage, refer to Documentation/devicetree/bindings/thermal/thermal.txt @@ -208,6 +211,11 @@ Required properties: - reg: register range associated with the thermal functions. Optional properties: +- interrupts-extended: overheat interrupt handle. Should point to + a line of the ICU-SEI irqchip (116 is what is usually used by the + firmware). The ICU-SEI will redirect towards interrupt line #37 of the + AP SEI which is shared across all CPs. + See interrupt-controller/interrupts.txt - #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer to this IP and represents the channel ID. There is one sensor per channel. O refers to the thermal IP internal channel. @@ -220,6 +228,7 @@ CP110_LABEL(syscon1): system-controller@6f8000 { CP110_LABEL(thermal): thermal-sensor@70 { compatible = "marvell,armada-cp110-thermal"; reg = <0x70 0x10>; + interrupts-extended = <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <1>; }; }; -- cgit v1.2.3 From 69f8f55185ff2405366b1b193d3d2fea16589e54 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:19:48 +0000 Subject: dt-bindings: thermal: rcar-thermal: add R8A774C0 support Document RZ/G2E SoC (a.k.a. r8a774c0) bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Eduardo Valentin --- Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt index 73e1613d2cb0..a679fb4160d8 100644 --- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt @@ -4,11 +4,12 @@ Required properties: - compatible : "renesas,thermal-", "renesas,rcar-gen2-thermal" (with thermal-zone) or "renesas,rcar-thermal" (without thermal-zone) as - fallback except R-Car V3M/D3. + fallback except R-Car V3M/D3 and RZ/G2E. Examples with soctypes are: - "renesas,thermal-r8a73a4" (R-Mobile APE6) - "renesas,thermal-r8a7743" (RZ/G1M) - "renesas,thermal-r8a7744" (RZ/G1N) + - "renesas,thermal-r8a774c0" (RZ/G2E) - "renesas,thermal-r8a7779" (R-Car H1) - "renesas,thermal-r8a7790" (R-Car H2) - "renesas,thermal-r8a7791" (R-Car M2-W) @@ -23,7 +24,7 @@ Required properties: Option properties: - interrupts : If present should contain 3 interrupts for - R-Car V3M/D3 or 1 interrupt otherwise. + R-Car V3M/D3 and RZ/G2E or 1 interrupt otherwise. Example (non interrupt support): -- cgit v1.2.3 From 6471a52deeea8bba8163a1f8c7aa309d4e287eb1 Mon Sep 17 00:00:00 2001 From: Yoshihiro Kaneko Date: Mon, 17 Dec 2018 23:50:20 +0900 Subject: dt-bindings: thermal: rcar-thermal: add R8A77990 support Document the R-Car E3 (R8A77990) SoC bindings. Signed-off-by: Yoshihiro Kaneko Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Tested-by: Simon Horman Signed-off-by: Eduardo Valentin --- Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt index a679fb4160d8..196112d23b1e 100644 --- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt @@ -4,7 +4,7 @@ Required properties: - compatible : "renesas,thermal-", "renesas,rcar-gen2-thermal" (with thermal-zone) or "renesas,rcar-thermal" (without thermal-zone) as - fallback except R-Car V3M/D3 and RZ/G2E. + fallback except R-Car V3M/E3/D3 and RZ/G2E. Examples with soctypes are: - "renesas,thermal-r8a73a4" (R-Mobile APE6) - "renesas,thermal-r8a7743" (RZ/G1M) @@ -16,6 +16,7 @@ Required properties: - "renesas,thermal-r8a7792" (R-Car V2H) - "renesas,thermal-r8a7793" (R-Car M2-N) - "renesas,thermal-r8a77970" (R-Car V3M) + - "renesas,thermal-r8a77990" (R-Car E3) - "renesas,thermal-r8a77995" (R-Car D3) - reg : Address range of the thermal registers. The 1st reg will be recognized as common register @@ -24,7 +25,7 @@ Required properties: Option properties: - interrupts : If present should contain 3 interrupts for - R-Car V3M/D3 and RZ/G2E or 1 interrupt otherwise. + R-Car V3M/E3/D3 and RZ/G2E or 1 interrupt otherwise. Example (non interrupt support): -- cgit v1.2.3 From 0ddb46080a465fad99cff838682744f1f4848a4b Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Thu, 20 Dec 2018 10:37:08 +0300 Subject: ASoC: cs4341: Add DT bindings documentation for CS4341 DAC This patch adds DT bindings documentation for Cirrus Logic CS4341 DAC. Signed-off-by: Alexander Shiyan Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/cs4341.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/cs4341.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/cs4341.txt b/Documentation/devicetree/bindings/sound/cs4341.txt new file mode 100644 index 000000000000..12b4aa8ef0db --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs4341.txt @@ -0,0 +1,22 @@ +Cirrus Logic CS4341 audio DAC + +This device supports both I2C and SPI (configured with pin strapping +on the board). + +Required properties: + - compatible: "cirrus,cs4341a" + - reg : the I2C address of the device for I2C, the chip select + number for SPI. + +For required properties on I2C-bus, please consult +Documentation/devicetree/bindings/i2c/i2c.txt +For required properties on SPI-bus, please consult +Documentation/devicetree/bindings/spi/spi-bus.txt + +Example: + codec: cs4341@0 { + #sound-dai-cells = <0>; + compatible = "cirrus,cs4341a"; + reg = <0>; + spi-max-frequency = <6000000>; + }; -- cgit v1.2.3 From e4f4fdfc57d9c846862ea6109e356b3a4542df5b Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 18 Dec 2018 11:50:27 +0900 Subject: ASoC: audio-graph-scu-card: remove audio-graph-scu-card on Doc It is already merged into audio-graph-card. audio-graph-scu-card is no longer needed. Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- .../bindings/sound/audio-graph-scu-card.txt | 123 --------------------- 1 file changed, 123 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt b/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt deleted file mode 100644 index 62d42768a00b..000000000000 --- a/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt +++ /dev/null @@ -1,123 +0,0 @@ -Audio-Graph-SCU-Card: - -Audio-Graph-SCU-Card is "Audio-Graph-Card" + "ALSA DPCM". - -It is based on common bindings for device graphs. -see ${LINUX}/Documentation/devicetree/bindings/graph.txt - -Basically, Audio-Graph-SCU-Card property is same as -Simple-Card / Simple-SCU-Card / Audio-Graph-Card. -see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt - ${LINUX}/Documentation/devicetree/bindings/sound/simple-scu-card.txt - ${LINUX}/Documentation/devicetree/bindings/sound/audio-graph-card.txt - -Below are same as Simple-Card / Audio-Graph-Card. - -- label -- dai-format -- frame-master -- bitclock-master -- bitclock-inversion -- frame-inversion -- dai-tdm-slot-num -- dai-tdm-slot-width -- clocks / system-clock-frequency - -Below are same as Simple-SCU-Card. - -- convert-rate -- convert-channels -- prefix -- routing - -Required properties: - -- compatible : "audio-graph-scu-card"; -- dais : list of CPU DAI port{s} - -Example 1. Sampling Rate Conversion - - sound_card { - compatible = "audio-graph-scu-card"; - - label = "sound-card"; - prefix = "codec"; - routing = "codec Playback", "DAI0 Playback", - "DAI0 Capture", "codec Capture"; - convert-rate = <48000>; - - dais = <&cpu_port>; - }; - - audio-codec { - ... - - port { - codec_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint>; - }; - }; - }; - - dai-controller { - ... - cpu_port: port { - cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - - dai-format = "left_j"; - ... - }; - }; - }; - -Example 2. 2 CPU 1 Codec (Mixing) - - sound_card { - compatible = "audio-graph-scu-card"; - - label = "sound-card"; - routing = "codec Playback", "DAI0 Playback", - "codec Playback", "DAI1 Playback", - "DAI0 Capture", "codec Capture"; - - dais = <&cpu_port0 - &cpu_port1>; - }; - - audio-codec { - ... - - audio-graph-card,prefix = "codec"; - audio-graph-card,convert-rate = <48000>; - port { - codec_endpoint0: endpoint { - remote-endpoint = <&cpu_endpoint0>; - }; - codec_endpoint1: endpoint { - remote-endpoint = <&cpu_endpoint1>; - }; - }; - }; - - dai-controller { - ... - ports { - cpu_port0: port { - cpu_endpoint0: endpoint { - remote-endpoint = <&codec_endpoint0>; - - dai-format = "left_j"; - ... - }; - }; - cpu_port1: port { - cpu_endpoint1: endpoint { - remote-endpoint = <&codec_endpoint1>; - - dai-format = "left_j"; - ... - }; - }; - }; - }; -- cgit v1.2.3 From bb93487b85012b2232149888d260f935e4da680d Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 18 Dec 2018 11:50:37 +0900 Subject: ASoC: simple-scu-card: remove simple-scu-card on Doc It is already merged into simple-card. simple-scu-card is no longer needed. Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/simple-scu-card.txt | 94 ---------------------- 1 file changed, 94 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/simple-scu-card.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/simple-scu-card.txt b/Documentation/devicetree/bindings/sound/simple-scu-card.txt deleted file mode 100644 index 3a2f71616cda..000000000000 --- a/Documentation/devicetree/bindings/sound/simple-scu-card.txt +++ /dev/null @@ -1,94 +0,0 @@ -ASoC Simple SCU Sound Card - -Simple SCU Sound Card is "Simple Sound Card" + "ALSA DPCM". -For example, you can use this driver if you want to exchange sampling rate convert, -Mixing, etc... - -Required properties: - -- compatible : "simple-scu-audio-card" - "renesas,rsrc-card" -Optional properties: - -- simple-audio-card,name : see simple-audio-card.txt -- simple-audio-card,cpu : see simple-audio-card.txt -- simple-audio-card,codec : see simple-audio-card.txt - -Optional subnode properties: - -- simple-audio-card,format : see simple-audio-card.txt -- simple-audio-card,frame-master : see simple-audio-card.txt -- simple-audio-card,bitclock-master : see simple-audio-card.txt -- simple-audio-card,bitclock-inversion : see simple-audio-card.txt -- simple-audio-card,frame-inversion : see simple-audio-card.txt -- simple-audio-card,convert-rate : platform specified sampling rate convert -- simple-audio-card,convert-channels : platform specified converted channel size (2 - 8 ch) -- simple-audio-card,prefix : see routing -- simple-audio-card,widgets : Please refer to widgets.txt. -- simple-audio-card,routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources. - use audio-prefix if some components is using same sink/sources naming. - it can be used if compatible was "renesas,rsrc-card"; - -Required CPU/CODEC subnodes properties: - -- sound-dai : see simple-audio-card.txt - -Optional CPU/CODEC subnodes properties: - -- clocks / system-clock-frequency : see simple-audio-card.txt - -Example 1. Sampling Rate Conversion - -sound { - compatible = "simple-scu-audio-card"; - - simple-audio-card,name = "rsnd-ak4643"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - simple-audio-card,convert-rate = <48000>; - - simple-audio-card,prefix = "ak4642"; - simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback", - "DAI0 Capture", "ak4642 Capture"; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - system-clock-frequency = <11289600>; - }; -}; - -Example 2. 2 CPU 1 Codec (Mixing) - -sound { - compatible = "simple-scu-audio-card"; - - simple-audio-card,name = "rsnd-ak4643"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&dpcmcpu>; - simple-audio-card,frame-master = <&dpcmcpu>; - - simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback", - "ak4642 Playback", "DAI1 Playback"; - - dpcmcpu: cpu@0 { - sound-dai = <&rcar_sound 0>; - }; - - cpu@1 { - sound-dai = <&rcar_sound 1>; - }; - - codec { - prefix = "ak4642"; - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; -}; -- cgit v1.2.3 From e3e12ec09a18ad779b637f4a006a908cb6045aa7 Mon Sep 17 00:00:00 2001 From: Maruthi Srinivas Bayyavarapu Date: Fri, 21 Dec 2018 14:27:27 +0530 Subject: dt-bindings: ASoC: xlnx, audio-formatter: Document audio formatter bindings Added documentation for audio formatter IP core DT bindings. Signed-off-by: Maruthi Srinivas Bayyavarapu Signed-off-by: Mark Brown --- .../bindings/sound/xlnx,audio-formatter.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt b/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt new file mode 100644 index 000000000000..cbc93c8f4963 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt @@ -0,0 +1,29 @@ +Device-Tree bindings for Xilinx PL audio formatter + +The IP core supports DMA, data formatting(AES<->PCM conversion) +of audio samples. + +Required properties: + - compatible: "xlnx,audio-formatter-1.0" + - interrupt-names: Names specified to list of interrupts in same + order mentioned under "interrupts". + List of supported interrupt names are: + "irq_mm2s" : interrupt from MM2S block + "irq_s2mm" : interrupt from S2MM block + - interrupts-parent: Phandle for interrupt controller. + - interrupts: List of Interrupt numbers. + - reg: Base address and size of the IP core instance. + - clock-names: List of input clocks. + Required elements: "s_axi_lite_aclk", "aud_mclk" + - clocks: Input clock specifier. Refer to common clock bindings. + +Example: + audio_ss_0_audio_formatter_0: audio_formatter@80010000 { + compatible = "xlnx,audio-formatter-1.0"; + interrupt-names = "irq_mm2s", "irq_s2mm"; + interrupt-parent = <&gic>; + interrupts = <0 104 4>, <0 105 4>; + reg = <0x0 0x80010000 0x0 0x1000>; + clock-names = "s_axi_lite_aclk", "aud_mclk"; + clocks = <&clk 71>, <&clk_wiz_1 0>; + }; -- cgit v1.2.3 From c32759035ad246d3e4c65d23a07f9e6ba32caeaf Mon Sep 17 00:00:00 2001 From: Katsuhiro Suzuki Date: Fri, 21 Dec 2018 00:36:35 +0900 Subject: ASoC: rockchip: support ACODEC for rk3328 This patch adds support for audio CODEC core of rk3328. Rockchip does not publish detail specification of this core but driver source code is opened on their GitHub repository. https://github.com/rockchip-linux/kernel So I ported this code to linux-next and added some trivial fixes. Signed-off-by: Katsuhiro Suzuki Signed-off-by: Mark Brown --- .../bindings/sound/rockchip,rk3328-codec.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.txt new file mode 100644 index 000000000000..2469588c7ccb --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.txt @@ -0,0 +1,23 @@ +* Rockchip Rk3328 internal codec + +Required properties: + +- compatible: "rockchip,rk3328-codec" +- reg: physical base address of the controller and length of memory mapped + region. +- rockchip,grf: the phandle of the syscon node for GRF register. +- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names. +- clock-names: should be "pclk". +- spk-depop-time-ms: speak depop time msec. + +Example for rk3328 internal codec: + +codec: codec@ff410000 { + compatible = "rockchip,rk3328-codec"; + reg = <0x0 0xff410000 0x0 0x1000>; + rockchip,grf = <&grf>; + clocks = <&cru PCLK_ACODEC>; + clock-names = "pclk"; + spk-depop-time-ms = 100; + status = "disabled"; +}; -- cgit v1.2.3 From 78c0c25a8c08d76d12dd682de259f303baf25770 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Tue, 11 Dec 2018 09:04:45 +0100 Subject: dt-bindings: i2c: Add S700 support for Actions Semi Soc's Add s700 compatible string to Actions Semi SoC dt-bindings. Signed-off-by: Parthiban Nallathambi Reviewed-by: Rob Herring Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-owl.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-owl.txt b/Documentation/devicetree/bindings/i2c/i2c-owl.txt index b743fe444e9f..54c05dbdb2e4 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-owl.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-owl.txt @@ -2,7 +2,9 @@ Actions Semiconductor Owl I2C controller Required properties: -- compatible : Should be "actions,s900-i2c". +- compatible : Should be one of the following: + - "actions,s700-i2c" for S700 SoC + - "actions,s900-i2c" for S900 SoC - reg : Offset and length of the register set for the device. - #address-cells : Should be 1. - #size-cells : Should be 0. -- cgit v1.2.3 From 4664b94c98b4f9fdd3845da41d5c65288e59c66c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 3 Jan 2019 16:05:51 +0200 Subject: ASoC: davinci-mcasp: Document GPIO support McASP pins can be used as GPIO, add optional section to enable GPIO support for McASP. Signed-off-by: Peter Ujfalusi Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/davinci-mcasp-audio.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt index b279b6072bd5..a58f79f5345c 100644 --- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt +++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt @@ -45,6 +45,23 @@ Optional properties: - fck_parent : Should contain a valid clock name which will be used as parent for the McASP fck +Optional GPIO support: +If any McASP pin need to be used as GPIO then the McASP node must have: +... + gpio-controller + #gpio-cells = <2>; +... + +When requesting a GPIO, the first parameter is the PIN index in McASP_P* +registers. +For example to request the AXR2 pin of mcasp8: +function-gpios = <&mcasp8 2 0>; + +Or to request the ACLKR pin of mcasp8: +function-gpios = <&mcasp8 29 0>; + +For generic gpio information, please refer to bindings/gpio/gpio.txt + Example: mcasp0: mcasp0@1d00000 { -- cgit v1.2.3 From 6e33a125df66664a09cd518a2e1dd63b4ccddef8 Mon Sep 17 00:00:00 2001 From: Stefan Popa Date: Mon, 17 Dec 2018 14:23:40 +0200 Subject: dt-bindings: iio: adc: Add docs for AD7606 ADC Document support for AD7606 Analog to Digital Converter. Signed-off-by: Stefan Popa Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/adi,ad7606.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad7606.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.txt b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.txt new file mode 100644 index 000000000000..d7b6241ca881 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.txt @@ -0,0 +1,65 @@ +Analog Devices AD7606 Simultaneous Sampling ADC + +Required properties for the AD7606: + +- compatible: Must be one of + * "adi,ad7605-4" + * "adi,ad7606-8" + * "adi,ad7606-6" + * "adi,ad7606-4" +- reg: SPI chip select number for the device +- spi-max-frequency: Max SPI frequency to use + see: Documentation/devicetree/bindings/spi/spi-bus.txt +- spi-cpha: See Documentation/devicetree/bindings/spi/spi-bus.txt +- avcc-supply: phandle to the Avcc power supply +- interrupts: IRQ line for the ADC + see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt +- adi,conversion-start-gpios: must be the device tree identifier of the CONVST pin. + This logic input is used to initiate conversions on the analog + input channels. As the line is active high, it should be marked + GPIO_ACTIVE_HIGH. + +Optional properties: + +- reset-gpios: must be the device tree identifier of the RESET pin. If specified, + it will be asserted during driver probe. As the line is active high, + it should be marked GPIO_ACTIVE_HIGH. +- standby-gpios: must be the device tree identifier of the STBY pin. This pin is used + to place the AD7606 into one of two power-down modes, Standby mode or + Shutdown mode. As the line is active low, it should be marked + GPIO_ACTIVE_LOW. +- adi,first-data-gpios: must be the device tree identifier of the FRSTDATA pin. + The FRSTDATA output indicates when the first channel, V1, is + being read back on either the parallel, byte or serial interface. + As the line is active high, it should be marked GPIO_ACTIVE_HIGH. +- adi,range-gpios: must be the device tree identifier of the RANGE pin. The polarity on + this pin determines the input range of the analog input channels. If + this pin is tied to a logic high, the analog input range is ±10V for + all channels. If this pin is tied to a logic low, the analog input range + is ±5V for all channels. As the line is active high, it should be marked + GPIO_ACTIVE_HIGH. +- adi,oversampling-ratio-gpios: must be the device tree identifier of the over-sampling + mode pins. As the line is active high, it should be marked + GPIO_ACTIVE_HIGH. + +Example: + + adc@0 { + compatible = "adi,ad7606-8"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + + avcc-supply = <&adc_vref>; + + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; + + adi,conversion-start-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; + adi,first-data-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + adi,oversampling-ratio-gpios = <&gpio 18 GPIO_ACTIVE_HIGH + &gpio 23 GPIO_ACTIVE_HIGH + &gpio 26 GPIO_ACTIVE_HIGH>; + standby-gpios = <&gpio 24 GPIO_ACTIVE_LOW>; + }; -- cgit v1.2.3 From a4b475b1abbb41b71d62e088a1ffd2b86e5e0aa0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 27 Dec 2018 22:50:19 +0100 Subject: dt-bindings: iio: adc: meson-saradc: update temperature sensor support Meson8b and Meson8m2 use a 5-bit wide TSC (temperature sensor coefficient). The SAR ADC registers however can only store (the lower) 4 bits. The fifth (upper-most) bit is stored inside the MESON_HHI_DPLL_TOP_0[9] register from the HHI register area. This adds a syscon property to the HHI register area so a driver can fetch the HHI register map and store the fifth TSC bit in there. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt index 325090e43ce6..75c775954102 100644 --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt @@ -23,6 +23,10 @@ Required properties: - #io-channel-cells: must be 1, see ../iio-bindings.txt Optional properties: +- amlogic,hhi-sysctrl: phandle to the syscon which contains the 5th bit + of the TSC (temperature sensor coefficient) on + Meson8b and Meson8m2 (which used to calibrate the + temperature sensor) - nvmem-cells: phandle to the temperature_calib eFuse cells - nvmem-cell-names: if present (to enable the temperature sensor calibration) this must contain "temperature_calib" -- cgit v1.2.3 From 9e2b9d3490a684415fc7cc062dfdb2783045b544 Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Tue, 30 Oct 2018 10:36:04 +0800 Subject: dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings Document the devicetree bindings for NXP Layerscape qDMA controller which could be found on NXP QorIQ Layerscape SoCs. Signed-off-by: Wen He Signed-off-by: Peng Ma Reviewed-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/fsl-qdma.txt | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt new file mode 100644 index 000000000000..6a0ff9059e72 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt @@ -0,0 +1,57 @@ +NXP Layerscape SoC qDMA Controller +================================== + +This device follows the generic DMA bindings defined in dma/dma.txt. + +Required properties: + +- compatible: Must be one of + "fsl,ls1021a-qdma": for LS1021A Board + "fsl,ls1043a-qdma": for ls1043A Board + "fsl,ls1046a-qdma": for ls1046A Board +- reg: Should contain the register's base address and length. +- interrupts: Should contain a reference to the interrupt used by this + device. +- interrupt-names: Should contain interrupt names: + "qdma-queue0": the block0 interrupt + "qdma-queue1": the block1 interrupt + "qdma-queue2": the block2 interrupt + "qdma-queue3": the block3 interrupt + "qdma-error": the error interrupt +- fsl,dma-queues: Should contain number of queues supported. +- dma-channels: Number of DMA channels supported +- block-number: the virtual block number +- block-offset: the offset of different virtual block +- status-sizes: status queue size of per virtual block +- queue-sizes: command queue size of per virtual block, the size number + based on queues + +Optional properties: + +- dma-channels: Number of DMA channels supported by the controller. +- big-endian: If present registers and hardware scatter/gather descriptors + of the qDMA are implemented in big endian mode, otherwise in little + mode. + +Examples: + + qdma: dma-controller@8390000 { + compatible = "fsl,ls1021a-qdma"; + reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ + <0x0 0x8389000 0x0 0x1000>, /* Status regs */ + <0x0 0x838a000 0x0 0x2000>; /* Block regs */ + interrupts = , + , + ; + interrupt-names = "qdma-error", + "qdma-queue0", "qdma-queue1"; + dma-channels = <8>; + block-number = <2>; + block-offset = <0x1000>; + fsl,dma-queues = <2>; + status-sizes = <64>; + queue-sizes = <64 64>; + big-endian; + }; + +DMA clients must use the format described in dma/dma.txt file. -- cgit v1.2.3 From 7df54dbeb055229f6689161aa90bf00bf4af077e Mon Sep 17 00:00:00 2001 From: Andrea Merello Date: Tue, 20 Nov 2018 16:31:47 +0100 Subject: dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property The width of the "length register" cannot be autodetected, and it is now specified with a DT property. Add documentation for it. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey Reviewed-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 174af2c45e77..2fce9fb4b270 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -41,6 +41,10 @@ Optional properties: - xlnx,include-sg: Tells configured for Scatter-mode in the hardware. Optional properties for AXI DMA: +- xlnx,sg-length-width: Should be set to the width in bits of the length + register as configured in h/w. Takes values {8...26}. If the property + is missing or invalid then the default value 23 is used. This is the + maximum value that is supported by all IP versions. - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. -- cgit v1.2.3 From 29b9ee4a0c0edf32667e2d95690f6ed810aad6ec Mon Sep 17 00:00:00 2001 From: Andrea Merello Date: Tue, 20 Nov 2018 16:31:50 +0100 Subject: dt-bindings: dmaengine: xilinx_dma: drop include-sg property This property is not needed anymore, because the driver now autodetects it. Delete references in documentation. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey Reviewed-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 3 --- 1 file changed, 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 2fce9fb4b270..93b6d961dd4f 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -37,9 +37,6 @@ Required properties: Required properties for VDMA: - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. -Optional properties: -- xlnx,include-sg: Tells configured for Scatter-mode in - the hardware. Optional properties for AXI DMA: - xlnx,sg-length-width: Should be set to the width in bits of the length register as configured in h/w. Takes values {8...26}. If the property -- cgit v1.2.3 From 2808cd5e798d22e3f25ddfaddcde9b507c840d1e Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Sat, 29 Dec 2018 00:23:01 +0530 Subject: dt-bindings: remoteproc: qcom: Add missing clocks for SDM845 Add missing clock bindings for Q6V5 MSS on SDM845 SoCs. Fixes: fb22022ff63d ("dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845") Reviewed-by: Rob Herring Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index 9ff5b0309417..d645c8db29fd 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -39,13 +39,21 @@ on the Qualcomm Hexagon core. - clocks: Usage: required Value type: - Definition: reference to the iface, bus and mem clocks to be held on - behalf of the booting of the Hexagon core + Definition: reference to the clocks that match clock-names - clock-names: Usage: required Value type: - Definition: must be "iface", "bus", "mem" + Definition: The clocks needed depend on the compatible string: + qcom,ipq8074-wcss-pil: + no clock names required + qcom,q6v5-pil: + qcom,msm8916-mss-pil: + qcom,msm8974-mss-pil: + must be "iface", "bus", "mem", "xo" + qcom,sdm845-mss-pil: + must be "iface", "bus", "mem", "xo", "gpll0_mss", + "snoc_axi", "mnoc_axi", "prng" - resets: Usage: required -- cgit v1.2.3 From 0f97dbbc1f3498f8e672aedffbec69b113490369 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Sat, 29 Dec 2018 00:23:02 +0530 Subject: dt-bindings: remoteproc: qcom: Add missing clocks for MSM8996 Add missing clock bindings for Q6V5 MSS on MSM8996 SoCs. Fixes: 9f058fa2efb1 ("remoteproc: qcom: Add support for mss remoteproc on msm8996") Reviewed-by: Rob Herring Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index d645c8db29fd..bba3d6be71c0 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -51,6 +51,9 @@ on the Qualcomm Hexagon core. qcom,msm8916-mss-pil: qcom,msm8974-mss-pil: must be "iface", "bus", "mem", "xo" + qcom,msm8996-mss-pil: + must be "iface", "bus", "mem", "xo", "gpll0_mss", + "snoc_axi", "mnoc_axi", "pnoc", "qdss" qcom,sdm845-mss-pil: must be "iface", "bus", "mem", "xo", "gpll0_mss", "snoc_axi", "mnoc_axi", "prng" -- cgit v1.2.3 From 688c4375b853759120169e220a0ef648ad9f0970 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Sat, 29 Dec 2018 00:23:04 +0530 Subject: dt-bindings: remoteproc: qcom: Fixup regulator dependencies Fixup regulator supply dependencies for Q6V5 MSS on MSM996 SoCs. Fixes: 9f058fa2efb1 ("remoteproc: qcom: Add support for mss remoteproc on msm8996") Reviewed-by: Rob Herring Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index bba3d6be71c0..9db371da4897 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -76,6 +76,19 @@ on the Qualcomm Hexagon core. must be "mss_restart", "pdc_reset" for the modem sub-system on SDM845 SoCs +For the compatible strings below the following supplies are required: + "qcom,q6v5-pil" + "qcom,msm8916-mss-pil", +- cx-supply: +- mx-supply: +- pll-supply: + Usage: required + Value type: + Definition: reference to the regulators to be held on behalf of the + booting of the Hexagon core + +For the compatible string below the following supplies are required: + "qcom,msm8974-mss-pil" - cx-supply: - mss-supply: - mx-supply: @@ -85,6 +98,14 @@ on the Qualcomm Hexagon core. Definition: reference to the regulators to be held on behalf of the booting of the Hexagon core +For the compatible string below the following supplies are required: + "qcom,msm8996-mss-pil" +- pll-supply: + Usage: required + Value type: + Definition: reference to the regulators to be held on behalf of the + booting of the Hexagon core + - qcom,smem-states: Usage: required Value type: -- cgit v1.2.3 From f2951bb0022526e2c8884e4c5dfc50087d799eb9 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Sat, 29 Dec 2018 00:23:06 +0530 Subject: dt-bindings: remoteproc: qcom: Add power-domain bindings for Q6V5 Add power-domain bindings for Q6V5 MSS on MSM8996 and SDM845 SoCs. Reviewed-by: Rob Herring Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index 9db371da4897..36e91c9d76e0 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -106,6 +106,25 @@ For the compatible string below the following supplies are required: Definition: reference to the regulators to be held on behalf of the booting of the Hexagon core +- power-domains: + Usage: required + Value type: + Definition: reference to power-domains that match power-domain-names + +- power-domain-names: + Usage: required + Value type: + Definition: The power-domains needed depend on the compatible string: + qcom,q6v5-pil: + qcom,ipq8074-wcss-pil: + qcom,msm8916-mss-pil: + qcom,msm8974-mss-pil: + no power-domain names required + qcom,msm8996-mss-pil: + must be "cx", "mx" + qcom,sdm845-mss-pil: + must be "cx", "mx", "mss", "load_state" + - qcom,smem-states: Usage: required Value type: -- cgit v1.2.3 From a5cb1ee8f241e6595ef1538b3572b98ee3fe6396 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 28 Dec 2018 10:18:18 +0530 Subject: dt-bindings: remoteproc: qcom: Add firmware bindings for Q6V5 Add optional "firmware-name" bindings for Q6V5 MSS and PAS based remoteprocs. For Q6V5 MSS/PAS the two/one relative firmware paths/path are to be listed respectively. Fallback to the default images for mba/modem for Q6V5 MSS or the default Hexagon image for Q6V5 PAS if the "firmware-name" binding is not present. Reviewed-by: Rob Herring Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt | 6 ++++++ Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 7 +++++++ 2 files changed, 13 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt index 9c0cff3a5ed8..60ee0f73071a 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt @@ -27,6 +27,12 @@ on the Qualcomm ADSP Hexagon core. Value type: Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack" +- firmware-name: + Usage: optional + Value type: + Definition: must list the relative firmware image path for the + Hexagon Core. + - clocks: Usage: required Value type: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index 36e91c9d76e0..401e49ebee39 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -36,6 +36,13 @@ on the Qualcomm Hexagon core. Value type: Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack" +- firmware-name: + Usage: optional + Value type: + Definition: must list the relative firmware image paths for mba and + modem. They are used for booting and authenticating the + Hexagon core. + - clocks: Usage: required Value type: -- cgit v1.2.3 From 12749350567c819d8a35a405743313bd869c95c0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 5 Dec 2018 11:44:19 -0800 Subject: dt-bindings: arm: Convert Renesas board/soc bindings to json-schema Convert Renesas SoC bindings to DT schema format using json-schema. v2.1 [Simon Horman] - rebased on renesas-devel-20181204-v4.20-rc5 + Added r8a7744 development platform and SoM + Correct RZ/G2E part number - Update MAINTAINERS Signed-off-by: Rob Herring Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/renesas.yaml | 228 +++++++++++++++++++++ Documentation/devicetree/bindings/arm/shmobile.txt | 155 -------------- 2 files changed, 228 insertions(+), 155 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/renesas.yaml delete mode 100644 Documentation/devicetree/bindings/arm/shmobile.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml new file mode 100644 index 000000000000..5e9d4864a600 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -0,0 +1,228 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/shmobile.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings + +maintainers: + - Geert Uytterhoeven + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Emma Mobile EV2 + items: + - enum: + - renesas,kzm9d # Kyoto Microcomputer Co. KZM-A9-Dual + - const: renesas,emev2 + + - description: RZ/A1H (R7S72100) + items: + - enum: + - renesas,genmai # Genmai (RTK772100BC00000BR) + - renesas,gr-peach # GR-Peach (X28A-M01-E/F) + - renesas,rskrza1 # RSKRZA1 (YR0K77210C000BE) + - const: renesas,r7s72100 + + - description: RZ/A2 (R7S9210) + items: + - const: renesas,r7s9210 + + - description: SH-Mobile AG5 (R8A73A00/SH73A0) + items: + - enum: + - renesas,kzm9g # Kyoto Microcomputer Co. KZM-A9-GT + - const: renesas,sh73a0 + + - description: R-Mobile APE6 (R8A73A40) + items: + - enum: + - renesas,ape6evm + - const: renesas,r8a73a4 + + - description: R-Mobile A1 (R8A77400) + items: + - enum: + - renesas,armadillo800eva # Atmark Techno Armadillo-800 EVA + - const: renesas,r8a7740 + + - description: RZ/G1H (R8A77420) + items: + - const: renesas,r8a7742 + + - description: RZ/G1M (R8A77430) + items: + - enum: + # iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven) + - iwave,g20d + - const: iwave,g20m + - const: renesas,r8a7743 + + - items: + - enum: + # iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) + - iwave,g20m + - renesas,sk-rzg1m # SK-RZG1M (YR8A77430S000BE) + - const: renesas,r8a7743 + + - description: RZ/G1N (R8A77440) + items: + - enum: + # iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven) + - iwave,g20d + - const: iwave,g20m + - const: renesas,r8a7744 + + - items: + - enum: + # iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven) + - iwave,g20m + - const: renesas,r8a7744 + + - description: RZ/G1E (R8A77450) + items: + - enum: + - iwave,g22m # iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM) + - renesas,sk-rzg1e # SK-RZG1E (YR8A77450S000BE) + - const: renesas,r8a7745 + + - description: iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) + items: + - const: iwave,g22d + - const: iwave,g22m + - const: renesas,r8a7745 + + - description: RZ/G1C (R8A77470) + items: + - enum: + - iwave,g23s #iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S) + - const: renesas,r8a77470 + + - description: RZ/G2M (R8A774A1) + items: + - const: renesas,r8a774a1 + + - description: RZ/G2E (R8A774C0) + items: + - const: renesas,r8a774c0 + + - description: R-Car M1A (R8A77781) + items: + - enum: + - renesas,bockw + - const: renesas,r8a7778 + + - description: R-Car H1 (R8A77790) + items: + - enum: + - renesas,marzen # Marzen (R0P7779A00010S) + - renesas,stout # Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) + - const: renesas,r8a7779 + + - description: R-Car H2 (R8A77900) + items: + - enum: + - renesas,lager # Lager (RTP0RC7790SEB00010S) + - const: renesas,r8a7790 + + - description: R-Car M2-W (R8A77910) + items: + - enum: + - renesas,henninger + - renesas,koelsch # Koelsch (RTP0RC7791SEB00010S) + - renesas,porter # Porter (M2-LCDP) + - const: renesas,r8a7791 + + - description: R-Car V2H (R8A77920) + items: + - enum: + - renesas,blanche # Blanche (RTP0RC7792SEB00010S) + - renesas,wheat # Wheat (RTP0RC7792ASKB0000JE) + - const: renesas,r8a7792 + + - description: R-Car M2-N (R8A77930) + items: + - enum: + - renesas,gose # Gose (RTP0RC7793SEB00010S) + - const: renesas,r8a7793 + + - description: R-Car E2 (R8A77940) + items: + - enum: + - renesas,alt # Alt (RTP0RC7794SEB00010S) + - renesas,silk # SILK (RTP0RC7794LCB00011S) + - const: renesas,r8a7794 + + - description: R-Car H3 (R8A77950) + items: + - enum: + # H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1)) + # H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0)) + - renesas,h3ulcb + - renesas,salvator-x # Salvator-X (RTP0RC7795SIPB0010S) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) + - const: renesas,r8a7795 + + - description: R-Car M3-W (R8A77960) + items: + - enum: + - renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0)) + - renesas,salvator-x # Salvator-X (RTP0RC7796SIPB0011S) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) + - const: renesas,r8a7796 + + - description: Kingfisher (SBEV-RCAR-KF-M03) + items: + - const: shimafuji,kingfisher + - enum: + - renesas,h3ulcb + - renesas,m3ulcb + - enum: + - renesas,r8a7795 + - renesas,r8a7796 + + - description: R-Car M3-N (R8A77965) + items: + - enum: + - renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1)) + - renesas,salvator-x # Salvator-X (RTP0RC7796SIPB0011S (M3-N)) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S) + - const: renesas,r8a77965 + + - description: R-Car V3M (R8A77970) + items: + - enum: + - renesas,eagle # Eagle (RTP0RC77970SEB0010S) + - renesas,v3msk # V3MSK (Y-ASK-RCAR-V3M-WS10) + - const: renesas,r8a77970 + + - description: R-Car V3H (R8A77980) + items: + - enum: + - renesas,condor # Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01) + - renesas,v3hsk # V3HSK (Y-ASK-RCAR-V3H-WS10) + - const: renesas,r8a77980 + + - description: R-Car E3 (R8A77990) + items: + - enum: + - renesas,ebisu # Ebisu (RTP0RC77990SEB0010S) + - const: renesas,r8a77990 + + - description: R-Car D3 (R8A77995) + items: + - enum: + - renesas,draak # Draak (RTP0RC77995SEB0010S) + - const: renesas,r8a77995 + + - description: RZ/N1D (R9A06G032) + items: + - enum: + - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) + - const: renesas,r9a06g032 + +... diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt deleted file mode 100644 index 7f91c2a8b54e..000000000000 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ /dev/null @@ -1,155 +0,0 @@ -Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings --------------------------------------------------------------------- - -SoCs: - - - Emma Mobile EV2 - compatible = "renesas,emev2" - - RZ/A1H (R7S72100) - compatible = "renesas,r7s72100" - - RZ/A2 (R7S9210) - compatible = "renesas,r7s9210" - - SH-Mobile AG5 (R8A73A00/SH73A0) - compatible = "renesas,sh73a0" - - R-Mobile APE6 (R8A73A40) - compatible = "renesas,r8a73a4" - - R-Mobile A1 (R8A77400) - compatible = "renesas,r8a7740" - - RZ/G1H (R8A77420) - compatible = "renesas,r8a7742" - - RZ/G1M (R8A77430) - compatible = "renesas,r8a7743" - - RZ/G1N (R8A77440) - compatible = "renesas,r8a7744" - - RZ/G1E (R8A77450) - compatible = "renesas,r8a7745" - - RZ/G1C (R8A77470) - compatible = "renesas,r8a77470" - - RZ/G2M (R8A774A1) - compatible = "renesas,r8a774a1" - - RZ/G2E (R8A774C0) - compatible = "renesas,r8a774c0" - - R-Car M1A (R8A77781) - compatible = "renesas,r8a7778" - - R-Car H1 (R8A77790) - compatible = "renesas,r8a7779" - - R-Car H2 (R8A77900) - compatible = "renesas,r8a7790" - - R-Car M2-W (R8A77910) - compatible = "renesas,r8a7791" - - R-Car V2H (R8A77920) - compatible = "renesas,r8a7792" - - R-Car M2-N (R8A77930) - compatible = "renesas,r8a7793" - - R-Car E2 (R8A77940) - compatible = "renesas,r8a7794" - - R-Car H3 (R8A77950) - compatible = "renesas,r8a7795" - - R-Car M3-W (R8A77960) - compatible = "renesas,r8a7796" - - R-Car M3-N (R8A77965) - compatible = "renesas,r8a77965" - - R-Car V3M (R8A77970) - compatible = "renesas,r8a77970" - - R-Car V3H (R8A77980) - compatible = "renesas,r8a77980" - - R-Car E3 (R8A77990) - compatible = "renesas,r8a77990" - - R-Car D3 (R8A77995) - compatible = "renesas,r8a77995" - - RZ/N1D (R9A06G032) - compatible = "renesas,r9a06g032" - -Boards: - - - Alt (RTP0RC7794SEB00010S) - compatible = "renesas,alt", "renesas,r8a7794" - - APE6-EVM - compatible = "renesas,ape6evm", "renesas,r8a73a4" - - Atmark Techno Armadillo-800 EVA - compatible = "renesas,armadillo800eva", "renesas,r8a7740" - - Blanche (RTP0RC7792SEB00010S) - compatible = "renesas,blanche", "renesas,r8a7792" - - BOCK-W - compatible = "renesas,bockw", "renesas,r8a7778" - - Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01) - compatible = "renesas,condor", "renesas,r8a77980" - - Draak (RTP0RC77995SEB0010S) - compatible = "renesas,draak", "renesas,r8a77995" - - Eagle (RTP0RC77970SEB0010S) - compatible = "renesas,eagle", "renesas,r8a77970" - - Ebisu (RTP0RC77990SEB0010S) - compatible = "renesas,ebisu", "renesas,r8a77990" - - Genmai (RTK772100BC00000BR) - compatible = "renesas,genmai", "renesas,r7s72100" - - GR-Peach (X28A-M01-E/F) - compatible = "renesas,gr-peach", "renesas,r7s72100" - - Gose (RTP0RC7793SEB00010S) - compatible = "renesas,gose", "renesas,r8a7793" - - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1)) - H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0)) - compatible = "renesas,h3ulcb", "renesas,r8a7795" - - Henninger - compatible = "renesas,henninger", "renesas,r8a7791" - - iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S) - compatible = "iwave,g23s", "renesas,r8a77470" - - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) - compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745" - - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM) - compatible = "iwave,g22m", "renesas,r8a7745" - - iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven) - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" - - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) - compatible = "iwave,g20m", "renesas,r8a7743" - - iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven) - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744" - - iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven) - compatible = "iwave,g20m", "renesas,r8a7744" - - Kingfisher (SBEV-RCAR-KF-M03) - compatible = "shimafuji,kingfisher" - - Koelsch (RTP0RC7791SEB00010S) - compatible = "renesas,koelsch", "renesas,r8a7791" - - Kyoto Microcomputer Co. KZM-A9-Dual - compatible = "renesas,kzm9d", "renesas,emev2" - - Kyoto Microcomputer Co. KZM-A9-GT - compatible = "renesas,kzm9g", "renesas,sh73a0" - - Lager (RTP0RC7790SEB00010S) - compatible = "renesas,lager", "renesas,r8a7790" - - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0)) - compatible = "renesas,m3ulcb", "renesas,r8a7796" - - M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1)) - compatible = "renesas,m3nulcb", "renesas,r8a77965" - - Marzen (R0P7779A00010S) - compatible = "renesas,marzen", "renesas,r8a7779" - - Porter (M2-LCDP) - compatible = "renesas,porter", "renesas,r8a7791" - - RSKRZA1 (YR0K77210C000BE) - compatible = "renesas,rskrza1", "renesas,r7s72100" - - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) - compatible = "renesas,rzn1d400-db", "renesas,r9a06g032" - - Salvator-X (RTP0RC7795SIPB0010S) - compatible = "renesas,salvator-x", "renesas,r8a7795" - - Salvator-X (RTP0RC7796SIPB0011S) - compatible = "renesas,salvator-x", "renesas,r8a7796" - - Salvator-X (RTP0RC7796SIPB0011S (M3-N)) - compatible = "renesas,salvator-x", "renesas,r8a77965" - - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) - compatible = "renesas,salvator-xs", "renesas,r8a7795" - - Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) - compatible = "renesas,salvator-xs", "renesas,r8a7796" - - Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S) - compatible = "renesas,salvator-xs", "renesas,r8a77965" - - SILK (RTP0RC7794LCB00011S) - compatible = "renesas,silk", "renesas,r8a7794" - - SK-RZG1E (YR8A77450S000BE) - compatible = "renesas,sk-rzg1e", "renesas,r8a7745" - - SK-RZG1M (YR8A77430S000BE) - compatible = "renesas,sk-rzg1m", "renesas,r8a7743" - - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) - compatible = "renesas,stout", "renesas,r8a7790" - - V3HSK (Y-ASK-RCAR-V3H-WS10) - compatible = "renesas,v3hsk", "renesas,r8a77980" - - V3MSK (Y-ASK-RCAR-V3M-WS10) - compatible = "renesas,v3msk", "renesas,r8a77970" - - Wheat (RTP0RC7792ASKB0000JE) - compatible = "renesas,wheat", "renesas,r8a7792" -- cgit v1.2.3 From d7dba6be0f31ae61f5f3296aa130f45d57d30f74 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 7 Jan 2019 13:07:36 +0200 Subject: dmaengine: dw: Remove misleading is_private property The commit a9ddb575d6d6 ("dmaengine: dw_dmac: Enhance device tree support") introduces is_private property in uncertain understanding what does it mean. First of all, documentation defines DMA_PRIVATE capability as Documentation/crypto/async-tx-api.txt: The DMA_PRIVATE capability flag is used to tag dma devices that should not be used by the general-purpose allocator. It can be set at initialization time if it is known that a channel will always be private. Alternatively, it is set when dma_request_channel() finds an unused "public" channel. A couple caveats to note when implementing a driver and consumer: 1/ Once a channel has been privately allocated it will no longer be considered by the general-purpose allocator even after a call to dma_release_channel(). 2/ Since capabilities are specified at the device level a dma_device with multiple channels will either have all channels public, or all channels private. Documentation/driver-api/dmaengine/provider.rst: - DMA_PRIVATE The devices only supports slave transfers, and as such isn't available for async transfers. The capability had been introduced by the commit 59b5ec21446b ("dmaengine: introduce dma_request_channel and private channels") and some code didn't changed from that times ever. Taking into consideration above and the fact that on all known platforms Synopsys DesignWare DMA engine is attached to serve slave transfers, the DMA_PRIVATE capability must be enabled for this device unconditionally. Otherwise, as rightfully noticed in drivers/dma/at_xdmac.c: /* * Without DMA_PRIVATE the driver is not able to allocate more than * one channel, second allocation fails in private_candidate. */ because of of a caveats mentioned in above documentation excerpts. So, remove conditional around DMA_PRIVATE followed by removal leftovers. If someone wonders, DMA_PRIVATE can be not used if and only if the all channels of the DMA controller are supposed to serve memory-to-memory like operations. For example, EP93xx has two controllers, one of which can only perform memory-to-memory transfers Note, this change doesn't affect dmatest to be able to test such controllers. Cc: Greg Kroah-Hartman (maintainer:SERIAL DRIVERS) Cc: Dan Williams Signed-off-by: Andy Shevchenko Acked-by: Greg Kroah-Hartman Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/snps-dma.txt | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt index db757df7057d..0bedceed1963 100644 --- a/Documentation/devicetree/bindings/dma/snps-dma.txt +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt @@ -23,8 +23,6 @@ Deprecated properties: Optional properties: -- is_private: The device channels should be marked as private and not for by the - general purpose DMA channel allocator. False if not passed. - multi-block: Multi block transfers supported by hardware. Array property with one cell per channel. 0: not supported, 1 (default): supported. - snps,dma-protection-control: AHB HPROT[3:1] protection setting. -- cgit v1.2.3 From a277105b239bdcb6490ec51366413643dbc8ed4a Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 5 Nov 2018 14:05:49 -0600 Subject: ARM: socfpga: dts: document "altr,stratix10-rst-mgr" binding "altr,stratix10-rst-mgr" is used for the Stratix10 reset manager. Signed-off-by: Dinh Nguyen Signed-off-by: Philipp Zabel --- Documentation/devicetree/bindings/reset/socfpga-reset.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/socfpga-reset.txt b/Documentation/devicetree/bindings/reset/socfpga-reset.txt index 98c9f560e5c5..38fe34fd8b8a 100644 --- a/Documentation/devicetree/bindings/reset/socfpga-reset.txt +++ b/Documentation/devicetree/bindings/reset/socfpga-reset.txt @@ -1,7 +1,8 @@ Altera SOCFPGA Reset Manager Required properties: -- compatible : "altr,rst-mgr" +- compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10) + "altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC - reg : Should contain 1 register ranges(address and length) - altr,modrst-offset : Should contain the offset of the first modrst register. - #reset-cells: 1 -- cgit v1.2.3 From 21b22136b4330abd1467e59fbe651ae4d18f0357 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Fri, 9 Nov 2018 10:42:04 +0900 Subject: dt-bindings: reset: uniphier: Replace the expression of USB3 with generic peripherals Replace the expression of "USB3 glue layer" with the glue layer of the generic peripherals to allow other devices to use it. The reset control belongs to this glue layer. Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring Signed-off-by: Philipp Zabel --- .../devicetree/bindings/reset/uniphier-reset.txt | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt index 101743dda223..f63c511a9de8 100644 --- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt +++ b/Documentation/devicetree/bindings/reset/uniphier-reset.txt @@ -120,27 +120,27 @@ Example: }; -USB3 core reset ---------------- +Peripheral core reset in glue layer +----------------------------------- -USB3 core reset belongs to USB3 glue layer. Before using the core reset, -it is necessary to control the clocks and resets to enable this layer. -These clocks and resets should be described in each property. +Some peripheral core reset belongs to its own glue layer. Before using +this core reset, it is necessary to control the clocks and resets to enable +this layer. These clocks and resets should be described in each property. Required properties: - compatible: Should be - "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC - "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC - "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC - "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC + "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3 + "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3 + "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3 + "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3 - #reset-cells: Should be 1. - reg: Specifies offset and length of the register set for the device. -- clocks: A list of phandles to the clock gate for USB3 glue layer. +- clocks: A list of phandles to the clock gate for the glue layer. According to the clock-names, appropriate clocks are required. - clock-names: Should contain "gio", "link" - for Pro4 SoC "link" - for others -- resets: A list of phandles to the reset control for USB3 glue layer. +- resets: A list of phandles to the reset control for the glue layer. According to the reset-names, appropriate resets are required. - reset-names: Should contain "gio", "link" - for Pro4 SoC -- cgit v1.2.3 From 69af3d1b8a91cf9b426c4238964df847036bf214 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Fri, 9 Nov 2018 10:42:06 +0900 Subject: dt-bindings: reset: uniphier: Add AHCI core reset description Add compatible strings for reset control of AHCI core implemented in UniPhier SoCs. The reset control belongs to AHCI glue layer. Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring Signed-off-by: Philipp Zabel --- Documentation/devicetree/bindings/reset/uniphier-reset.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt index f63c511a9de8..ea005177d20a 100644 --- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt +++ b/Documentation/devicetree/bindings/reset/uniphier-reset.txt @@ -133,6 +133,9 @@ Required properties: "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3 "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3 "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3 + "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI + "socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI + "socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI - #reset-cells: Should be 1. - reg: Specifies offset and length of the register set for the device. - clocks: A list of phandles to the clock gate for the glue layer. -- cgit v1.2.3 From 5d8d66077af12681441897a350f346c0da7f5576 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Fri, 4 Jan 2019 16:27:04 +0000 Subject: ASoC: dt-bindings: Document support for ak4497 ak4458 driver supports also ak4497 codec. Signed-off-by: Daniel Baluta Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/ak4458.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/ak4458.txt b/Documentation/devicetree/bindings/sound/ak4458.txt index 7839be78448d..e5820235e0d5 100644 --- a/Documentation/devicetree/bindings/sound/ak4458.txt +++ b/Documentation/devicetree/bindings/sound/ak4458.txt @@ -4,7 +4,7 @@ This device supports I2C mode. Required properties: -- compatible : "asahi-kasei,ak4458" +- compatible : "asahi-kasei,ak4458" or "asahi-kasei,ak4497" - reg : The I2C address of the device for I2C Optional properties: -- cgit v1.2.3 From 80261459804507a349daf754d6e5d835bb8578ae Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 7 Jan 2019 09:29:49 +0000 Subject: dt-bindings: spi: Move the bindings for the FSL QSPI driver Move the documentation of the old SPI NOR driver to the place of the new SPI memory interface based driver. Signed-off-by: Frieder Schrempf Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- .../devicetree/bindings/mtd/fsl-quadspi.txt | 65 ---------------------- .../devicetree/bindings/spi/spi-fsl-qspi.txt | 65 ++++++++++++++++++++++ 2 files changed, 65 insertions(+), 65 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt create mode 100644 Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt deleted file mode 100644 index 483e9cfac1b1..000000000000 --- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt +++ /dev/null @@ -1,65 +0,0 @@ -* Freescale Quad Serial Peripheral Interface(QuadSPI) - -Required properties: - - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", - "fsl,imx7d-qspi", "fsl,imx6ul-qspi", - "fsl,ls1021a-qspi" - or - "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi", - "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" - - reg : the first contains the register location and length, - the second contains the memory mapping address and length - - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory" - - interrupts : Should contain the interrupt for the device - - clocks : The clocks needed by the QuadSPI controller - - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". - -Optional properties: - - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B. - Each bus can be connected with two NOR flashes. - Most of the time, each bus only has one NOR flash - connected, this is the default case. - But if there are two NOR flashes connected to the - bus, you should enable this property. - (Please check the board's schematic.) - - big-endian : That means the IP register is big endian - -Example: - -qspi0: quadspi@40044000 { - compatible = "fsl,vf610-qspi"; - reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_QSPI0_EN>, - <&clks VF610_CLK_QSPI0>; - clock-names = "qspi_en", "qspi"; - - flash0: s25fl128s@0 { - .... - }; -}; - -Example showing the usage of two SPI NOR devices: - -&qspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi2>; - status = "okay"; - - flash0: n25q256a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - reg = <0>; - }; - - flash1: n25q256a@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - reg = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt new file mode 100644 index 000000000000..483e9cfac1b1 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt @@ -0,0 +1,65 @@ +* Freescale Quad Serial Peripheral Interface(QuadSPI) + +Required properties: + - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", + "fsl,imx7d-qspi", "fsl,imx6ul-qspi", + "fsl,ls1021a-qspi" + or + "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi", + "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" + - reg : the first contains the register location and length, + the second contains the memory mapping address and length + - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory" + - interrupts : Should contain the interrupt for the device + - clocks : The clocks needed by the QuadSPI controller + - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". + +Optional properties: + - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B. + Each bus can be connected with two NOR flashes. + Most of the time, each bus only has one NOR flash + connected, this is the default case. + But if there are two NOR flashes connected to the + bus, you should enable this property. + (Please check the board's schematic.) + - big-endian : That means the IP register is big endian + +Example: + +qspi0: quadspi@40044000 { + compatible = "fsl,vf610-qspi"; + reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_QSPI0_EN>, + <&clks VF610_CLK_QSPI0>; + clock-names = "qspi_en", "qspi"; + + flash0: s25fl128s@0 { + .... + }; +}; + +Example showing the usage of two SPI NOR devices: + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2>; + status = "okay"; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; -- cgit v1.2.3 From 78df30808961cd32f0517c7469886386b0680852 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 7 Jan 2019 09:29:50 +0000 Subject: dt-bindings: spi: Adjust the bindings for the FSL QSPI driver Adjust the documentation of the new SPI memory interface based driver to reflect the new drivers settings. The "old" driver was using the "fsl,qspi-has-second-chip" property to select one of two dual chip setups (two chips on one bus or two chips on separate buses). And it used the order in which the subnodes are defined in the dt to select the CS, the chip is connected to. Both methods are wrong and in fact the "reg" property should be used to determine which bus and CS a chip is connected to. This also enables us to use different setups than just single chip, or symmetric dual chip. So the porting of the driver from the MTD to the SPI framework actually enforces the use of the "reg" properties and makes "fsl,qspi-has-second-chip" superfluous. As all boards that have "fsl,qspi-has-second-chip" set, also have correct "reg" properties, the removal of this property shouldn't lead to any incompatibilities. The only compatibility issues I can see are with imx6sx-sdb.dts and imx6sx-sdb-reva.dts, which have their reg properties set incorrectly (see explanation here: [2]), all other boards should stay compatible. Also the "big-endian" flag was removed, as this setting is now selected by the driver, depending on which SoC is in use. [2] https://patchwork.ozlabs.org/patch/922817/#1925445 Signed-off-by: Frieder Schrempf Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt index 483e9cfac1b1..e8f1d627d288 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt @@ -14,15 +14,13 @@ Required properties: - clocks : The clocks needed by the QuadSPI controller - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". -Optional properties: - - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B. - Each bus can be connected with two NOR flashes. - Most of the time, each bus only has one NOR flash - connected, this is the default case. - But if there are two NOR flashes connected to the - bus, you should enable this property. - (Please check the board's schematic.) - - big-endian : That means the IP register is big endian +Required SPI slave node properties: + - reg: There are two buses (A and B) with two chip selects each. + This encodes to which bus and CS the flash is connected: + <0>: Bus A, CS 0 + <1>: Bus A, CS 1 + <2>: Bus B, CS 0 + <3>: Bus B, CS 1 Example: @@ -40,7 +38,7 @@ qspi0: quadspi@40044000 { }; }; -Example showing the usage of two SPI NOR devices: +Example showing the usage of two SPI NOR devices on bus A: &qspi2 { pinctrl-names = "default"; -- cgit v1.2.3 From e595da28ecc87e7cec2681c01d5970e31153bddd Mon Sep 17 00:00:00 2001 From: Cosmin Samoila Date: Fri, 4 Jan 2019 09:17:37 +0000 Subject: ASoC: micfil: Add bindings for MICFIL DAI Document the bindings for MICFIL DAI. Signed-off-by: Cosmin-Gabriel Samoila Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/fsl,micfil.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/fsl,micfil.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/fsl,micfil.txt b/Documentation/devicetree/bindings/sound/fsl,micfil.txt new file mode 100644 index 000000000000..53e227b15277 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,micfil.txt @@ -0,0 +1,32 @@ +NXP MICFIL Digital Audio Interface (MICFIL). + +The MICFIL digital interface provides a 16-bit audio signal from a PDM +microphone bitstream in a configurable output sampling rate. + +Required properties: + + - compatible : Compatible list, contains "fsl,imx8mm-micfil" + + - reg : Offset and length of the register set for the device. + + - interrupts : Contains the micfil interrupts. + + - clocks : Must contain an entry for each entry in clock-names. + + - clock-names : Must include the "ipg_clk" for register access and + "ipg_clk_app" for internal micfil clock. + + - dmas : Generic dma devicetree binding as described in + Documentation/devicetree/bindings/dma/dma.txt. + +Example: +micfil: micfil@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x0 0x30080000 0x0 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8MM_CLK_PDM_IPG>, + <&clk IMX8MM_CLK_PDM_ROOT>; + clock-names = "ipg_clk", "ipg_clk_app"; + dmas = <&sdma2 24 26 0x80000000>; +}; -- cgit v1.2.3 From 2f00f7715e624d04e25d9cb8bb0f53884d3bcb59 Mon Sep 17 00:00:00 2001 From: Maruthi Srinivas Bayyavarapu Date: Thu, 3 Jan 2019 23:39:51 +0530 Subject: dt-bindings: ASoC: xlnx, spdif: Document spdif bindings Added documentation for SPDIF IP DT bindings. Signed-off-by: Maruthi Srinivas Bayyavarapu Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/xlnx,spdif.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/xlnx,spdif.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/xlnx,spdif.txt b/Documentation/devicetree/bindings/sound/xlnx,spdif.txt new file mode 100644 index 000000000000..15c2d64d247c --- /dev/null +++ b/Documentation/devicetree/bindings/sound/xlnx,spdif.txt @@ -0,0 +1,28 @@ +Device-Tree bindings for Xilinx SPDIF IP + +The IP supports playback and capture of SPDIF audio + +Required properties: + - compatible: "xlnx,spdif-2.0" + - clock-names: List of input clocks. + Required elements: "s_axi_aclk", "aud_clk_i" + - clocks: Input clock specifier. Refer to common clock bindings. + - reg: Base address and address length of the IP core instance. + - interrupts-parent: Phandle for interrupt controller. + - interrupts: List of Interrupt numbers. + - xlnx,spdif-mode: 0 :- receiver mode + 1 :- transmitter mode + - xlnx,aud_clk_i: input audio clock value. + +Example: + spdif_0: spdif@80010000 { + clock-names = "aud_clk_i", "s_axi_aclk"; + clocks = <&misc_clk_0>, <&clk 71>; + compatible = "xlnx,spdif-2.0"; + interrupt-names = "spdif_interrupt"; + interrupt-parent = <&gic>; + interrupts = <0 91 4>; + reg = <0x0 0x80010000 0x0 0x10000>; + xlnx,spdif-mode = <1>; + xlnx,aud_clk_i = <49152913>; + }; -- cgit v1.2.3 From 5dc4ca2996840db569e43d00420c10499140274a Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 26 Dec 2018 08:59:53 +0800 Subject: ASoC: sgtl5000: Allow SCLK pad drive strength to be changed This patch introduces "sclk-strength" property to allow SCLK pad drive strength to be changed via device tree. When running playback test on LS1028ARDB, Tx Frame sync error interrupt will occur sometimes. Some noises also exist. After changing SCLK pad drive strength to the maximum value, the issues are gone. Signed-off-by: Alison Wang Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/sgtl5000.txt | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt index 9c58f724396a..9d9ff5184939 100644 --- a/Documentation/devicetree/bindings/sound/sgtl5000.txt +++ b/Documentation/devicetree/bindings/sound/sgtl5000.txt @@ -37,6 +37,15 @@ VDDIO 1.8V 2.5V 3.3V 2 = 3.33 mA 5.74 mA 8.03 mA 3 = 4.99 mA 8.61 mA 12.05 mA +- sclk-strength: the SCLK pad strength. Possible values are: +0, 1, 2 and 3 as per the table below: + +VDDIO 1.8V 2.5V 3.3V +0 = Disable +1 = 1.66 mA 2.87 mA 4.02 mA +2 = 3.33 mA 5.74 mA 8.03 mA +3 = 4.99 mA 8.61 mA 12.05 mA + Example: sgtl5000: codec@a { -- cgit v1.2.3 From 560b097c77ccdfa22586718e9e45f85e86ef2156 Mon Sep 17 00:00:00 2001 From: Cezary Gapinski Date: Mon, 24 Dec 2018 23:00:40 +0100 Subject: spi: stm32: add description about STM32F4 bindings Add description that STM32F4 can be used in compatible property. Master Inter-Data Idleness optional property cannot be used in STM32F4. Signed-off-by: Cezary Gapinski Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-stm32.txt | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-stm32.txt b/Documentation/devicetree/bindings/spi/spi-stm32.txt index 1b3fa2c119d5..d82755c63eaf 100644 --- a/Documentation/devicetree/bindings/spi/spi-stm32.txt +++ b/Documentation/devicetree/bindings/spi/spi-stm32.txt @@ -7,7 +7,9 @@ from 4 to 32-bit data size. Although it can be configured as master or slave, only master is supported by the driver. Required properties: -- compatible: Must be "st,stm32h7-spi". +- compatible: Should be one of: + "st,stm32h7-spi" + "st,stm32f4-spi" - reg: Offset and length of the device's register set. - interrupts: Must contain the interrupt id. - clocks: Must contain an entry for spiclk (which feeds the internal clock @@ -30,8 +32,9 @@ Child nodes represent devices on the SPI bus See ../spi/spi-bus.txt Optional properties: -- st,spi-midi-ns: (Master Inter-Data Idleness) minimum time delay in - nanoseconds inserted between two consecutive data frames. +- st,spi-midi-ns: Only for STM32H7, (Master Inter-Data Idleness) minimum time + delay in nanoseconds inserted between two consecutive data + frames. Example: -- cgit v1.2.3 From 48f1b4efd67c922eff113f247533cbe175b1491e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Jan 2019 13:12:33 +0100 Subject: regulator: Fix trivial language typos Fix few trivial language typos in core and drivers. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/pfuze100.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/pfuze100.txt b/Documentation/devicetree/bindings/regulator/pfuze100.txt index f9be1acf891c..4d3b12b92cb3 100644 --- a/Documentation/devicetree/bindings/regulator/pfuze100.txt +++ b/Documentation/devicetree/bindings/regulator/pfuze100.txt @@ -8,7 +8,7 @@ Optional properties: - fsl,pfuze-support-disable-sw: Boolean, if present disable all unused switch regulators to save power consumption. Attention, ensure that all important regulators (e.g. DDR ref, DDR supply) has set the "regulator-always-on" - property. If not present, the switched regualtors are always on and can't be + property. If not present, the switched regulators are always on and can't be disabled. This binding is a workaround to keep backward compatibility with old dtb's which rely on the fact that the switched regulators are always on and don't mark them explicit as "regulator-always-on". -- cgit v1.2.3 From fbeab182b1ae41c3e2e9c05808c01e8f65883e61 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 12 Dec 2018 15:51:46 -0800 Subject: dt-bindings: soc: Add a new binding for the BCM2835 PM node. (v4) This binding supersedes the bcm2835-pm-wdt binding which only covered enough to provide a watchdog, but the HW block is actually mostly about power domains. Signed-off-by: Eric Anholt Reviewed-by: Rob Herring (v3) Acked-by: Stefan Wahren Signed-off-by: Stefan Wahren --- .../bindings/soc/bcm/brcm,bcm2835-pm.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.txt b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.txt new file mode 100644 index 000000000000..3b7d32956391 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.txt @@ -0,0 +1,46 @@ +BCM2835 PM (Power domains, watchdog) + +The PM block controls power domains and some reset lines, and includes +a watchdog timer. This binding supersedes the brcm,bcm2835-pm-wdt +binding which covered some of PM's register range and functionality. + +Required properties: + +- compatible: Should be "brcm,bcm2835-pm" +- reg: Specifies base physical address and size of the two + register ranges ("PM" and "ASYNC_BRIDGE" in that + order) +- clocks: a) v3d: The V3D clock from CPRMAN + b) peri_image: The PERI_IMAGE clock from CPRMAN + c) h264: The H264 clock from CPRMAN + d) isp: The ISP clock from CPRMAN +- #reset-cells: Should be 1. This property follows the reset controller + bindings[1]. +- #power-domain-cells: Should be 1. This property follows the power domain + bindings[2]. + +Optional properties: + +- timeout-sec: Contains the watchdog timeout in seconds +- system-power-controller: Whether the watchdog is controlling the + system power. This node follows the power controller bindings[3]. + +[1] Documentation/devicetree/bindings/reset/reset.txt +[2] Documentation/devicetree/bindings/power/power_domain.txt +[3] Documentation/devicetree/bindings/power/power-controller.txt + +Example: + +pm { + compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; + #power-domain-cells = <1>; + #reset-cells = <1>; + reg = <0x7e100000 0x114>, + <0x7e00a000 0x24>; + clocks = <&clocks BCM2835_CLOCK_V3D>, + <&clocks BCM2835_CLOCK_PERI_IMAGE>, + <&clocks BCM2835_CLOCK_H264>, + <&clocks BCM2835_CLOCK_ISP>; + clock-names = "v3d", "peri_image", "h264", "isp"; + system-power-controller; +}; -- cgit v1.2.3 From 5885ca007e9a975d1749c388a7c84bffeef73cd6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 15 Dec 2018 08:31:51 +0530 Subject: dt-bindings: vendor-prefixes: Add Novtech Vendor Prefix Add vendor prefix for NovTech, Inc. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..17c29009184a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -273,6 +273,7 @@ nintendo Nintendo nlt NLT Technologies, Ltd. nokia Nokia nordic Nordic Semiconductor +novtech NovTech, Inc. nutsboard NutsBoard nuvoton Nuvoton Technology Corporation nvd New Vision Display -- cgit v1.2.3 From 5b42aac8904bfe8fcd65179c0fe71a6a1109ee53 Mon Sep 17 00:00:00 2001 From: Jan Kotas Date: Thu, 13 Dec 2018 12:49:28 +0000 Subject: dt-bindings: clk: Add bindings for Fixed MMIO clock This patch adds a DT binding documentation for Fixed Memory Mapped IO clocks. Signed-off-by: Jan Kotas Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/fixed-mmio-clock.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt b/Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt new file mode 100644 index 000000000000..c359367fd1a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt @@ -0,0 +1,24 @@ +Binding for simple memory mapped io fixed-rate clock sources. +The driver reads a clock frequency value from a single 32-bit memory mapped +I/O register and registers it as a fixed rate clock. + +It was designed for test systems, like FPGA, not for complete, finished SoCs. + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be "fixed-mmio-clock". +- #clock-cells : from common clock binding; shall be set to 0. +- reg : Address and length of the clock value register set. + +Optional properties: +- clock-output-names : From common clock binding. + +Example: +sysclock: sysclock@fd020004 { + #clock-cells = <0>; + compatible = "fixed-mmio-clock"; + reg = <0xfd020004 0x4>; +}; -- cgit v1.2.3 From 6131dc81211cfcd8b7bd210665fbe0b6ba2e5fc5 Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Mon, 17 Dec 2018 19:15:36 -0700 Subject: clk: qcom: smd: Add support for MSM8998 rpm clocks Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998 for clients to vote on. Signed-off-by: Jeffrey Hugo Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,rpmcc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index 87b4949e9bc8..944719bd586f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -16,6 +16,7 @@ Required properties : "qcom,rpmcc-msm8974", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" "qcom,rpmcc-msm8996", "qcom,rpmcc" + "qcom,rpmcc-msm8998", "qcom,rpmcc" "qcom,rpmcc-qcs404", "qcom,rpmcc" - #clock-cells : shall contain 1 -- cgit v1.2.3 From e7a095908227fb3ccc86d001d9e13c9ae2bef8e6 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Tue, 8 Jan 2019 21:57:23 +0000 Subject: arm64: dts: rockchip: Add devicetree for NanoPC-T4 This adds a device tree for the NanoPC-T4 SBC, which is based on the Rockchip RK3399 SoC and marketed by FriendlyELEC. Known working: - Serial - Ethernet - HDMI - USB 2.0 All of the interesting stuff is in a .dtsi because there are at least two other boards that share most of it: NanoPi M4 and NanoPi NEO4. Signed-off-by: Tomeu Vizoso Reviewed-by: Rob Herring [rm: various further cleanup] Signed-off-by: Robin Murphy Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index b12958bda09c..bcc60c492a12 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -87,6 +87,11 @@ properties: - const: firefly,roc-rk3399-pc - const: rockchip,rk3399 + - description: FriendlyElec NanoPC-T4 + items: + - const: friendlyarm,nanopc-t4 + - const: rockchip,rk3399 + - description: GeekBuying GeekBox items: - const: geekbuying,geekbox -- cgit v1.2.3 From a1a38e1f4d1d79dfbedb66148d611827c23c7c44 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 3 Dec 2018 15:32:07 -0600 Subject: dt-bindings: arm: Convert FSL board/soc bindings to json-schema Convert Freescale SoC bindings to DT schema format using json-schema. Cc: Shawn Guo Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/armadeus.txt | 6 - Documentation/devicetree/bindings/arm/bhf.txt | 6 - .../devicetree/bindings/arm/compulab-boards.txt | 25 --- Documentation/devicetree/bindings/arm/fsl.txt | 237 --------------------- Documentation/devicetree/bindings/arm/fsl.yaml | 214 +++++++++++++++++++ Documentation/devicetree/bindings/arm/i2se.txt | 22 -- Documentation/devicetree/bindings/arm/olimex.txt | 10 - .../devicetree/bindings/arm/technologic.txt | 23 -- 8 files changed, 214 insertions(+), 329 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/armadeus.txt delete mode 100644 Documentation/devicetree/bindings/arm/bhf.txt delete mode 100644 Documentation/devicetree/bindings/arm/compulab-boards.txt delete mode 100644 Documentation/devicetree/bindings/arm/fsl.txt create mode 100644 Documentation/devicetree/bindings/arm/fsl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/i2se.txt delete mode 100644 Documentation/devicetree/bindings/arm/olimex.txt delete mode 100644 Documentation/devicetree/bindings/arm/technologic.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/armadeus.txt b/Documentation/devicetree/bindings/arm/armadeus.txt deleted file mode 100644 index 9821283ff516..000000000000 --- a/Documentation/devicetree/bindings/arm/armadeus.txt +++ /dev/null @@ -1,6 +0,0 @@ -Armadeus i.MX Platforms Device Tree Bindings ------------------------------------------------ - -APF51: i.MX51 based module. -Required root node properties: - - compatible = "armadeus,imx51-apf51", "fsl,imx51"; diff --git a/Documentation/devicetree/bindings/arm/bhf.txt b/Documentation/devicetree/bindings/arm/bhf.txt deleted file mode 100644 index 886b503caf9c..000000000000 --- a/Documentation/devicetree/bindings/arm/bhf.txt +++ /dev/null @@ -1,6 +0,0 @@ -Beckhoff Automation Platforms Device Tree Bindings --------------------------------------------------- - -CX9020 Embedded PC -Required root node properties: - - compatible = "bhf,cx9020", "fsl,imx53"; diff --git a/Documentation/devicetree/bindings/arm/compulab-boards.txt b/Documentation/devicetree/bindings/arm/compulab-boards.txt deleted file mode 100644 index 42a10285af9c..000000000000 --- a/Documentation/devicetree/bindings/arm/compulab-boards.txt +++ /dev/null @@ -1,25 +0,0 @@ -CompuLab SB-SOM is a multi-module baseboard capable of carrying: - - CM-T43 - - CM-T54 - - CM-QS600 - - CL-SOM-AM57x - - CL-SOM-iMX7 -modules with minor modifications to the SB-SOM assembly. - -Required root node properties: - - compatible = should be "compulab,sb-som" - -Compulab CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on -Freescale i.MX7 ARM Cortex-A7 System-on-Chip. - -Required root node properties: - - compatible = "compulab,cl-som-imx7", "fsl,imx7d"; - -Compulab SBC-iMX7 is a single board computer based on the -Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with -the CL-SOM-iMX7 System-on-Module providing most of the functions, -and SB-SOM-iMX7 carrier board providing additional peripheral -functions and connectors. - -Required root node properties: - - compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d"; diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt deleted file mode 100644 index 7fbc42484001..000000000000 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ /dev/null @@ -1,237 +0,0 @@ -Freescale i.MX Platforms Device Tree Bindings ------------------------------------------------ - -i.MX23 Evaluation Kit -Required root node properties: - - compatible = "fsl,imx23-evk", "fsl,imx23"; - -i.MX25 Product Development Kit -Required root node properties: - - compatible = "fsl,imx25-pdk", "fsl,imx25"; - -i.MX27 Product Development Kit -Required root node properties: - - compatible = "fsl,imx27-pdk", "fsl,imx27"; - -i.MX28 Evaluation Kit -Required root node properties: - - compatible = "fsl,imx28-evk", "fsl,imx28"; - -i.MX51 Babbage Board -Required root node properties: - - compatible = "fsl,imx51-babbage", "fsl,imx51"; - -i.MX53 Automotive Reference Design Board -Required root node properties: - - compatible = "fsl,imx53-ard", "fsl,imx53"; - -i.MX53 Evaluation Kit -Required root node properties: - - compatible = "fsl,imx53-evk", "fsl,imx53"; - -i.MX53 Quick Start Board -Required root node properties: - - compatible = "fsl,imx53-qsb", "fsl,imx53"; - -i.MX53 Smart Mobile Reference Design Board -Required root node properties: - - compatible = "fsl,imx53-smd", "fsl,imx53"; - -i.MX6 Quad Armadillo2 Board -Required root node properties: - - compatible = "fsl,imx6q-arm2", "fsl,imx6q"; - -i.MX6 Quad SABRE Lite Board -Required root node properties: - - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; - -i.MX6 Quad SABRE Smart Device Board -Required root node properties: - - compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; - -i.MX6 Quad SABRE Automotive Board -Required root node properties: - - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; - -i.MX6SLL EVK board -Required root node properties: - - compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; - -i.MX6 Quad Plus SABRE Smart Device Board -Required root node properties: - - compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp"; - -i.MX6 Quad Plus SABRE Automotive Board -Required root node properties: - - compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; - -i.MX6 DualLite SABRE Smart Device Board -Required root node properties: - - compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; - -i.MX6 DualLite/Solo SABRE Automotive Board -Required root node properties: - - compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; - -i.MX6 SoloLite EVK Board -Required root node properties: - - compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; - -i.MX6 UltraLite 14x14 EVK Board -Required root node properties: - - compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; - -i.MX6 UltraLiteLite 14x14 EVK Board -Required root node properties: - - compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; - -i.MX6 ULZ 14x14 EVK Board -Required root node properties: - - compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz"; - -i.MX6 SoloX SDB Board -Required root node properties: - - compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; - -i.MX6 SoloX Sabre Auto Board -Required root node properties: - - compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; - -i.MX7 SabreSD Board -Required root node properties: - - compatible = "fsl,imx7d-sdb", "fsl,imx7d"; - -i.MX7ULP Evaluation Kit -Required root node properties: - - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; - -Generic i.MX boards -------------------- - -No iomux setup is done for these boards, so this must have been configured -by the bootloader for boards to work with the generic bindings. - -i.MX27 generic board -Required root node properties: - - compatible = "fsl,imx27"; - -i.MX51 generic board -Required root node properties: - - compatible = "fsl,imx51"; - -i.MX53 generic board -Required root node properties: - - compatible = "fsl,imx53"; - -i.MX6q generic board -Required root node properties: - - compatible = "fsl,imx6q"; - -i.MX7ULP generic board -Required root node properties: - - compatible = "fsl,imx7ulp"; - -Freescale Vybrid Platform Device Tree Bindings ----------------------------------------------- - -For the Vybrid SoC familiy all variants with DDR controller are supported, -which is the VF5xx and VF6xx series. Out of historical reasons, in most -places the kernel uses vf610 to refer to the whole familiy. -The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 -core support. - -Required root node compatible property (one of them): - - compatible = "fsl,vf500"; - - compatible = "fsl,vf510"; - - compatible = "fsl,vf600"; - - compatible = "fsl,vf610"; - - compatible = "fsl,vf610m4"; - -Freescale LS1021A Platform Device Tree Bindings ------------------------------------------------- - -Required root node compatible properties: - - compatible = "fsl,ls1021a"; - -Freescale ARMv8 based Layerscape SoC family Device Tree Bindings ----------------------------------------------------------------- - -LS1012A SoC -Required root node properties: - - compatible = "fsl,ls1012a"; - -LS1012A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; - -LS1012A ARMv8 based FRDM Board -Required root node properties: - - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; - -LS1012A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; - -LS1043A SoC -Required root node properties: - - compatible = "fsl,ls1043a"; - -LS1043A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; - -LS1043A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; - -LS1046A SoC -Required root node properties: - - compatible = "fsl,ls1046a"; - -LS1046A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; - -LS1046A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; - -LS1088A SoC -Required root node properties: - - compatible = "fsl,ls1088a"; - -LS1088A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; - -LS1088A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; - -LS2080A SoC -Required root node properties: - - compatible = "fsl,ls2080a"; - -LS2080A ARMv8 based Simulator model -Required root node properties: - - compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; - -LS2080A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; - -LS2080A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; - -LS2088A SoC -Required root node properties: - - compatible = "fsl,ls2088a"; - -LS2088A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; - -LS2088A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml new file mode 100644 index 000000000000..a4d625d7ff4d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/fsl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX Platforms Device Tree Bindings + +maintainers: + - Shawn Guo + - Li Yang + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: i.MX23 based Boards + items: + - enum: + - fsl,imx23-evk + - olimex,imx23-olinuxino + - const: fsl,imx23 + + - description: i.MX25 Product Development Kit + items: + - enum: + - fsl,imx25-pdk + - const: fsl,imx25 + + - description: i.MX27 Product Development Kit + items: + - enum: + - fsl,imx27-pdk + - const: fsl,imx27 + + - description: i.MX28 based Boards + items: + - enum: + - fsl,imx28-evk + - i2se,duckbill + - i2se,duckbill-2 + - technologic,imx28-ts4600 + - const: fsl,imx28 + - description: i.MX28 Duckbill 2 based Boards + items: + - enum: + - i2se,duckbill-2-485 + - i2se,duckbill-2-enocean + - i2se,duckbill-2-spi + - const: i2se,duckbill-2 + - const: fsl,imx28 + + - description: i.MX51 Babbage Board + items: + - enum: + - armadeus,imx51-apf51 + - fsl,imx51-babbage + - technologic,imx51-ts4800 + - const: fsl,imx51 + + - description: i.MX53 based Boards + items: + - enum: + - bhf,cx9020 + - fsl,imx53-ard + - fsl,imx53-evk + - fsl,imx53-qsb + - fsl,imx53-smd + - const: fsl,imx53 + + - description: i.MX6Q based Boards + items: + - enum: + - fsl,imx6q-arm2 + - fsl,imx6q-sabreauto + - fsl,imx6q-sabrelite + - fsl,imx6q-sabresd + - technologic,imx6q-ts4900 + - technologic,imx6q-ts7970 + - const: fsl,imx6q + + - description: i.MX6QP based Boards + items: + - enum: + - fsl,imx6qp-sabreauto # i.MX6 Quad Plus SABRE Automotive Board + - fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board + - const: fsl,imx6qp + + - description: i.MX6DL based Boards + items: + - enum: + - fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board + - fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board + - technologic,imx6dl-ts4900 + - technologic,imx6dl-ts7970 + - const: fsl,imx6dl + + - description: i.MX6SL based Boards + items: + - enum: + - fsl,imx6sl-evk # i.MX6 SoloLite EVK Board + - const: fsl,imx6sl + + - description: i.MX6SLL based Boards + items: + - enum: + - fsl,imx6sll-evk + - const: fsl,imx6sll + + - description: i.MX6SX based Boards + items: + - enum: + - fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board + - fsl,imx6sx-sdb # i.MX6 SoloX SDB Board + - const: fsl,imx6sx + + - description: i.MX6UL based Boards + items: + - enum: + - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board + - const: fsl,imx6ul + + - description: i.MX6ULL based Boards + items: + - enum: + - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board + - const: fsl,imx6ull + + - description: i.MX6ULZ based Boards + items: + - enum: + - fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board + - const: fsl,imx6ull # This seems odd. Should be last? + - const: fsl,imx6ulz + + - description: i.MX7D based Boards + items: + - enum: + - fsl,imx7d-sdb # i.MX7 SabreSD Board + - const: fsl,imx7d + + - description: + Compulab SBC-iMX7 is a single board computer based on the + Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with + the CL-SOM-iMX7 System-on-Module providing most of the functions, + and SB-SOM-iMX7 carrier board providing additional peripheral + functions and connectors. + items: + - const: compulab,sbc-imx7 + - const: compulab,cl-som-imx7 + - const: fsl,imx7d + + - description: + Freescale Vybrid Platform Device Tree Bindings + + For the Vybrid SoC familiy all variants with DDR controller are supported, + which is the VF5xx and VF6xx series. Out of historical reasons, in most + places the kernel uses vf610 to refer to the whole familiy. + The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 + core support. + items: + - enum: + - fsl,vf500 + - fsl,vf510 + - fsl,vf600 + - fsl,vf610 + - fsl,vf610m4 + + - description: LS1021A based Boards + items: + - enum: + - fsl,ls1012a-rdb + - fsl,ls1012a-frdm + - fsl,ls1012a-qds + - const: fsl,ls1021a + + - description: LS1043A based Boards + items: + - enum: + - fsl,ls1043a-rdb + - fsl,ls1043a-qds + - const: fsl,ls1043a + + - description: LS1046A based Boards + items: + - enum: + - fsl,ls1046a-qds + - fsl,ls1046a-rdb + - const: fsl,ls1046a + + - description: LS1088A based Boards + items: + - enum: + - fsl,ls1088a-qds + - fsl,ls1088a-rdb + - const: fsl,ls1088a + + - description: LS2080A based Boards + items: + - enum: + - fsl,ls2080a-simu + - fsl,ls2080a-qds + - fsl,ls2080a-rdb + - const: fsl,ls2080a + + - description: LS2088A based Boards + items: + - enum: + - fsl,ls2088a-qds + - fsl,ls2088a-rdb + - const: fsl,ls2088a + +... diff --git a/Documentation/devicetree/bindings/arm/i2se.txt b/Documentation/devicetree/bindings/arm/i2se.txt deleted file mode 100644 index dbd54a3aa07d..000000000000 --- a/Documentation/devicetree/bindings/arm/i2se.txt +++ /dev/null @@ -1,22 +0,0 @@ -I2SE Device Tree Bindings -------------------------- - -Duckbill Board -Required root node properties: - - compatible = "i2se,duckbill", "fsl,imx28"; - -Duckbill 2 Board -Required root node properties: - - compatible = "i2se,duckbill-2", "fsl,imx28"; - -Duckbill 2 485 Board -Required root node properties: - - compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28"; - -Duckbill 2 EnOcean Board -Required root node properties: - - compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28"; - -Duckbill 2 SPI Board -Required root node properties: - - compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28"; diff --git a/Documentation/devicetree/bindings/arm/olimex.txt b/Documentation/devicetree/bindings/arm/olimex.txt deleted file mode 100644 index d726aeca56be..000000000000 --- a/Documentation/devicetree/bindings/arm/olimex.txt +++ /dev/null @@ -1,10 +0,0 @@ -Olimex Device Tree Bindings ---------------------------- - -SAM9-L9260 Board -Required root node properties: - - compatible = "olimex,sam9-l9260", "atmel,at91sam9260"; - -i.MX23 Olinuxino Low Cost Board -Required root node properties: - - compatible = "olimex,imx23-olinuxino", "fsl,imx23"; diff --git a/Documentation/devicetree/bindings/arm/technologic.txt b/Documentation/devicetree/bindings/arm/technologic.txt deleted file mode 100644 index f1cedc00dcab..000000000000 --- a/Documentation/devicetree/bindings/arm/technologic.txt +++ /dev/null @@ -1,23 +0,0 @@ -Technologic Systems Platforms Device Tree Bindings --------------------------------------------------- - -TS-4600 is a System-on-Module based on the Freescale i.MX28 System-on-Chip. -It can be mounted on a carrier board providing additional peripheral connectors. -Required root node properties: - - compatible = "technologic,imx28-ts4600", "fsl,imx28" - -TS-4800 board -Required root node properties: - - compatible = "technologic,imx51-ts4800", "fsl,imx51"; - -TS-4900 is a System-on-Module based on the Freescale i.MX6 System-on-Chip. -It can be mounted on a carrier board providing additional peripheral connectors. -Required root node properties: - - compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl" - - compatible = "technologic,imx6q-ts4900", "fsl,imx6q" - -TS-7970 is a System-on-Module based on the Freescale i.MX6 System-on-Chip. -It can be mounted on a carrier board providing additional peripheral connectors. -Required root node properties: - - compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl" - - compatible = "technologic,imx6q-ts7970", "fsl,imx6q" -- cgit v1.2.3 From a9074e1e3d78298dd085c84299c8de27766f3884 Mon Sep 17 00:00:00 2001 From: Dianlong Li Date: Thu, 13 Dec 2018 18:13:48 +0800 Subject: dt-bindings: define vendor prefix for whwave, Inc. Introduce vendor prefix for whwave, Inc. for SD3078 rtc device. Signed-off-by: Dianlong Li Reviewed-by: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..475f90687c05 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -430,6 +430,7 @@ vot Vision Optical Technology Co., Ltd. wd Western Digital Corp. wetek WeTek Electronics, limited. wexler Wexler +whwave Shenzhen whwave Electronics, Inc. wi2wi Wi2Wi, Inc. winbond Winbond Electronics corp. winstar Winstar Display Corp. -- cgit v1.2.3 From a1c1eae4690aacd3a7ce9df97b47194ac2bf44e2 Mon Sep 17 00:00:00 2001 From: Dianlong Li Date: Thu, 13 Dec 2018 18:13:49 +0800 Subject: dt-bindings: rtc: sd3078: add device tree documentation The devicetree documentation for the SD3078 device tree. Signed-off-by: Dianlong Li Reviewed-by: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/rtc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc.txt b/Documentation/devicetree/bindings/rtc/rtc.txt index 7c8da6926095..e46edab31403 100644 --- a/Documentation/devicetree/bindings/rtc/rtc.txt +++ b/Documentation/devicetree/bindings/rtc/rtc.txt @@ -62,3 +62,4 @@ ricoh,rs5c372b I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC ricoh,rv5c386 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC ricoh,rv5c387a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC sii,s35390a 2-wire CMOS real-time clock +whwave,sd3078 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -- cgit v1.2.3 From 7c617e0c5f37d2f681b3a568c3642115a32b7427 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 18 Dec 2018 22:52:12 +0100 Subject: rtc: pcf8523: Add rv8523 compatible The Microcrystal RV-8523 is compatible with the PCF8523. Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/rtc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc.txt b/Documentation/devicetree/bindings/rtc/rtc.txt index e46edab31403..b79a4794a928 100644 --- a/Documentation/devicetree/bindings/rtc/rtc.txt +++ b/Documentation/devicetree/bindings/rtc/rtc.txt @@ -49,6 +49,7 @@ isil,isl1208 Intersil ISL1208 Low Power RTC with Battery Backed SRAM isil,isl1218 Intersil ISL1218 Low Power RTC with Battery Backed SRAM isil,isl12022 Intersil ISL12022 Real-time Clock microcrystal,rv3029 Real Time Clock Module with I2C-Bus +microcrystal,rv8523 Real Time Clock nxp,pcf2127 Real-time clock nxp,pcf2129 Real-time clock nxp,pcf8523 Real-time Clock -- cgit v1.2.3 From 5938f2c8c8bbdef7cf7746a723f98623a599a0ca Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 18:12:43 +0100 Subject: dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b compatible Add a compatible string for the Mali-450 GPU on Amlogic Meson8 and Meson8b SoCs. Meson8 uses an "MP6" variant with six pixel processors while Meson8b (as cost-reduced SoC) uses an "MP2" variant with two pixel processors. Both have a reset line to bring the GPU into a well-defined state. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 3f128e4f95c6..ae63f09fda7d 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -13,6 +13,8 @@ Required properties: + allwinner,sun8i-h3-mali + allwinner,sun50i-a64-mali + allwinner,sun50i-h5-mali + + amlogic,meson8-mali + + amlogic,meson8b-mali + amlogic,meson-gxbb-mali + amlogic,meson-gxl-mali + rockchip,rk3036-mali @@ -82,6 +84,10 @@ to specify one more vendor-specific compatible, among: Required properties: * resets: phandle to the reset line for the GPU + - amlogic,meson8-mali and amlogic,meson8b-mali + Required properties: + * resets: phandle to the reset line for the GPU + - Rockchip variants: Required properties: * resets: phandle to the reset line for the GPU -- cgit v1.2.3 From ae1d2add26a4a0d34dc0615d304be2f341202e77 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 17 Dec 2018 16:31:52 +0100 Subject: soc: imx: gpcv2: handle reset clocks Some power domains handled by the GPCv2 driver need to enable the clocks for devies inside the domain, so that the reset propagation and proper power-up sequencing happens. Handle them in the same way as on GPCv1. Signed-off-by: Lucas Stach Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt index 7c947a996df1..7c7e972aaa42 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt @@ -32,6 +32,9 @@ Required properties: Optional properties: - power-supply: Power supply used to power the domain +- clocks: a number of phandles to clocks that need to be enabled during + domain power-up sequencing to ensure reset propagation into devices + located inside this power domain Example: -- cgit v1.2.3 From 4c783b010467db8eadd65da40b26f566d0d4d5cb Mon Sep 17 00:00:00 2001 From: Sven Van Asbroeck Date: Mon, 17 Dec 2018 10:47:58 -0500 Subject: dt-bindings: bus: imx-weim: document multiple address ranges per child node The imx-weim driver was patched to allow correct WEIM configuration when multiple address ranges are used in a child node. Update the dt-bindings to reflect this. Reviewed-by: Rob Herring Signed-off-by: Sven Van Asbroeck Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/bus/imx-weim.txt | 32 ++++++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt index 683eaf3aed79..dda7d6d66479 100644 --- a/Documentation/devicetree/bindings/bus/imx-weim.txt +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt @@ -47,9 +47,9 @@ Optional properties: Timing property for child nodes. It is mandatory, not optional. - fsl,weim-cs-timing: The timing array, contains timing values for the - child node. We can get the CS index from the child - node's "reg" property. The number of registers depends - on the selected chip. + child node. We get the CS indexes from the address + ranges in the child node's "reg" property. + The number of registers depends on the selected chip: For i.MX1, i.MX21 ("fsl,imx1-weim") there are two registers: CSxU, CSxL. For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim") @@ -80,3 +80,29 @@ Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: 0x0000c000 0x1404a38e 0x00000000>; }; }; + +Example for an imx6q-based board, a multi-chipselect device connected to WEIM: + +In this case, both chip select 0 and 1 will be configured with the same timing +array values. + + weim: weim@21b8000 { + compatible = "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + clocks = <&clks 196>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x02000000 + 1 0 0x0a000000 0x02000000 + 2 0 0x0c000000 0x02000000 + 3 0 0x0e000000 0x02000000>; + fsl,weim-cs-gpr = <&gpr>; + + acme@0 { + compatible = "acme,whatever"; + reg = <0 0 0x100>, <0 0x400000 0x800>, + <1 0x400000 0x800>; + fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100 + 0x00000000 0xa0000240 0x00000000>; + }; + }; -- cgit v1.2.3 From 823868fceae3bac07cf5eccb128d6916e7a5ae9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Fri, 21 Dec 2018 18:32:57 +0100 Subject: pinctrl: armada-37xx: Correct mpp definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a cleanup and fix of the patch by Ken Ma . Fix the mpp definitions according to newest revision of the specification: - northbridge: fix pmic1 gpio number to 7 fix pmic0 gpio number to 6 - southbridge split pcie1 group bit mask to BIT(5) and BIT(9) fix ptp group bit mask to BIT(11) | BIT(12) | BIT(13) add smi group with bit mask BIT(4) [gregory: split the pcie group in 2, as at hardware level they can be configured separately] Signed-off-by: Marek Behún Signed-off-by: Gregory CLEMENT Tested-by: Miquel Raynal Signed-off-by: Linus Walleij --- .../bindings/pinctrl/marvell,armada-37xx-pinctrl.txt | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt index c7c088d2dd50..f69f82741cae 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt @@ -58,11 +58,11 @@ group pwm3 - functions pwm, gpio group pmic1 - - pin 17 + - pin 7 - functions pmic, gpio group pmic0 - - pin 16 + - pin 6 - functions pmic, gpio group i2c2 @@ -112,17 +112,25 @@ group usb2_drvvbus1 - functions drvbus, gpio group sdio_sb - - pins 60-64 + - pins 60-65 - functions sdio, gpio group rgmii - - pins 42-55 + - pins 42-53 - functions mii, gpio group pcie1 - - pins 39-40 + - pins 39 + - functions pcie, gpio + +group pcie1_clkreq + - pins 40 - functions pcie, gpio +group smi + - pins 54-55 + - functions smi, gpio + group ptp - pins 56-58 - functions ptp, gpio -- cgit v1.2.3 From 3fbb9a8d79a84bf549979cad5511e202098d0aaa Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 21 Dec 2018 18:32:59 +0100 Subject: pinctrl: dt-bindings: Fix the armada-37xx documentation While it was possible to configure the PCIe1 Wakeup pin, it was missing in the bidding, let's document it. Signed-off-by: Gregory CLEMENT Tested-by: Miquel Raynal Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt index f69f82741cae..38dc56a57760 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt @@ -127,12 +127,16 @@ group pcie1_clkreq - pins 40 - functions pcie, gpio +group pcie1_wakeup + - pins 41 + - functions pcie, gpio + group smi - pins 54-55 - functions smi, gpio group ptp - - pins 56-58 + - pins 56 - functions ptp, gpio group ptp_clk -- cgit v1.2.3 From ef4efa14560adf7cdc77022c86e659d910c5c6fc Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Fri, 4 Jan 2019 22:56:56 +0100 Subject: dt-bindings: marvell,mmp2: fix typos in bindings doc A pair of rather trivial ones. Signed-off-by: Lubomir Rintel Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/clock/marvell,mmp2.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt index af376a01f2b7..23b52dc02266 100644 --- a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt +++ b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt @@ -18,4 +18,4 @@ Required Properties: Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. -All these identifier could be found in . +All these identifiers could be found in . -- cgit v1.2.3 From 8217724eb7c51bbec351b23cbc924577b2f4b8e6 Mon Sep 17 00:00:00 2001 From: Otto Sabart Date: Wed, 9 Jan 2019 00:46:55 +0100 Subject: doc: bindings: fix bad reference to ARM CPU bindings The primecell.txt and cpus.txt files were converted into YAML. This patch updates old references with new ones. Fixes: d3c207eeb905 ("dt-bindings: arm: Convert primecell binding to json-schema") Fixes: 672951cbd1b7 ("dt-bindings: arm: Convert cpu binding to json-schema") Signed-off-by: Otto Sabart Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/cpu-capacity.txt | 2 +- Documentation/devicetree/bindings/arm/idle-states.txt | 2 +- Documentation/devicetree/bindings/arm/sp810.txt | 2 +- Documentation/devicetree/bindings/arm/topology.txt | 2 +- Documentation/devicetree/bindings/display/arm,pl11x.txt | 2 +- Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpu-capacity.txt b/Documentation/devicetree/bindings/arm/cpu-capacity.txt index 84262cdb8d29..96fa46cb133c 100644 --- a/Documentation/devicetree/bindings/arm/cpu-capacity.txt +++ b/Documentation/devicetree/bindings/arm/cpu-capacity.txt @@ -235,4 +235,4 @@ cpus { =========================================== [1] ARM Linux Kernel documentation - CPUs bindings - Documentation/devicetree/bindings/arm/cpus.txt + Documentation/devicetree/bindings/arm/cpus.yaml diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt index 8f0937db55c5..45730ba60af5 100644 --- a/Documentation/devicetree/bindings/arm/idle-states.txt +++ b/Documentation/devicetree/bindings/arm/idle-states.txt @@ -684,7 +684,7 @@ cpus { =========================================== [1] ARM Linux Kernel documentation - CPUs bindings - Documentation/devicetree/bindings/arm/cpus.txt + Documentation/devicetree/bindings/arm/cpus.yaml [2] ARM Linux Kernel documentation - PSCI bindings Documentation/devicetree/bindings/arm/psci.txt diff --git a/Documentation/devicetree/bindings/arm/sp810.txt b/Documentation/devicetree/bindings/arm/sp810.txt index 1b2ab1ff5587..46652bf65147 100644 --- a/Documentation/devicetree/bindings/arm/sp810.txt +++ b/Documentation/devicetree/bindings/arm/sp810.txt @@ -4,7 +4,7 @@ SP810 System Controller Required properties: - compatible: standard compatible string for a Primecell peripheral, - see Documentation/devicetree/bindings/arm/primecell.txt + see Documentation/devicetree/bindings/arm/primecell.yaml for more details should be: "arm,sp810", "arm,primecell" diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/arm/topology.txt index de9eb0486630..b0d80c0fb265 100644 --- a/Documentation/devicetree/bindings/arm/topology.txt +++ b/Documentation/devicetree/bindings/arm/topology.txt @@ -472,4 +472,4 @@ cpus { =============================================================================== [1] ARM Linux kernel documentation - Documentation/devicetree/bindings/arm/cpus.txt + Documentation/devicetree/bindings/arm/cpus.yaml diff --git a/Documentation/devicetree/bindings/display/arm,pl11x.txt b/Documentation/devicetree/bindings/display/arm,pl11x.txt index ef89ab46b2c9..572fa2773ec4 100644 --- a/Documentation/devicetree/bindings/display/arm,pl11x.txt +++ b/Documentation/devicetree/bindings/display/arm,pl11x.txt @@ -1,6 +1,6 @@ * ARM PrimeCell Color LCD Controller PL110/PL111 -See also Documentation/devicetree/bindings/arm/primecell.txt +See also Documentation/devicetree/bindings/arm/primecell.yaml Required properties: diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index b83bb8249074..a3be5298a5eb 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -78,7 +78,7 @@ Sub-nodes: PPI affinity can be expressed as a single "ppi-partitions" node, containing a set of sub-nodes, each with the following property: - affinity: Should be a list of phandles to CPU nodes (as described in -Documentation/devicetree/bindings/arm/cpus.txt). + Documentation/devicetree/bindings/arm/cpus.yaml). GICv3 has one or more Interrupt Translation Services (ITS) that are used to route Message Signalled Interrupts (MSI) to the CPUs. -- cgit v1.2.3 From d80eebeb5dc6e0679f5d4187e9a8eb3895d13242 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Tue, 18 Dec 2018 16:01:20 +0000 Subject: dt-bindings: fsl: scu: add fallback compatible string for power domain SCU power domain can be used in the same way by IMX8QXP and IMX8QM SoCs. Let's add a "fsl,scu-pd" fallback compatible string to allow other SoCs to reuse the common part. Cc: Ulf Hansson Cc: Rob Herring Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng Reviewed-by: Rob Herring Reviewed-by: Ulf Hansson Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 27784b6edfed..4a833c93e5a5 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -58,7 +58,10 @@ This binding for the SCU power domain providers uses the generic power domain binding[2]. Required properties: -- compatible: Should be "fsl,imx8qxp-scu-pd". +- compatible: Should be one of: + "fsl,imx8qxp-scu-pd" + followed by "fsl,scu-pd" + - #power-domain-cells: Must be 1. Contains the Resource ID used by SCU commands. See detailed Resource ID list from: @@ -154,7 +157,7 @@ firmware { }; pd: imx8qx-pd { - compatible = "fsl,imx8qxp-scu-pd"; + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; #power-domain-cells = <1>; }; -- cgit v1.2.3 From 8ae170cfad9af1798522f5d9929bd2a09cc3f21a Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Tue, 18 Dec 2018 16:01:25 +0000 Subject: dt-bindings: fsl: scu: add imx8qm scu power domain support Add imx8qm scu power domain support Cc: Ulf Hansson Cc: Rob Herring Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng Reviewed-by: Rob Herring Reviewed-by: Ulf Hansson Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 4a833c93e5a5..fd2bed23e0e3 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -59,6 +59,7 @@ domain binding[2]. Required properties: - compatible: Should be one of: + "fsl,imx8qm-scu-pd", "fsl,imx8qxp-scu-pd" followed by "fsl,scu-pd" -- cgit v1.2.3 From 49ad8171e56c5ef5422837fd6fe5b6eb5091d27f Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Fri, 11 Jan 2019 13:57:05 -0600 Subject: iio: ti-ads124s08: Add DT binding documentation Adding binding documentation for Texas Instruments ADS124S08 and ADS124S06 ADC. S08 is a 12 channel ADC S06 is a 6 channel ADC Datesheet can be found here: http://www.ti.com/lit/gpn/ads124s08 Signed-off-by: Dan Murphy Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/ti-ads124s08.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/ti-ads124s08.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/ti-ads124s08.txt b/Documentation/devicetree/bindings/iio/adc/ti-ads124s08.txt new file mode 100644 index 000000000000..ecf807bb32f7 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti-ads124s08.txt @@ -0,0 +1,25 @@ +* Texas Instruments' ads124s08 and ads124s06 ADC chip + +Required properties: + - compatible : + "ti,ads124s08" + "ti,ads124s06" + - reg : spi chip select number for the device + +Recommended properties: + - spi-max-frequency : Definition as per + Documentation/devicetree/bindings/spi/spi-bus.txt + - spi-cpha : Definition as per + Documentation/devicetree/bindings/spi/spi-bus.txt + +Optional properties: + - reset-gpios : GPIO pin used to reset the device. + +Example: +adc@0 { + compatible = "ti,ads124s08"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpha; + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +}; -- cgit v1.2.3 From f4a6de855eae10bba725c6dae65fa1e351c9cd25 Mon Sep 17 00:00:00 2001 From: Mark Yao Date: Sat, 29 Dec 2018 14:33:14 +0100 Subject: drm: rockchip: vop: add rk3066 vop definitions This patch adds the rk3066 VOP definitions. The VOP or LCD Controller serves as interface between framebuffer memory and a display device (LCD panel or TV set). This SOC has two symmetrical LCDC's for a dual panel application. A LCDC has 5 display layers. Only 3 are used here. - Video layer 0 (Win0) - Video layer 1 (Win1) - OSD layer (Win2) Win0 and Win1 are exchangeable. Maximum resolution is 1920x1080. The LCDC0 output is connected to: - LCDC0 IO (without IOMUX) - HDMI TX video input The LCDC1 output is connected to: - LCDC1 IO (with IOMUX) - HDMI TX video input The HDMI TX input can switch between LCDC0 and LCDC1. Signed-off-by: Mark Yao Signed-off-by: Johan Jonker Acked-by: Rob Herring Signed-off-by: Heiko Stuebner Link: https://patchwork.freedesktop.org/patch/msgid/20181229133318.18128-4-jbx6244@gmail.com --- Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index b79e5769f0ae..4f58c5a2d195 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -10,6 +10,7 @@ Required properties: "rockchip,rk3126-vop"; "rockchip,px30-vop-lit"; "rockchip,px30-vop-big"; + "rockchip,rk3066-vop"; "rockchip,rk3188-vop"; "rockchip,rk3288-vop"; "rockchip,rk3368-vop"; -- cgit v1.2.3 From a7b4f316af857915e27633e48600c146b4978522 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 8 Jan 2019 09:14:01 +0000 Subject: dt-bindings: iio: accel: mma8452: add power supplies property The accelerometer's power supplies could be controllable on some platforms, add property "vdd/vddio" power supply to let device tree to pass phandles to the regulators to driver. Signed-off-by: Anson Huang Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/accel/mma8452.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/accel/mma8452.txt b/Documentation/devicetree/bindings/iio/accel/mma8452.txt index 2100e9af379c..e132394375a1 100644 --- a/Documentation/devicetree/bindings/iio/accel/mma8452.txt +++ b/Documentation/devicetree/bindings/iio/accel/mma8452.txt @@ -20,6 +20,10 @@ Optional properties: - interrupt-names: should contain "INT1" and/or "INT2", the accelerometer's interrupt line in use. + - vdd-supply: phandle to the regulator that provides vdd power to the accelerometer. + + - vddio-supply: phandle to the regulator that provides vddio power to the accelerometer. + Example: mma8453fc@1d { -- cgit v1.2.3 From d4c03ebe7c035a42c9ba462c7f7e051fd2bb0f73 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 3 Jan 2019 23:40:22 -0200 Subject: dt-bindings: Add vendor prefix for elgin Add elgin vendor definition as 'Elgin S/A.' Signed-off-by: Otavio Salvador Reviewed-by: Rob Herring Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..0ba5150a8f2e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -113,6 +113,7 @@ eckelmann Eckelmann AG edt Emerging Display Technologies eeti eGalax_eMPIA Technology Inc elan Elan Microelectronic Corp. +elgin Elgin S/A. embest Shenzhen Embest Technology Co., Ltd. emlid Emlid, Ltd. emmicro EM Microelectronic -- cgit v1.2.3 From 4a26c1602927c79dba91de195c3908d786addf64 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 3 Jan 2019 23:40:23 -0200 Subject: ARM: dts: rv1108: Add support for rv1108-elgin-r1 board rv1108-elgin-r1 board is based on Rockchip RV1108 SoC. Signed-off-by: Otavio Salvador Reviewed-by: Rob Herring Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index b12958bda09c..d30fff4b4676 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -60,6 +60,11 @@ properties: - const: chipspark,rayeager-px2 - const: rockchip,rk3066a + - description: Elgin RV1108 R1 + items: + - const: elgin,rv1108-r1 + - const: rockchip,rv1108 + - description: Firefly Firefly-RK3288 items: - enum: -- cgit v1.2.3 From 1b5715c602fda7b812af0e190eddcce2812e5417 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Sun, 6 Jan 2019 10:10:10 +0530 Subject: arm64: dts: rockchip: add ROCK Pi 4 DTS support ROCK Pi 4 is RK3399 based SBC from radxa.com. board has a 1G/2G/4G lpddr4, CSI, DSI, HDMI, OTG, USB 2.0, USB 3.0, 10/100/1000 RGMII Ethernet Phy, es8316 codec, POE, WIFI (for Model B only), PCIE M.2 support on board. This patch enables - HDMI Display - Console - MMC, EMMC - USB 2.0, USB-3.0 - Ethernet Signed-off-by: Akash Gajjar Signed-off-by: Pragnesh Patel Reviewed-by: Rob Herring Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index bcc60c492a12..21d09a78869d 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -322,6 +322,11 @@ properties: - const: radxa,rock - const: rockchip,rk3188 + - description: Radxa ROCK Pi 4 + items: + - const: radxa,rockpi4 + - const: rockchip,rk3399 + - description: Radxa Rock2 Square items: - const: radxa,rock2-square -- cgit v1.2.3 From 839eb8c7738ba835f6cf1a2190ffbb7108024160 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Fri, 11 Jan 2019 11:37:24 +0000 Subject: dt-bindings: arm: imx: add imx8qxp mek support i.MX 8QuadXPlus is a quad (4x) Cortex-A35 proccessor with powerful graphic and multimedia features. This patch adds imx8qxp mek board support. Cc: Shawn Guo Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a4d625d7ff4d..d34fe0749199 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -151,6 +151,12 @@ properties: - const: compulab,cl-som-imx7 - const: fsl,imx7d + - description: i.MX8QXP based Boards + items: + - enum: + - fsl,imx8qxp-mek # i.MX8QXP MEK Board + - const: fsl,imx8qxp + - description: Freescale Vybrid Platform Device Tree Bindings -- cgit v1.2.3 From 8c9fde42c5d386165d96593d8cc16fca48813589 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:20:45 +0000 Subject: dt-bindings: display: renesas: du: Document r8a774c0 bindings Document the RZ/G2E (a.k.a. r8a774c0) SoC in the R-Car DU bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart Reviewed-by: Simon Horman --- Documentation/devicetree/bindings/display/renesas,du.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt index 3c855d9f2719..aedb22b4d161 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.txt +++ b/Documentation/devicetree/bindings/display/renesas,du.txt @@ -7,6 +7,7 @@ Required Properties: - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU + - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU @@ -57,6 +58,7 @@ corresponding to each DU output. R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - - R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - - R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 - + R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 - R8A7779 (R-Car H1) DPAD 0 DPAD 1 - - R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 - R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - - -- cgit v1.2.3 From 1cac4f267b60ae9c8ce17a85c4bd9a8c6d760f83 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:20:54 +0000 Subject: dt-bindings: display: renesas: lvds: Document r8a774c0 bindings The RZ/G2E (r8a774c0) supports two LVDS channels. Extend the binding to support them. Signed-off-by: Fabrizio Castro Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart Reviewed-by: Simon Horman --- Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt index ba5469dd09f3..27a054e1bb5f 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt +++ b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt @@ -8,6 +8,7 @@ Required properties: - compatible : Shall contain one of - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders + - "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders @@ -25,7 +26,7 @@ Required properties: - clock-names: Name of the clocks. This property is model-dependent. - The functional clock, which mandatory for all models, shall be listed first, and shall be named "fck". - - On R8A77990 and R8A77995, the LVDS encoder can use the EXTAL or + - On R8A77990, R8A77995 and R8A774C0, the LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks. Those clocks are optional. When supplied they must be named "extal" and "dclkin.x" respectively, with "x" being the DU_DOTCLKIN numerical index. -- cgit v1.2.3 From df766e4a419c77283485931070e0692f64aebf8a Mon Sep 17 00:00:00 2001 From: "james qian wang (Arm Technology China)" Date: Thu, 3 Jan 2019 11:40:04 +0000 Subject: dt/bindings: drm/komeda: Add DT bindings for ARM display processor D71 Add DT bindings documentation for the ARM display processor D71 and later IPs. Changes in v4: - Deleted unnecessary address-cells, size-cells [Liviu Dudau] Changes in v3: - Deleted unnecessary property: interrupt-names. - Dropped 'ports' and moving 'port' up a level. Signed-off-by: James Qian Wang (Arm Technology China) Reviewed-by: Liviu Dudau Reviewed-by: Rob Herring [moved in the same directory as the other Arm display bindings] Signed-off-by: Liviu Dudau --- .../devicetree/bindings/display/arm,komeda.txt | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/arm,komeda.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/arm,komeda.txt b/Documentation/devicetree/bindings/display/arm,komeda.txt new file mode 100644 index 000000000000..02b226532ebd --- /dev/null +++ b/Documentation/devicetree/bindings/display/arm,komeda.txt @@ -0,0 +1,73 @@ +Device Tree bindings for Arm Komeda display driver + +Required properties: +- compatible: Should be "arm,mali-d71" +- reg: Physical base address and length of the registers in the system +- interrupts: the interrupt line number of the device in the system +- clocks: A list of phandle + clock-specifier pairs, one for each entry + in 'clock-names' +- clock-names: A list of clock names. It should contain: + - "mclk": for the main processor clock + - "pclk": for the APB interface clock +- #address-cells: Must be 1 +- #size-cells: Must be 0 + +Required properties for sub-node: pipeline@nq +Each device contains one or two pipeline sub-nodes (at least one), each +pipeline node should provide properties: +- reg: Zero-indexed identifier for the pipeline +- clocks: A list of phandle + clock-specifier pairs, one for each entry + in 'clock-names' +- clock-names: should contain: + - "pxclk": pixel clock + - "aclk": AXI interface clock + +- port: each pipeline connect to an encoder input port. The connection is + modeled using the OF graph bindings specified in + Documentation/devicetree/bindings/graph.txt + +Optional properties: + - memory-region: phandle to a node describing memory (see + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) + to be used for the framebuffer; if not present, the framebuffer may + be located anywhere in memory. + +Example: +/ { + ... + + dp0: display@c00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,mali-d71"; + reg = <0xc00000 0x20000>; + interrupts = <0 168 4>; + clocks = <&dpu_mclk>, <&dpu_aclk>; + clock-names = "mclk", "pclk"; + + dp0_pipe0: pipeline@0 { + clocks = <&fpgaosc2>, <&dpu_aclk>; + clock-names = "pxclk", "aclk"; + reg = <0>; + + port { + dp0_pipe0_out: endpoint { + remote-endpoint = <&db_dvi0_in>; + }; + }; + }; + + dp0_pipe1: pipeline@1 { + clocks = <&fpgaosc2>, <&dpu_aclk>; + clock-names = "pxclk", "aclk"; + reg = <1>; + + port { + dp0_pipe1_out: endpoint { + remote-endpoint = <&db_dvi1_in>; + }; + }; + }; + }; + ... +}; -- cgit v1.2.3 From c061ce249f9bd21a7b6effa46a99563b876f76b6 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Jan 2019 16:16:28 -0600 Subject: dt-bindings: arm: Convert PMU binding to json-schema Convert ARM PMU binding to DT schema format using json-schema. Cc: Will Deacon Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/arm/pmu.txt | 70 --------------------- Documentation/devicetree/bindings/arm/pmu.yaml | 87 ++++++++++++++++++++++++++ 2 files changed, 87 insertions(+), 70 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/pmu.txt create mode 100644 Documentation/devicetree/bindings/arm/pmu.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt deleted file mode 100644 index 13611a8199bb..000000000000 --- a/Documentation/devicetree/bindings/arm/pmu.txt +++ /dev/null @@ -1,70 +0,0 @@ -* ARM Performance Monitor Units - -ARM cores often have a PMU for counting cpu and cache events like cache misses -and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU -representation in the device tree should be done as under:- - -Required properties: - -- compatible : should be one of - "apm,potenza-pmu" - "arm,armv8-pmuv3" - "arm,cortex-a73-pmu" - "arm,cortex-a72-pmu" - "arm,cortex-a57-pmu" - "arm,cortex-a53-pmu" - "arm,cortex-a35-pmu" - "arm,cortex-a17-pmu" - "arm,cortex-a15-pmu" - "arm,cortex-a12-pmu" - "arm,cortex-a9-pmu" - "arm,cortex-a8-pmu" - "arm,cortex-a7-pmu" - "arm,cortex-a5-pmu" - "arm,arm11mpcore-pmu" - "arm,arm1176-pmu" - "arm,arm1136-pmu" - "brcm,vulcan-pmu" - "cavium,thunder-pmu" - "qcom,scorpion-pmu" - "qcom,scorpion-mp-pmu" - "qcom,krait-pmu" -- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu - interrupt (PPI) then 1 interrupt should be specified. - -Optional properties: - -- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU - nodes corresponding directly to the affinity of - the SPIs listed in the interrupts property. - - When using a PPI, specifies a list of phandles to CPU - nodes corresponding to the set of CPUs which have - a PMU of this type signalling the PPI listed in the - interrupts property, unless this is already specified - by the PPI interrupt specifier itself (in which case - the interrupt-affinity property shouldn't be present). - - This property should be present when there is more than - a single SPI. - - -- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd - events. - -- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register - (SDER) is accessible. This will cause the driver to do - any setup required that is only possible in ARMv7 secure - state. If not present the ARMv7 SDER will not be touched, - which means the PMU may fail to operate unless external - code (bootloader or security monitor) has performed the - appropriate initialisation. Note that this property is - not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux - in Non-secure state. - -Example: - -pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <100 101>; -}; diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml new file mode 100644 index 000000000000..52ae094ce330 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Performance Monitor Units + +maintainers: + - Mark Rutland + - Will Deacon + +description: |+ + ARM cores often have a PMU for counting cpu and cache events like cache misses + and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU + representation in the device tree should be done as under:- + +properties: + compatible: + items: + - enum: + - apm,potenza-pmu + - arm,armv8-pmuv3 + - arm,cortex-a73-pmu + - arm,cortex-a72-pmu + - arm,cortex-a57-pmu + - arm,cortex-a53-pmu + - arm,cortex-a35-pmu + - arm,cortex-a17-pmu + - arm,cortex-a15-pmu + - arm,cortex-a12-pmu + - arm,cortex-a9-pmu + - arm,cortex-a8-pmu + - arm,cortex-a7-pmu + - arm,cortex-a5-pmu + - arm,arm11mpcore-pmu + - arm,arm1176-pmu + - arm,arm1136-pmu + - brcm,vulcan-pmu + - cavium,thunder-pmu + - qcom,scorpion-pmu + - qcom,scorpion-mp-pmu + - qcom,krait-pmu + + interrupts: + # Don't know how many CPUs, so no constraints to specify + description: 1 per-cpu interrupt (PPI) or 1 interrupt per core. + + interrupt-affinity: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + When using SPIs, specifies a list of phandles to CPU + nodes corresponding directly to the affinity of + the SPIs listed in the interrupts property. + + When using a PPI, specifies a list of phandles to CPU + nodes corresponding to the set of CPUs which have + a PMU of this type signalling the PPI listed in the + interrupts property, unless this is already specified + by the PPI interrupt specifier itself (in which case + the interrupt-affinity property shouldn't be present). + + This property should be present when there is more than + a single SPI. + + qcom,no-pc-write: + type: boolean + description: + Indicates that this PMU doesn't support the 0xc and 0xd events. + + secure-reg-access: + type: boolean + description: + Indicates that the ARMv7 Secure Debug Enable Register + (SDER) is accessible. This will cause the driver to do + any setup required that is only possible in ARMv7 secure + state. If not present the ARMv7 SDER will not be touched, + which means the PMU may fail to operate unless external + code (bootloader or security monitor) has performed the + appropriate initialisation. Note that this property is + not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux + in Non-secure state. + +required: + - compatible + +... -- cgit v1.2.3 From 053979d2395bdf0e77f6591655e1f491611a6d89 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Jan 2019 16:19:03 -0600 Subject: regulator: dt-bindings: Convert fixed-regulator to json-schema Convert the fixed-regulator binding to DT schema format using json-schema. Cc: Liam Girdwood Cc: Mark Brown Signed-off-by: Rob Herring Signed-off-by: Mark Brown --- .../bindings/regulator/fixed-regulator.txt | 35 ----------- .../bindings/regulator/fixed-regulator.yaml | 67 ++++++++++++++++++++++ 2 files changed, 67 insertions(+), 35 deletions(-) delete mode 100644 Documentation/devicetree/bindings/regulator/fixed-regulator.txt create mode 100644 Documentation/devicetree/bindings/regulator/fixed-regulator.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt deleted file mode 100644 index 0c2a6c8a1536..000000000000 --- a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt +++ /dev/null @@ -1,35 +0,0 @@ -Fixed Voltage regulators - -Required properties: -- compatible: Must be "regulator-fixed"; -- regulator-name: Defined in regulator.txt as optional, but required here. - -Optional properties: -- gpio: gpio to use for enable control -- startup-delay-us: startup time in microseconds -- enable-active-high: Polarity of GPIO is Active high -If this property is missing, the default assumed is Active low. -- gpio-open-drain: GPIO is open drain type. - If this property is missing then default assumption is false. --vin-supply: Input supply name. - -Any property defined as part of the core regulator -binding, defined in regulator.txt, can also be used. -However a fixed voltage regulator is expected to have the -regulator-min-microvolt and regulator-max-microvolt -to be the same. - -Example: - - abc: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 16 0>; - startup-delay-us = <70000>; - enable-active-high; - regulator-boot-on; - gpio-open-drain; - vin-supply = <&parent_reg>; - }; diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml b/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml new file mode 100644 index 000000000000..a7607b0baab7 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Fixed Voltage regulators + +maintainers: + - Liam Girdwood + - Mark Brown + +description: + Any property defined as part of the core regulator binding, defined in + regulator.txt, can also be used. However a fixed voltage regulator is + expected to have the regulator-min-microvolt and regulator-max-microvolt + to be the same. + +properties: + compatible: + const: regulator-fixed + + regulator-name: true + + gpio: + description: gpio to use for enable control + maxItems: 1 + + startup-delay-us: + description: startup time in microseconds + $ref: /schemas/types.yaml#/definitions/uint32 + + enable-active-high: + description: + Polarity of GPIO is Active high. If this property is missing, + the default assumed is Active low. + type: boolean + + gpio-open-drain: + description: + GPIO is open drain type. If this property is missing then default + assumption is false. + type: boolean + + vin-supply: + description: Input supply phandle. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - regulator-name + +examples: + - | + abc: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 16 0>; + startup-delay-us = <70000>; + enable-active-high; + regulator-boot-on; + gpio-open-drain; + vin-supply = <&parent_reg>; + }; +... -- cgit v1.2.3 From 8c6e7fd9ac7960c7ca129678c75bdb599f1c9968 Mon Sep 17 00:00:00 2001 From: Christophe Kerello Date: Fri, 14 Dec 2018 10:58:06 +0100 Subject: dt-bindings: mtd: stm32_fmc2: add STM32 FMC2 NAND controller documentation This patch adds the documentation of the device tree bindings for the STM32 FMC2 NAND controller. Signed-off-by: Christophe Kerello Reviewed-by: Boris Brezillon Signed-off-by: Miquel Raynal --- .../devicetree/bindings/mtd/stm32-fmc2-nand.txt | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/stm32-fmc2-nand.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/stm32-fmc2-nand.txt b/Documentation/devicetree/bindings/mtd/stm32-fmc2-nand.txt new file mode 100644 index 000000000000..ad2bef826582 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/stm32-fmc2-nand.txt @@ -0,0 +1,61 @@ +STMicroelectronics Flexible Memory Controller 2 (FMC2) +NAND Interface + +Required properties: +- compatible: Should be one of: + * st,stm32mp15-fmc2 +- reg: NAND flash controller memory areas. + First region contains the register location. + Regions 2 to 4 respectively contain the data, command, + and address space for CS0. + Regions 5 to 7 contain the same areas for CS1. +- interrupts: The interrupt number +- pinctrl-0: Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt) +- clocks: The clock needed by the NAND flash controller + +Optional properties: +- resets: Reference to a reset controller asserting the FMC controller +- dmas: DMA specifiers (see: dma/stm32-mdma.txt) +- dma-names: Must be "tx", "rx" and "ecc" + +* NAND device bindings: + +Required properties: +- reg: describes the CS lines assigned to the NAND device. + +Optional properties: +- nand-on-flash-bbt: see nand.txt +- nand-ecc-strength: see nand.txt +- nand-ecc-step-size: see nand.txt + +The following ECC strength and step size are currently supported: + - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming) + - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4) + - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) (default) + +Example: + + fmc: nand-controller@58002000 { + compatible = "st,stm32mp15-fmc2"; + reg = <0x58002000 0x1000>, + <0x80000000 0x1000>, + <0x88010000 0x1000>, + <0x88020000 0x1000>, + <0x81000000 0x1000>, + <0x89010000 0x1000>, + <0x89020000 0x1000>; + interrupts = ; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + pinctrl-names = "default"; + pinctrl-0 = <&fmc_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + }; + }; -- cgit v1.2.3 From 35d6808221bd22005839ded36ddae381fe08e381 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 11 Jan 2019 06:22:40 +0000 Subject: dt-bindings: fsl: add imx7ulp system integration module binding Add i.MX7ULP system integration module (SIM) binding. Signed-off-by: Anson Huang Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../bindings/arm/freescale/fsl,imx7ulp-sim.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt new file mode 100644 index 000000000000..7d0c7f002401 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt @@ -0,0 +1,16 @@ +Freescale i.MX7ULP System Integration Module +---------------------------------------------- +The system integration module (SIM) provides system control and chip configuration +registers. In this module, chip revision information is located in JTAG ID register, +and a set of registers have been made available in DGO domain for SW use, with the +objective to maintain its value between system resets. + +Required properties: +- compatible: Should be "fsl,imx7ulp-sim". +- reg: Specifies base physical address and size of the register sets. + +Example: +sim: sim@410a3000 { + compatible = "fsl,imx7ulp-sim", "syscon"; + reg = <0x410a3000 0x1000>; +}; -- cgit v1.2.3 From 590ce401c207fd944827eb5aa5e87d834eddb149 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Sun, 13 Jan 2019 09:56:48 +0100 Subject: dt-bindings: net: dsa: ksz9477: fix indentation for switch spi bindings Switch bindings for spi managed mode are using spaces instead of tabs. Fix them to get a file with a proper kernel indentation style. Reviewed-by: Florian Fainelli Signed-off-by: Sergio Paracuellos Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/dsa/ksz.txt | 102 +++++++++++----------- 1 file changed, 51 insertions(+), 51 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dsa/ksz.txt b/Documentation/devicetree/bindings/net/dsa/ksz.txt index 0f407fb371ce..8d58c2a7de39 100644 --- a/Documentation/devicetree/bindings/net/dsa/ksz.txt +++ b/Documentation/devicetree/bindings/net/dsa/ksz.txt @@ -19,58 +19,58 @@ Examples: Ethernet switch connected via SPI to the host, CPU port wired to eth0: - eth0: ethernet@10001000 { - fixed-link { - speed = <1000>; - full-duplex; - }; - }; + eth0: ethernet@10001000 { + fixed-link { + speed = <1000>; + full-duplex; + }; + }; - spi1: spi@f8008000 { - pinctrl-0 = <&pinctrl_spi_ksz>; - cs-gpios = <&pioC 25 0>; - id = <1>; + spi1: spi@f8008000 { + pinctrl-0 = <&pinctrl_spi_ksz>; + cs-gpios = <&pioC 25 0>; + id = <1>; - ksz9477: ksz9477@0 { - compatible = "microchip,ksz9477"; - reg = <0>; + ksz9477: ksz9477@0 { + compatible = "microchip,ksz9477"; + reg = <0>; - spi-max-frequency = <44000000>; - spi-cpha; - spi-cpol; + spi-max-frequency = <44000000>; + spi-cpha; + spi-cpol; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - label = "lan1"; - }; - port@1 { - reg = <1>; - label = "lan2"; - }; - port@2 { - reg = <2>; - label = "lan3"; - }; - port@3 { - reg = <3>; - label = "lan4"; - }; - port@4 { - reg = <4>; - label = "lan5"; - }; - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð0>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + label = "lan1"; + }; + port@1 { + reg = <1>; + label = "lan2"; + }; + port@2 { + reg = <2>; + label = "lan3"; + }; + port@3 { + reg = <3>; + label = "lan4"; + }; + port@4 { + reg = <4>; + label = "lan5"; + }; + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <ð0>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; -- cgit v1.2.3 From 993a815dcbb2d13c2a2fe6b89612361dd7f0a4df Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 3 Dec 2018 17:13:10 +0100 Subject: dt-bindings: panel: Add missing .txt suffix All other files in that directory have a .txt suffix, so add one for consistency. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring Link: https://patchwork.freedesktop.org/patch/msgid/20181203161310.15438-1-thierry.reding@gmail.com --- .../devicetree/bindings/display/panel/auo,g101evn010 | 12 ------------ .../devicetree/bindings/display/panel/auo,g101evn010.txt | 12 ++++++++++++ 2 files changed, 12 insertions(+), 12 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/panel/auo,g101evn010 create mode 100644 Documentation/devicetree/bindings/display/panel/auo,g101evn010.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/auo,g101evn010 b/Documentation/devicetree/bindings/display/panel/auo,g101evn010 deleted file mode 100644 index bc6a0c858e23..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,g101evn010 +++ /dev/null @@ -1,12 +0,0 @@ -AU Optronics Corporation 10.1" (1280x800) color TFT LCD panel - -Required properties: -- compatible: should be "auo,g101evn010" -- power-supply: as specified in the base binding - -Optional properties: -- backlight: as specified in the base binding -- enable-gpios: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/auo,g101evn010.txt b/Documentation/devicetree/bindings/display/panel/auo,g101evn010.txt new file mode 100644 index 000000000000..bc6a0c858e23 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/auo,g101evn010.txt @@ -0,0 +1,12 @@ +AU Optronics Corporation 10.1" (1280x800) color TFT LCD panel + +Required properties: +- compatible: should be "auo,g101evn010" +- power-supply: as specified in the base binding + +Optional properties: +- backlight: as specified in the base binding +- enable-gpios: as specified in the base binding + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- cgit v1.2.3 From 24ef3b6e22fe7268603ac435868e9c99dae12cda Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vok=C3=A1=C4=8D=20Michal?= Date: Tue, 15 Jan 2019 14:22:44 +0000 Subject: dt-bindings: arm: Add Y Soft IOTA Draco, Hydra and Ursa boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are i.MX6DualLite/Solo based single board computers used in various Y Soft products. Cc: Andrew Lunn Signed-off-by: Michal Vokáč Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d34fe0749199..8a571c7dc11a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -94,6 +94,9 @@ properties: - fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 + - ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board + - ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board + - ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board - const: fsl,imx6dl - description: i.MX6SL based Boards -- cgit v1.2.3 From 270a60bcc8f23254d749987f3d2acb79ea5c599e Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 21 Dec 2018 14:46:30 +0100 Subject: dt-bindings: stmpe: Reformatting parameter list and use tabs only This patch reformats the parameter list for stmpe device in a table-style so it is more clear to read. Signed-off-by: Philippe Schenker Reviewed-by: Rob Herring Signed-off-by: Lee Jones --- .../bindings/input/touchscreen/stmpe.txt | 64 ++++++++++++++++------ Documentation/devicetree/bindings/mfd/stmpe.txt | 14 ++--- 2 files changed, 53 insertions(+), 25 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt b/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt index 127baa31a77a..bf66a55a7de5 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt @@ -5,24 +5,52 @@ Required properties: - compatible: "st,stmpe-ts" Optional properties: -- st,sample-time: ADC converstion time in number of clock. (0 -> 36 clocks, 1 -> - 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks, 4 -> 80 clocks, 5 -> 96 clocks, 6 - -> 144 clocks), recommended is 4. -- st,mod-12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC) -- st,ref-sel: ADC reference source (0 -> internal reference, 1 -> external - reference) -- st,adc-freq: ADC Clock speed (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz) -- st,ave-ctrl: Sample average control (0 -> 1 sample, 1 -> 2 samples, 2 -> 4 - samples, 3 -> 8 samples) -- st,touch-det-delay: Touch detect interrupt delay (0 -> 10 us, 1 -> 50 us, 2 -> - 100 us, 3 -> 500 us, 4-> 1 ms, 5 -> 5 ms, 6 -> 10 ms, 7 -> 50 ms) recommended - is 3 -- st,settling: Panel driver settling time (0 -> 10 us, 1 -> 100 us, 2 -> 500 us, 3 - -> 1 ms, 4 -> 5 ms, 5 -> 10 ms, 6 for 50 ms, 7 -> 100 ms) recommended is 2 -- st,fraction-z: Length of the fractional part in z (fraction-z ([0..7]) = Count of - the fractional part) recommended is 7 -- st,i-drive: current limit value of the touchscreen drivers (0 -> 20 mA typical 35 - mA max, 1 -> 50 mA typical 80 mA max) +- st,sample-time : ADC conversion time in number of clock. + 0 -> 36 clocks + 1 -> 44 clocks + 2 -> 56 clocks + 3 -> 64 clocks + 4 -> 80 clocks (recommended) + 5 -> 96 clocks + 6 -> 144 clocks +- st,mod-12b : ADC Bit mode + 0 -> 10bit ADC + 1 -> 12bit ADC +- st,ref-sel : ADC reference source + 0 -> internal + 1 -> external +- st,adc-freq : ADC Clock speed + 0 -> 1.625 MHz + 1 -> 3.25 MHz + 2 || 3 -> 6.5 MHz +- st,ave-ctrl : Sample average control + 0 -> 1 sample + 1 -> 2 samples + 2 -> 4 samples + 3 -> 8 samples +- st,touch-det-delay : Touch detect interrupt delay (recommended is 3) + 0 -> 10 us + 1 -> 50 us + 2 -> 100 us + 3 -> 500 us + 4 -> 1 ms + 5 -> 5 ms + 6 -> 10 ms + 7 -> 50 ms +- st,settling : Panel driver settling time (recommended is 2) + 0 -> 10 us + 1 -> 100 us + 2 -> 500 us + 3 -> 1 ms + 4 -> 5 ms + 5 -> 10 ms + 6 -> 50 ms + 7 -> 100 ms +- st,fraction-z : Length of the fractional part in z (recommended is 7) + (fraction-z ([0..7]) = Count of the fractional part) +- st,i-drive : current limit value of the touchscreen drivers + 0 -> 20 mA (typical 35mA max) + 1 -> 50 mA (typical 80 mA max) Node name must be stmpe_touchscreen and should be child node of stmpe node to which it belongs. diff --git a/Documentation/devicetree/bindings/mfd/stmpe.txt b/Documentation/devicetree/bindings/mfd/stmpe.txt index c797c05cd3c2..a46e7177195d 100644 --- a/Documentation/devicetree/bindings/mfd/stmpe.txt +++ b/Documentation/devicetree/bindings/mfd/stmpe.txt @@ -4,15 +4,15 @@ STMPE is an MFD device which may expose the following inbuilt devices: gpio, keypad, touchscreen, adc, pwm, rotator. Required properties: - - compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]" - - reg : I2C/SPI address of the device + - compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]" + - reg : I2C/SPI address of the device Optional properties: - - interrupts : The interrupt outputs from the controller - - interrupt-controller : Marks the device node as an interrupt controller - - wakeup-source : Marks the input device as wakable - - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024 - - irq-gpio : If present, which GPIO to use for event IRQ + - interrupts : The interrupt outputs from the controller + - interrupt-controller : Marks the device node as an interrupt controller + - wakeup-source : Marks the input device as wakable + - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024 + - irq-gpio : If present, which GPIO to use for event IRQ Example: -- cgit v1.2.3 From 81cdab79818988d27d8aeb162b7988c9e6dde936 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 21 Dec 2018 14:46:35 +0100 Subject: iio: adc: add STMPE ADC devicetree bindings This adds the devicetree bindings for the STMPE ADC. This also corrects a typo in st,sample-time it is rather "6 -> 124 clocks" according to the datasheet and not 144. We need to use the naming stmpe_adc in devicetree because this is given by the mfd device. Signed-off-by: Stefan Agner Signed-off-by: Max Krummenacher Signed-off-by: Philippe Schenker Reviewed-by: Jonathan Cameron Reviewed-by: Rob Herring Signed-off-by: Lee Jones --- .../devicetree/bindings/iio/adc/stmpe-adc.txt | 21 ++++++ .../bindings/input/touchscreen/stmpe.txt | 88 ++++++++++++++++------ Documentation/devicetree/bindings/mfd/stmpe.txt | 14 ++++ 3 files changed, 98 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/adc/stmpe-adc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/stmpe-adc.txt b/Documentation/devicetree/bindings/iio/adc/stmpe-adc.txt new file mode 100644 index 000000000000..480e66422625 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/stmpe-adc.txt @@ -0,0 +1,21 @@ +STMPE ADC driver +---------------- + +Required properties: + - compatible: "st,stmpe-adc" + +Optional properties: +Note that the ADC is shared with the STMPE touchscreen. ADC related settings +have to be done in the mfd. +- st,norequest-mask: bitmask specifying which ADC channels should _not_ be + requestable due to different usage (e.g. touch) + +Node name must be stmpe_adc and should be child node of stmpe node to +which it belongs. + +Example: + + stmpe_adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x0F>; /* dont use ADC CH3-0 */ + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt b/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt index bf66a55a7de5..c549924603d2 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt @@ -5,24 +5,6 @@ Required properties: - compatible: "st,stmpe-ts" Optional properties: -- st,sample-time : ADC conversion time in number of clock. - 0 -> 36 clocks - 1 -> 44 clocks - 2 -> 56 clocks - 3 -> 64 clocks - 4 -> 80 clocks (recommended) - 5 -> 96 clocks - 6 -> 144 clocks -- st,mod-12b : ADC Bit mode - 0 -> 10bit ADC - 1 -> 12bit ADC -- st,ref-sel : ADC reference source - 0 -> internal - 1 -> external -- st,adc-freq : ADC Clock speed - 0 -> 1.625 MHz - 1 -> 3.25 MHz - 2 || 3 -> 6.5 MHz - st,ave-ctrl : Sample average control 0 -> 1 sample 1 -> 2 samples @@ -52,20 +34,76 @@ Optional properties: 0 -> 20 mA (typical 35mA max) 1 -> 50 mA (typical 80 mA max) +Optional properties common with MFD (deprecated): + - st,sample-time : ADC conversion time in number of clock. + 0 -> 36 clocks + 1 -> 44 clocks + 2 -> 56 clocks + 3 -> 64 clocks + 4 -> 80 clocks (recommended) + 5 -> 96 clocks + 6 -> 124 clocks + - st,mod-12b : ADC Bit mode + 0 -> 10bit ADC + 1 -> 12bit ADC + - st,ref-sel : ADC reference source + 0 -> internal + 1 -> external + - st,adc-freq : ADC Clock speed + 0 -> 1.625 MHz + 1 -> 3.25 MHz + 2 || 3 -> 6.5 MHz + Node name must be stmpe_touchscreen and should be child node of stmpe node to which it belongs. +Note that common ADC settings of stmpe_touchscreen (child) will take precedence +over the settings done in MFD. + Example: +stmpe811@41 { + compatible = "st,stmpe811"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio4>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + /* Common ADC settings */ + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + stmpe_touchscreen { compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; + reg = <0>; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 7 length fractional part in z */ st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ st,i-drive = <1>; }; + stmpe_adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x0F>; + }; +}; diff --git a/Documentation/devicetree/bindings/mfd/stmpe.txt b/Documentation/devicetree/bindings/mfd/stmpe.txt index a46e7177195d..d4408a417193 100644 --- a/Documentation/devicetree/bindings/mfd/stmpe.txt +++ b/Documentation/devicetree/bindings/mfd/stmpe.txt @@ -14,6 +14,20 @@ Optional properties: - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024 - irq-gpio : If present, which GPIO to use for event IRQ +Optional properties for devices with touch and ADC (STMPE811|STMPE610): + - st,sample-time : ADC conversion time in number of clock. + 0 -> 36 clocks 4 -> 80 clocks (recommended) + 1 -> 44 clocks 5 -> 96 clocks + 2 -> 56 clocks 6 -> 124 clocks + 3 -> 64 clocks + - st,mod-12b : ADC Bit mode + 0 -> 10bit ADC 1 -> 12bit ADC + - st,ref-sel : ADC reference source + 0 -> internal 1 -> external + - st,adc-freq : ADC Clock speed + 0 -> 1.625 MHz 2 || 3 -> 6.5 MHz + 1 -> 3.25 MHz + Example: stmpe1601: stmpe1601@40 { -- cgit v1.2.3 From 53f986accf34d4428b90b26086b9571ea653b920 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 12 Dec 2018 23:38:49 +0300 Subject: dt-bindings: memory: tegra: Squash tegra20-gart into tegra20-mc Splitting GART and Memory Controller wasn't a good decision that was made back in the day. Given that the GART driver wasn't ever been used by anything in the kernel, we decided that it will be better to correct the mistakes of the past and merge two bindings into a single one. As a result there is a DT ABI change for the Memory Controller that allows not to break newer kernels using older DT and not to break older kernels using newer DT, that is done by changing the 'compatible' of the node to 'tegra20-mc-gart' and adding a new-required clock property. The new clock property also puts the tegra20-mc binding in line with the bindings of the later Tegra generations. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Acked-by: Thierry Reding Signed-off-by: Joerg Roedel --- .../bindings/iommu/nvidia,tegra20-gart.txt | 14 ----------- .../memory-controllers/nvidia,tegra20-mc.txt | 27 +++++++++++++++------- 2 files changed, 19 insertions(+), 22 deletions(-) delete mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt deleted file mode 100644 index 099d9362ebc1..000000000000 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt +++ /dev/null @@ -1,14 +0,0 @@ -NVIDIA Tegra 20 GART - -Required properties: -- compatible: "nvidia,tegra20-gart" -- reg: Two pairs of cells specifying the physical address and size of - the memory controller registers and the GART aperture respectively. - -Example: - - gart { - compatible = "nvidia,tegra20-gart"; - reg = <0x7000f024 0x00000018 /* controller registers */ - 0x58000000 0x02000000>; /* GART aperture */ - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt index 7d60a50a4fa1..e55328237df4 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt @@ -1,26 +1,37 @@ NVIDIA Tegra20 MC(Memory Controller) Required properties: -- compatible : "nvidia,tegra20-mc" -- reg : Should contain 2 register ranges(address and length); see the - example below. Note that the MC registers are interleaved with the - GART registers, and hence must be represented as multiple ranges. +- compatible : "nvidia,tegra20-mc-gart" +- reg : Should contain 2 register ranges: physical base address and length of + the controller's registers and the GART aperture respectively. +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - mc: the module's clock input - interrupts : Should contain MC General interrupt. - #reset-cells : Should be 1. This cell represents memory client module ID. The assignments may be found in header file or in the TRM documentation. +- #iommu-cells: Should be 0. This cell represents the number of cells in an + IOMMU specifier needed to encode an address. GART supports only a single + address space that is shared by all devices, therefore no additional + information needed for the address encoding. Example: mc: memory-controller@7000f000 { - compatible = "nvidia,tegra20-mc"; - reg = <0x7000f000 0x024 - 0x7000f03c 0x3c4>; - interrupts = <0 77 0x04>; + compatible = "nvidia,tegra20-mc-gart"; + reg = <0x7000f000 0x400 /* controller registers */ + 0x58000000 0x02000000>; /* GART aperture */ + clocks = <&tegra_car TEGRA20_CLK_MC>; + clock-names = "mc"; + interrupts = ; #reset-cells = <1>; + #iommu-cells = <0>; }; video-codec@6001a000 { compatible = "nvidia,tegra20-vde"; ... resets = <&mc TEGRA20_MC_RESET_VDE>; + iommus = <&mc>; }; -- cgit v1.2.3 From 3eafbd3a7745e1579665cbb8c3959a74a666b8c9 Mon Sep 17 00:00:00 2001 From: Pascal PAILLET-LME Date: Mon, 14 Jan 2019 10:05:15 +0000 Subject: dt-bindings: mfd: Document STPMIC1 STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10 regulators, 3 power switches, a watchdog and an input for a power on key. Signed-off-by: Pascal Paillet Reviewed-by: Rob Herring Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/st,stpmic1.txt | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/st,stpmic1.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/st,stpmic1.txt b/Documentation/devicetree/bindings/mfd/st,stpmic1.txt new file mode 100644 index 000000000000..afd45c089585 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/st,stpmic1.txt @@ -0,0 +1,61 @@ +* STMicroelectronics STPMIC1 Power Management IC + +Required properties: +- compatible: : "st,stpmic1" +- reg: : The I2C slave address for the STPMIC1 chip. +- interrupts: : The interrupt line the device is connected to. +- #interrupt-cells: : Should be 1. +- interrupt-controller: : Marks the device node as an interrupt controller. + Interrupt numbers are defined at + dt-bindings/mfd/st,stpmic1.h. + +STPMIC1 consists in a varied group of sub-devices. +Each sub-device binding is be described in own documentation file. + +Device Description +------ ------------ +st,stpmic1-onkey : Power on key, see ../input/st,stpmic1-onkey.txt +st,stpmic1-regulators : Regulators, see ../regulator/st,stpmic1-regulator.txt +st,stpmic1-wdt : Watchdog, see ../watchdog/st,stpmic1-wdt.txt + +Example: + +#include + +pmic: pmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupt-parent = <&gpioa>; + interrupts = <0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = ,; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + }; + + regulators { + compatible = "st,stpmic1-regulators"; + + vdd_core: buck1 { + regulator-name = "vdd_core"; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1200000>; + }; + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-pull-down; + }; + }; -- cgit v1.2.3 From d1f1c76896c012e71ea76e48fc039df72cc30a69 Mon Sep 17 00:00:00 2001 From: Pascal PAILLET-LME Date: Mon, 14 Jan 2019 10:05:16 +0000 Subject: dt-bindings: input: Document STPMIC1 PMIC onkey The STPMIC1 PMIC is able to manage an onkey button. It can be configured to shut-down the power supplies on a long key-press with an adjustable duration. Signed-off-by: Pascal Paillet Reviewed-by: Rob Herring Signed-off-by: Lee Jones --- .../devicetree/bindings/input/st,stpmic1-onkey.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/st,stpmic1-onkey.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/st,stpmic1-onkey.txt b/Documentation/devicetree/bindings/input/st,stpmic1-onkey.txt new file mode 100644 index 000000000000..4494613ae7ad --- /dev/null +++ b/Documentation/devicetree/bindings/input/st,stpmic1-onkey.txt @@ -0,0 +1,28 @@ +STMicroelectronics STPMIC1 Onkey + +Required properties: + +- compatible = "st,stpmic1-onkey"; +- interrupts: interrupt line to use +- interrupt-names = "onkey-falling", "onkey-rising" + onkey-falling: happens when onkey is pressed; IT_PONKEY_F of pmic + onkey-rising: happens when onkey is released; IT_PONKEY_R of pmic + +Optional properties: + +- st,onkey-clear-cc-flag: onkey is able power on after an + over-current shutdown event. +- st,onkey-pu-inactive: onkey pull up is not active +- power-off-time-sec: Duration in seconds which the key should be kept + pressed for device to power off automatically (from 1 to 16 seconds). + see See Documentation/devicetree/bindings/input/keys.txt + +Example: + +onkey { + compatible = "st,stpmic1-onkey"; + interrupt-parent = <&pmic>; + interrupts = ,; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; +}; -- cgit v1.2.3 From 6e4531090fcddf436acf6248d3a32aa516b07075 Mon Sep 17 00:00:00 2001 From: Pascal PAILLET-LME Date: Mon, 14 Jan 2019 10:05:17 +0000 Subject: dt-bindings: watchdog: document STPMIC1 PMIC watchdog The STPMIC1 PMIC embeds a watchdog which is disabled by default. In case of watchdog, the PMIC goes off. Signed-off-by: Pascal Paillet Reviewed-by: Rob Herring Reviewed-by: Guenter Roeck Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/watchdog/st,stpmic1-wdt.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/st,stpmic1-wdt.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/st,stpmic1-wdt.txt b/Documentation/devicetree/bindings/watchdog/st,stpmic1-wdt.txt new file mode 100644 index 000000000000..7cc1407f15cb --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/st,stpmic1-wdt.txt @@ -0,0 +1,11 @@ +STMicroelectronics STPMIC1 Watchdog + +Required properties: + +- compatible : should be "st,stpmic1-wdt" + +Example: + +watchdog { + compatible = "st,stpmic1-wdt"; +}; -- cgit v1.2.3 From 4a09a91e5efd3759d28ae4708a7bcef11bee4416 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Wed, 16 Jan 2019 10:12:03 +0800 Subject: dt-bindings: mtd: mtk-quadspi: update bindings for MT7629 SoC This updates bindings for the MT7629 SPI-NOR controller. Signed-off-by: Ryder Lee Reviewed-by: Rob Herring Signed-off-by: Boris Brezillon --- Documentation/devicetree/bindings/mtd/mtk-quadspi.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt index 56d3668e2c50..a12e3b5c495d 100644 --- a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt @@ -1,4 +1,4 @@ -* Serial NOR flash controller for MTK MT81xx (and similar) +* Serial NOR flash controller for MediaTek SoCs Required properties: - compatible: For mt8173, compatible should be "mediatek,mt8173-nor", @@ -10,6 +10,7 @@ Required properties: "mediatek,mt2712-nor", "mediatek,mt8173-nor" "mediatek,mt7622-nor", "mediatek,mt8173-nor" "mediatek,mt7623-nor", "mediatek,mt8173-nor" + "mediatek,mt7629-nor", "mediatek,mt8173-nor" "mediatek,mt8173-nor" - reg: physical base address and length of the controller's register - clocks: the phandle of the clocks needed by the nor controller -- cgit v1.2.3 From 6af61a0bc43201425afa6052d24f2a67648f69d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Wed, 28 Nov 2018 21:01:44 -0500 Subject: media: dt-bindings: adv748x: make data-lanes property mandatory for CSI-2 endpoints MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CSI-2 transmitters can use a different number of lanes to transmit data. Make the data-lanes mandatory for the endpoints that describe the transmitters as no good default can be set to fallback on. Signed-off-by: Niklas Söderlund Reviewed-by: Laurent Pinchart Reviewed-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/i2c/adv748x.txt | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/adv748x.txt b/Documentation/devicetree/bindings/media/i2c/adv748x.txt index 5dddc95f9cc4..4f91686e54a6 100644 --- a/Documentation/devicetree/bindings/media/i2c/adv748x.txt +++ b/Documentation/devicetree/bindings/media/i2c/adv748x.txt @@ -48,7 +48,16 @@ are numbered as follows. TXA source 10 TXB source 11 -The digital output port nodes must contain at least one endpoint. +The digital output port nodes, when present, shall contain at least one +endpoint. Each of those endpoints shall contain the data-lanes property as +described in video-interfaces.txt. + +Required source endpoint properties: + - data-lanes: an array of physical data lane indexes + The accepted value(s) for this property depends on which of the two + sources are described. For TXA 1, 2 or 4 data lanes can be described + while for TXB only 1 data lane is valid. See video-interfaces.txt + for detailed description. Ports are optional if they are not connected to anything at the hardware level. -- cgit v1.2.3 From 9640ee1c308c1bb21c224a0cf41d9ed1b7e3a427 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 15:21:49 -0500 Subject: media: dt-bindings: rcar-csi2: Add r8a774c0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the compatible string for RZ/G2E (a.k.a. R8A774C0) to the list of supported SoCs. Signed-off-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Niklas Söderlund Reviewed-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt b/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt index 541d936b62e8..d63275e17afd 100644 --- a/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt +++ b/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt @@ -2,12 +2,13 @@ Renesas R-Car MIPI CSI-2 ------------------------ The R-Car CSI-2 receiver device provides MIPI CSI-2 capabilities for the -Renesas R-Car family of devices. It is used in conjunction with the +Renesas R-Car and RZ/G2 family of devices. It is used in conjunction with the R-Car VIN module, which provides the video capture capabilities. Mandatory properties -------------------- - compatible: Must be one or more of the following + - "renesas,r8a774c0-csi2" for the R8A774C0 device. - "renesas,r8a7795-csi2" for the R8A7795 device. - "renesas,r8a7796-csi2" for the R8A7796 device. - "renesas,r8a77965-csi2" for the R8A77965 device. -- cgit v1.2.3 From 73960b787c615b41333600e1291f6a47ff7db21c Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 15:21:59 -0500 Subject: media: dt-bindings: rcar-vin: Add R8A774C0 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the compatible string for RZ/G2E (a.k.a. R8A774C0) to the list of SoCs supported by rcar-vin driver. Signed-off-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Niklas Söderlund Reviewed-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/rcar_vin.txt | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt index 0dd84a183ca7..224a4615b418 100644 --- a/Documentation/devicetree/bindings/media/rcar_vin.txt +++ b/Documentation/devicetree/bindings/media/rcar_vin.txt @@ -7,12 +7,13 @@ family of devices. Each VIN instance has a single parallel input that supports RGB and YUV video, with both external synchronization and BT.656 synchronization for the latter. Depending on the instance the VIN input is connected to external SoC pins, or -on Gen3 platforms to a CSI-2 receiver. +on Gen3 and RZ/G2 platforms to a CSI-2 receiver. - compatible: Must be one or more of the following - "renesas,vin-r8a7743" for the R8A7743 device - "renesas,vin-r8a7744" for the R8A7744 device - "renesas,vin-r8a7745" for the R8A7745 device + - "renesas,vin-r8a774c0" for the R8A774C0 device - "renesas,vin-r8a7778" for the R8A7778 device - "renesas,vin-r8a7779" for the R8A7779 device - "renesas,vin-r8a7790" for the R8A7790 device @@ -61,10 +62,10 @@ The per-board settings Gen2 platforms: - data-enable-active: polarity of CLKENB signal, see [1] for description. Default is active high. -The per-board settings Gen3 platforms: +The per-board settings Gen3 and RZ/G2 platforms: -Gen3 platforms can support both a single connected parallel input source -from external SoC pins (port@0) and/or multiple parallel input sources +Gen3 and RZ/G2 platforms can support both a single connected parallel input +source from external SoC pins (port@0) and/or multiple parallel input sources from local SoC CSI-2 receivers (port@1) depending on SoC. - renesas,id - ID number of the VIN, VINx in the documentation. -- cgit v1.2.3 From fe367be508473dac43c3277062555d3ab2b995ec Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 14 Nov 2018 07:13:38 -0500 Subject: media: dt-bindings: media: i2c: Fix external clock frequency for OV5645 Commit "4adb0a0432f4 media: ov5645: Supported external clock is 24MHz" modified the external clock frequency to be 24MHz instead of the 23.88MHz in driver. Hence, modify the frequency value in binding. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/i2c/ov5645.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/ov5645.txt b/Documentation/devicetree/bindings/media/i2c/ov5645.txt index fd7aec9f8e24..b032abfcea36 100644 --- a/Documentation/devicetree/bindings/media/i2c/ov5645.txt +++ b/Documentation/devicetree/bindings/media/i2c/ov5645.txt @@ -37,7 +37,7 @@ Example: clocks = <&clks 200>; clock-names = "xclk"; - clock-frequency = <23880000>; + clock-frequency = <24000000>; vdddo-supply = <&camera_dovdd_1v8>; vdda-supply = <&camera_avdd_2v8>; -- cgit v1.2.3 From 961304d17a615f42c38b867640980a3390e3baa6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 9 Nov 2018 02:56:43 -0500 Subject: media: dt-bindings: media: i2c: Fix i2c address for OV5645 camera sensor The i2c address for the Omnivision OV5645 camera sensor is 0x3c. It is incorrectly mentioned as 0x78 in binding. Hence fix that. Fixes: 09c716af36e6 [media] media: i2c/ov5645: add the device tree binding document Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/i2c/ov5645.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/ov5645.txt b/Documentation/devicetree/bindings/media/i2c/ov5645.txt index b032abfcea36..72ad992f77be 100644 --- a/Documentation/devicetree/bindings/media/i2c/ov5645.txt +++ b/Documentation/devicetree/bindings/media/i2c/ov5645.txt @@ -26,9 +26,9 @@ Example: &i2c1 { ... - ov5645: ov5645@78 { + ov5645: ov5645@3c { compatible = "ovti,ov5645"; - reg = <0x78>; + reg = <0x3c>; enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; -- cgit v1.2.3 From aace50f1fd8426c8dfffd9999a7c408db3c2f40e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 30 Nov 2018 02:58:44 -0500 Subject: media: dt-bindings: media: sun6i: Separate H3 compatible from A31 The CSI controller found on the H3 (and H5) is a reduced version of the one found on the A31. It only has 1 channel, instead of 4 channels for time-multiplexed BT.656. Since the H3 is a reduced version, it cannot "fallback" to a compatible that implements more features than it supports. Split out the H3 compatible as a separate entry, with no fallback. Fixes: b7eadaa3a02a ("media: dt-bindings: media: sun6i: Add A31 and H3 compatibles") Signed-off-by: Chen-Yu Tsai Reviewed-by: Jagan Teki Reviewed-by: Rob Herring Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/sun6i-csi.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt index d4ab34f2240c..cc37cf7fd051 100644 --- a/Documentation/devicetree/bindings/media/sun6i-csi.txt +++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt @@ -6,7 +6,7 @@ Allwinner V3s SoC features a CSI module(CSI1) with parallel interface. Required properties: - compatible: value must be one of: * "allwinner,sun6i-a31-csi" - * "allwinner,sun8i-h3-csi", "allwinner,sun6i-a31-csi" + * "allwinner,sun8i-h3-csi" * "allwinner,sun8i-v3s-csi" - reg: base address and size of the memory-mapped region. - interrupts: interrupt associated to this IP -- cgit v1.2.3 From 889f4ce60ed19cfd16216e96f90e64a0c1181c0d Mon Sep 17 00:00:00 2001 From: Otto Sabart Date: Wed, 9 Jan 2019 20:07:41 +0100 Subject: doc: gpio-mvebu: fix broken reference to cp110-system-controller0.txt file The cp110-system-controller0.txt file was renamed to cp110-system-controller.txt. Fixes: 4aa5496980e4 ("dt-bindings: cp110: rename cp110 syscon file") Signed-off-by: Otto Sabart Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/gpio/gpio-mvebu.txt | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt index 38ca2201e8ae..2e097b57f170 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt @@ -14,8 +14,6 @@ Required properties: "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K SoCs (either from AP or CP), see - Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt - and Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt for specific details about the offset property. -- cgit v1.2.3 From 9eac0ae1683575375de8c63166b3596b11d3b56a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Jan 2019 13:11:40 +0100 Subject: dt-bindings: soc: qcom: Fix trivial language typos Fix few trivial language typos in bindings. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt | 2 +- Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt index 0b8cc533ca83..cf759e5f9b10 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt @@ -55,7 +55,7 @@ of these nodes are defined by the individual bindings for the specific function = EXAMPLE The following example represents the GLINK RPM node on a MSM8996 device, with the function for the "rpm_request" channel defined, which is used for -regualtors and root clocks. +regulators and root clocks. apcs_glb: mailbox@9820000 { compatible = "qcom,msm8996-apcs-hmss-global"; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt index a35af2dafdad..49e1d72d3648 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt @@ -41,12 +41,12 @@ processor ID) and a string identifier. - qcom,local-pid: Usage: required Value type: - Definition: specifies the identfier of the local endpoint of this edge + Definition: specifies the identifier of the local endpoint of this edge - qcom,remote-pid: Usage: required Value type: - Definition: specifies the identfier of the remote endpoint of this edge + Definition: specifies the identifier of the remote endpoint of this edge = SUBNODES Each SMP2P pair contain a set of inbound and outbound entries, these are -- cgit v1.2.3 From 1dd7093742517b4aa362d22eaff8eef133d876ce Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 9 Jan 2019 15:44:45 +0100 Subject: dt-bindings: leds: Add pattern initialization from Device Tree Document new led-pattern property for initialization of LED triggers. The property format is trigger-specific (except being array of integers). For pattern trigger, the explanation of pattern format was moved to a common file shared with sysfs ABI. Signed-off-by: Krzysztof Kozlowski Acked-by: Pavel Machek Reviewed-by: Rob Herring Signed-off-by: Jacek Anaszewski --- Documentation/devicetree/bindings/leds/common.txt | 12 ++++++ .../bindings/leds/leds-trigger-pattern.txt | 49 ++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/leds-trigger-pattern.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/leds/common.txt b/Documentation/devicetree/bindings/leds/common.txt index aa1399814a2a..70876ac11367 100644 --- a/Documentation/devicetree/bindings/leds/common.txt +++ b/Documentation/devicetree/bindings/leds/common.txt @@ -37,6 +37,18 @@ Optional properties for child nodes: "ide-disk" - LED indicates IDE disk activity (deprecated), in new implementations use "disk-activity" "timer" - LED flashes at a fixed, configurable rate + "pattern" - LED alters the brightness for the specified duration with one + software timer (requires "led-pattern" property) + +- led-pattern : Array of integers with default pattern for certain triggers. + Each trigger may parse this property differently: + - one-shot : two numbers specifying delay on and delay off (in ms), + - timer : two numbers specifying delay on and delay off (in ms), + - pattern : the pattern is given by a series of tuples, of + brightness and duration (in ms). The exact format is + described in: + Documentation/devicetree/bindings/leds/leds-trigger-pattern.txt + - led-max-microamp : Maximum LED supply current in microamperes. This property can be made mandatory for the board configurations diff --git a/Documentation/devicetree/bindings/leds/leds-trigger-pattern.txt b/Documentation/devicetree/bindings/leds/leds-trigger-pattern.txt new file mode 100644 index 000000000000..d3696680bfc8 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-trigger-pattern.txt @@ -0,0 +1,49 @@ +* Pattern format for LED pattern trigger + +The pattern is given by a series of tuples, of brightness and duration (ms). +The LED is expected to traverse the series and each brightness value for the +specified duration. Duration of 0 means brightness should immediately change to +new value, and writing malformed pattern deactivates any active one. + +1. For gradual dimming, the dimming interval now is set as 50 milliseconds. So +the tuple with duration less than dimming interval (50ms) is treated as a step +change of brightness, i.e. the subsequent brightness will be applied without +adding intervening dimming intervals. + +The gradual dimming format of the software pattern values should be: +"brightness_1 duration_1 brightness_2 duration_2 brightness_3 duration_3 ...". +For example (using sysfs interface): + +echo 0 1000 255 2000 > pattern + +It will make the LED go gradually from zero-intensity to max (255) intensity in +1000 milliseconds, then back to zero intensity in 2000 milliseconds: + +LED brightness + ^ +255-| / \ / \ / + | / \ / \ / + | / \ / \ / + | / \ / \ / + 0-| / \/ \/ + +---0----1----2----3----4----5----6------------> time (s) + +2. To make the LED go instantly from one brightness value to another, we should +use zero-time lengths (the brightness must be same as the previous tuple's). So +the format should be: "brightness_1 duration_1 brightness_1 0 brightness_2 +duration_2 brightness_2 0 ...". +For example (using sysfs interface): + +echo 0 1000 0 0 255 2000 255 0 > pattern + +It will make the LED stay off for one second, then stay at max brightness for +two seconds: + +LED brightness + ^ +255-| +---------+ +---------+ + | | | | | + | | | | | + | | | | | + 0-| -----+ +----+ +---- + +---0----1----2----3----4----5----6------------> time (s) -- cgit v1.2.3 From 1a6e741177d0fb70993d605305b09f9cb3b54414 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 14 Jan 2019 12:05:31 +0000 Subject: arm64: dts: rockchip: Add DT for NanoPi M4 There are a number of subtle differences between the nanopi4 variants, and where they disagree, the common DTSI currently follows the details of NanoPi M4. In order to improve matters even more, let's add a separate DTS for the M4 to which we can start splitting things out appropriately. The third variant, NanoPi NEO4, is a lot closer to the M4 than either is to the larger T4, so arguably could get away with just sharing the M4 DT for now (plus I have neither of the smaller boards to actually test with). CC: Rob Herring CC: Mark Rutland Signed-off-by: Robin Murphy Reviewed-by: Rob Herring Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 21d09a78869d..eb4d7f356543 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -87,9 +87,11 @@ properties: - const: firefly,roc-rk3399-pc - const: rockchip,rk3399 - - description: FriendlyElec NanoPC-T4 + - description: FriendlyElec NanoPi4 series boards items: - - const: friendlyarm,nanopc-t4 + - enum: + - friendlyarm,nanopc-t4 + - friendlyarm,nanopi-m4 - const: rockchip,rk3399 - description: GeekBuying GeekBox -- cgit v1.2.3 From a720349d2cb2e3d6d2f793b35ce7ffac38f9fcb8 Mon Sep 17 00:00:00 2001 From: Maxime Jourdan Date: Wed, 16 Jan 2019 13:40:29 +0100 Subject: dt-bindings: meson: add specific simplefb bindings Similar to simple-framebuffer-sunxi, we support different display pipelines that the firmware is free to choose from. This documents the "amlogic,simple-framebuffer" compatible and the "amlogic,pipeline" extension. Reviewed-by: Rob Herring Signed-off-by: Maxime Jourdan Signed-off-by: Kevin Hilman --- .../display/amlogic,simple-framebuffer.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/amlogic,simple-framebuffer.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/amlogic,simple-framebuffer.txt b/Documentation/devicetree/bindings/display/amlogic,simple-framebuffer.txt new file mode 100644 index 000000000000..aaa6c24c8e70 --- /dev/null +++ b/Documentation/devicetree/bindings/display/amlogic,simple-framebuffer.txt @@ -0,0 +1,33 @@ +Meson specific Simple Framebuffer bindings + +This binding documents meson specific extensions to the simple-framebuffer +bindings. The meson simplefb u-boot code relies on the devicetree containing +pre-populated simplefb nodes. + +These extensions are intended so that u-boot can select the right node based +on which pipeline is being used. As such they are solely intended for +firmware / bootloader use, and the OS should ignore them. + +Required properties: +- compatible: "amlogic,simple-framebuffer", "simple-framebuffer" +- amlogic,pipeline, one of: + "vpu-cvbs" + "vpu-hdmi" + +Example: + +chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + simplefb_hdmi: framebuffer-hdmi { + compatible = "amlogic,simple-framebuffer", + "simple-framebuffer"; + amlogic,pipeline = "vpu-hdmi"; + clocks = <&clkc CLKID_HDMI_PCLK>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_GCLK_VENCI_INT0>; + power-domains = <&pwrc_vpu>; + }; +}; -- cgit v1.2.3 From 2c6467d29583cba33da6e4265be09968e3d10b3c Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Fri, 11 Jan 2019 15:18:55 +0000 Subject: dt-bindings: display: bridge: fork out ti, ds90c185 from lvds-transmitter DS90C185 has a shutdown pin which does not fit in the lvds-transmitter binding, which is meant to be generic. The sister chip DS90C187 is similar to DS90C185, describe it here as well. Signed-off-by: Peter Rosin Reviewed-by: Rob Herring Signed-off-by: Andrzej Hajda Link: https://patchwork.freedesktop.org/patch/msgid/20190111151843.11114-2-peda@axentia.se --- .../bindings/display/bridge/lvds-transmitter.txt | 10 ++-- .../bindings/display/bridge/ti,ds90c185.txt | 55 ++++++++++++++++++++++ 2 files changed, 59 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt index 50220190c203..bc6960741cb5 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt +++ b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt @@ -22,13 +22,11 @@ among others. Required properties: -- compatible: Must be one or more of the following - - "ti,ds90c185" for the TI DS90C185 FPD-Link Serializer - - "lvds-encoder" for a generic LVDS encoder device +- compatible: Must be "lvds-encoder" - When compatible with the generic version, nodes must list the - device-specific version corresponding to the device first - followed by the generic version. + Any encoder compatible with this generic binding, but with additional + properties not listed here, must list a device specific compatible first + followed by this generic compatible. Required nodes: diff --git a/Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt b/Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt new file mode 100644 index 000000000000..e575f996959a --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt @@ -0,0 +1,55 @@ +Texas Instruments FPD-Link (LVDS) Serializer +-------------------------------------------- + +The DS90C185 and DS90C187 are low-power serializers for portable +battery-powered applications that reduces the size of the RGB +interface between the host GPU and the display. + +Required properties: + +- compatible: Should be + "ti,ds90c185", "lvds-encoder" for the TI DS90C185 FPD-Link Serializer + "ti,ds90c187", "lvds-encoder" for the TI DS90C187 FPD-Link Serializer + +Optional properties: + +- powerdown-gpios: Power down control GPIO (the PDB pin, active-low) + +Required nodes: + +The devices have two video ports. Their connections are modeled using the OF +graph bindings specified in Documentation/devicetree/bindings/graph.txt. + +- Video port 0 for parallel input +- Video port 1 for LVDS output + + +Example +------- + +lvds-encoder { + compatible = "ti,ds90c185", "lvds-encoder"; + + powerdown-gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_enc_in: endpoint { + remote-endpoint = <&lcdc_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + + lvds_enc_out: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; +}; -- cgit v1.2.3 From ad223fe3a6fdc18de696d1a39ff62a43700f93ec Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Fri, 11 Jan 2019 15:19:00 +0000 Subject: dt-bindings: display: bridge: lvds-transmitter: cleanup example Drop #address-cells and #size-cells from the root node in the example, they are unused. Reviewed-by: Rob Herring Signed-off-by: Peter Rosin Signed-off-by: Andrzej Hajda Link: https://patchwork.freedesktop.org/patch/msgid/20190111151843.11114-3-peda@axentia.se --- Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt index bc6960741cb5..60091db5dfa5 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt +++ b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt @@ -42,8 +42,6 @@ Example lvds-encoder { compatible = "lvds-encoder"; - #address-cells = <1>; - #size-cells = <0>; ports { #address-cells = <1>; -- cgit v1.2.3 From c572c95c42bf4d6768d7ec0969bb603bb3738f0e Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Fri, 11 Jan 2019 15:19:05 +0000 Subject: dt-bindings: display: bridge: thc63lvdm83d: use standard powerdown-gpios The name powerdown-gpios is the standard property name for the functionality covered by the previous pwdn-gpios name. This rename should be safe to do since the linux driver supporting the binding (lvds-encoder.c) never implemented the property, and no dts file names it. At least not upstream. Reviewed-by: Rob Herring Signed-off-by: Peter Rosin Signed-off-by: Andrzej Hajda Link: https://patchwork.freedesktop.org/patch/msgid/20190111151843.11114-4-peda@axentia.se --- Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt b/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt index 527e236e9a2a..fee3c88e1a17 100644 --- a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt +++ b/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt @@ -10,7 +10,7 @@ Required properties: Optional properties: -- pwdn-gpios: Power down control GPIO +- powerdown-gpios: Power down control GPIO (the /PWDN pin, active low). Required nodes: -- cgit v1.2.3 From 5d6353fe6984e7c3c41dae47aa38ee9c8ddaebd8 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Wed, 16 Jan 2019 15:20:36 +0100 Subject: dt-bindings: usb: usb251xb: add documentation for data lane swapping Add optional binding to allow USB differential-pair (D+/D-) data lane swapping. The swapping can be specified for each port separately, default is no swapping. Signed-off-by: Marco Felsch Reviewed-by: Richard Leitner Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/usb251xb.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/usb251xb.txt b/Documentation/devicetree/bindings/usb/usb251xb.txt index 168ff819e827..17915f64b8ee 100644 --- a/Documentation/devicetree/bindings/usb/usb251xb.txt +++ b/Documentation/devicetree/bindings/usb/usb251xb.txt @@ -64,6 +64,8 @@ Optional properties : - power-on-time-ms : Specifies the time it takes from the time the host initiates the power-on sequence to a port until the port has adequate power. The value is given in ms in a 0 - 510 range (default is 100ms). + - swap-dx-lanes : Specifies the ports which will swap the differential-pair + (D+/D-), default is not-swapped. Examples: usb2512b@2c { @@ -81,4 +83,6 @@ Examples: manufacturer = "Foo"; product = "Foo-Bar"; serial = "1234567890A"; + /* correct misplaced usb connectors on port 1,2 */ + swap-dx-lanes = <1 2>; }; -- cgit v1.2.3 From df230079140f836aeaef640cd31e01e20f37e099 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 Jan 2019 11:29:29 -0600 Subject: dt-bindings: serial: Convert snps,dw-apb-uart to json-schema Convert the snps,dw-apb-uart binding to DT schema using json-schema. The Rockchip and Broadcom compatible strings were not documented, so add them here. Cc: Greg Kroah-Hartman Cc: linux-serial@vger.kernel.org Reviewed-by: Simon Horman Signed-off-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- .../bindings/serial/snps-dw-apb-uart.txt | 76 ------------ .../bindings/serial/snps-dw-apb-uart.yaml | 135 +++++++++++++++++++++ 2 files changed, 135 insertions(+), 76 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt create mode 100644 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt deleted file mode 100644 index 12bbe9f22560..000000000000 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt +++ /dev/null @@ -1,76 +0,0 @@ -* Synopsys DesignWare ABP UART - -Required properties: -- compatible : "snps,dw-apb-uart" -- reg : offset and length of the register set for the device. -- interrupts : should contain uart interrupt. - -Clock handling: -The clock rate of the input clock needs to be supplied by one of -- clock-frequency : the input clock frequency for the UART. -- clocks : phandle to the input clock - -The supplying peripheral clock can also be handled, needing a second property -- clock-names: tuple listing input clock names. - Required elements: "baudclk", "apb_pclk" - -Optional properties: -- snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE - configuration parameter. Define this if your UART does not implement the busy - functionality. -- resets : phandle to the parent reset controller. -- reg-shift : quantity to shift the register offsets by. If this property is - not present then the register offsets are not shifted. -- reg-io-width : the size (in bytes) of the IO accesses that should be - performed on the device. If this property is not present then single byte - accesses are used. -- dcd-override : Override the DCD modem status signal. This signal will always - be reported as active instead of being obtained from the modem status - register. Define this if your serial port does not use this pin. -- dsr-override : Override the DTS modem status signal. This signal will always - be reported as active instead of being obtained from the modem status - register. Define this if your serial port does not use this pin. -- cts-override : Override the CTS modem status signal. This signal will always - be reported as active instead of being obtained from the modem status - register. Define this if your serial port does not use this pin. -- ri-override : Override the RI modem status signal. This signal will always be - reported as inactive instead of being obtained from the modem status register. - Define this if your serial port does not use this pin. - -Example: - - uart@80230000 { - compatible = "snps,dw-apb-uart"; - reg = <0x80230000 0x100>; - clock-frequency = <3686400>; - interrupts = <10>; - reg-shift = <2>; - reg-io-width = <4>; - dcd-override; - dsr-override; - cts-override; - ri-override; - }; - -Example with one clock: - - uart@80230000 { - compatible = "snps,dw-apb-uart"; - reg = <0x80230000 0x100>; - clocks = <&baudclk>; - interrupts = <10>; - reg-shift = <2>; - reg-io-width = <4>; - }; - -Example with two clocks: - - uart@80230000 { - compatible = "snps,dw-apb-uart"; - reg = <0x80230000 0x100>; - clocks = <&baudclk>, <&apb_pclk>; - clock-names = "baudclk", "apb_pclk"; - interrupts = <10>; - reg-shift = <2>; - reg-io-width = <4>; - }; diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml new file mode 100644 index 000000000000..3e90c790d720 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare ABP UART + +maintainers: + - Rob Herring + +allOf: + - $ref: /schemas/serial.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - rockchip,px30-uart + - rockchip,rk3036-uart + - rockchip,rk3066-uart + - rockchip,rk3188-uart + - rockchip,rk3288-uart + - rockchip,rk3328-uart + - rockchip,rk3368-uart + - rockchip,rk3399-uart + - rockchip,rv1108-uart + - const: snps,dw-apb-uart + - items: + - enum: + - brcm,bcm11351-dw-apb-uart + - brcm,bcm21664-dw-apb-uart + - const: snps,dw-apb-uart + - const: snps,dw-apb-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: true + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + items: + - const: baudclk + - const: apb_pclk + + snps,uart-16550-compatible: + description: reflects the value of UART_16550_COMPATIBLE configuration + parameter. Define this if your UART does not implement the busy functionality. + type: boolean + + resets: + maxItems: 1 + + reg-shift: true + + reg-io-width: true + + dcd-override: + description: Override the DCD modem status signal. This signal will + always be reported as active instead of being obtained from the modem + status register. Define this if your serial port does not use this + pin. + type: boolean + + dsr-override: + description: Override the DTS modem status signal. This signal will + always be reported as active instead of being obtained from the modem + status register. Define this if your serial port does not use this + pin. + type: boolean + + cts-override: + description: Override the CTS modem status signal. This signal will + always be reported as active instead of being obtained from the modem + status register. Define this if your serial port does not use this + pin. + type: boolean + + ri-override: + description: Override the RI modem status signal. This signal will always + be reported as inactive instead of being obtained from the modem status + register. Define this if your serial port does not use this pin. + type: boolean + +required: + - compatible + - reg + - interrupts + +examples: + - | + serial@80230000 { + compatible = "snps,dw-apb-uart"; + reg = <0x80230000 0x100>; + clock-frequency = <3686400>; + interrupts = <10>; + reg-shift = <2>; + reg-io-width = <4>; + dcd-override; + dsr-override; + cts-override; + ri-override; + }; + + - | + // Example with one clock: + serial@80230000 { + compatible = "snps,dw-apb-uart"; + reg = <0x80230000 0x100>; + clocks = <&baudclk>; + interrupts = <10>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + - | + // Example with two clocks: + serial@80230000 { + compatible = "snps,dw-apb-uart"; + reg = <0x80230000 0x100>; + clocks = <&baudclk>, <&apb_pclk>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <10>; + reg-shift = <2>; + reg-io-width = <4>; + }; +... -- cgit v1.2.3 From 896efccfcc7ff9cca44baa916a55ddf323cc10d1 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 Jan 2019 11:29:30 -0600 Subject: dt-bindings: serial: Move renesas,rzn1-uart into the snps-dw-apb-uart binding The renesas,rzn1-uart binding only differs in compatible string from the snps-dw-apb-uart binding. Move it there, converting it to json-schema in the process. Cc: Phil Edworthy Cc: Greg Kroah-Hartman Cc: linux-serial@vger.kernel.org Reviewed-by: Simon Horman Signed-off-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt | 10 ---------- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 5 +++++ 2 files changed, 5 insertions(+), 10 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt b/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt deleted file mode 100644 index 8b9e0d4dc2e4..000000000000 --- a/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt +++ /dev/null @@ -1,10 +0,0 @@ -Renesas RZ/N1 UART - -This controller is based on the Synopsys DesignWare ABP UART and inherits all -properties defined in snps-dw-apb-uart.txt except for the compatible property. - -Required properties: -- compatible : The device specific string followed by the generic RZ/N1 string. - Therefore it must be one of: - "renesas,r9a06g032-uart", "renesas,rzn1-uart" - "renesas,r9a06g033-uart", "renesas,rzn1-uart" diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 3e90c790d720..b42002542690 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -15,6 +15,11 @@ allOf: properties: compatible: oneOf: + - items: + - enum: + - renesas,r9a06g032-uart + - renesas,r9a06g033-uart + - const: renesas,rzn1-uart - items: - enum: - rockchip,px30-uart -- cgit v1.2.3 From abe9213a5e9c30649d44dd2bacce34319d7871a1 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Jan 2019 16:19:42 -0600 Subject: dt-bindings: serial: Convert arm,pl011 to json-schema Convert the arm,pl011 binding to DT schema using json-schema. The zte,zx296702-uart binding appears to be broken as the dts files are missing 'arm,primecell'. That's included in the schema here to throw a warning. Cc: Greg Kroah-Hartman Cc: linux-serial@vger.kernel.org Signed-off-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/pl011.txt | 51 --------- .../devicetree/bindings/serial/pl011.yaml | 126 +++++++++++++++++++++ 2 files changed, 126 insertions(+), 51 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/pl011.txt create mode 100644 Documentation/devicetree/bindings/serial/pl011.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt deleted file mode 100644 index 77863aefe9ef..000000000000 --- a/Documentation/devicetree/bindings/serial/pl011.txt +++ /dev/null @@ -1,51 +0,0 @@ -* ARM AMBA Primecell PL011 serial UART - -Required properties: -- compatible: must be "arm,primecell", "arm,pl011", "zte,zx296702-uart" -- reg: exactly one register range with length 0x1000 -- interrupts: exactly one interrupt specifier - -Optional properties: -- pinctrl: - When present, must have one state named "default", - and may contain a second name named "sleep". The former - state sets up pins for ordinary operation whereas - the latter state will put the associated pins to sleep - when the UART is unused -- clocks: - When present, the first clock listed must correspond to - the clock named UARTCLK on the IP block, i.e. the clock - to the external serial line, whereas the second clock - must correspond to the PCLK clocking the internal logic - of the block. Just listing one clock (the first one) is - deprecated. -- clock-names: - When present, the first clock listed must be named - "uartclk" and the second clock listed must be named - "apb_pclk" -- dmas: - When present, may have one or two dma channels. - The first one must be named "rx", the second one - must be named "tx". -- auto-poll: - Enables polling when using RX DMA. -- poll-rate-ms: - Rate at which poll occurs when auto-poll is set, - default 100ms. -- poll-timeout-ms: - Poll timeout when auto-poll is set, default - 3000ms. - -See also bindings/arm/primecell.txt - -Example: - -uart@80120000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80120000 0x1000>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>; - dma-names = "rx", "tx"; - clocks = <&foo_clk>, <&bar_clk>; - clock-names = "uartclk", "apb_pclk"; -}; diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml new file mode 100644 index 000000000000..1a64d59152aa --- /dev/null +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/pl011.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM AMBA Primecell PL011 serial UART + +maintainers: + - Rob Herring + +allOf: + - $ref: /schemas/serial.yaml# + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - arm,pl011 + - zte,zx296702-uart + required: + - compatible + +properties: + compatible: + oneOf: + - items: + - const: arm,pl011 + - const: arm,primecell + - items: + - const: zte,zx296702-uart + - const: arm,primecell + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + pinctrl-0: true + pinctrl-1: true + + pinctrl-names: + description: + When present, must have one state named "default", + and may contain a second name named "sleep". The former + state sets up pins for ordinary operation whereas + the latter state will put the associated pins to sleep + when the UART is unused + minItems: 1 + items: + - const: default + - const: sleep + + clocks: + description: + When present, the first clock listed must correspond to + the clock named UARTCLK on the IP block, i.e. the clock + to the external serial line, whereas the second clock + must correspond to the PCLK clocking the internal logic + of the block. Just listing one clock (the first one) is + deprecated. + maxItems: 2 + + clock-names: + items: + - const: uartclk + - const: apb_pclk + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + minItems: 1 + items: + - const: rx + - const: tx + + auto-poll: + description: + Enables polling when using RX DMA. + type: boolean + + poll-rate-ms: + description: + Rate at which poll occurs when auto-poll is set. + default 100ms. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - default: 100 + + poll-timeout-ms: + description: + Poll timeout when auto-poll is set, default + 3000ms. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - default: 3000 + +required: + - compatible + - reg + - interrupts + +dependencies: + poll-rate-ms: [ auto-poll ] + poll-timeout-ms: [ auto-poll ] + +additionalProperties: false + +examples: + - | + serial@80120000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80120000 0x1000>; + interrupts = <0 11 4>; + dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>; + dma-names = "rx", "tx"; + clocks = <&foo_clk>, <&bar_clk>; + clock-names = "uartclk", "apb_pclk"; + }; + +... -- cgit v1.2.3 From c24177b4a020b23f5ded65a54e3d93c4d268a15f Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Thu, 10 Jan 2019 16:30:12 +0100 Subject: dt-bindings: serial: sh-sci: Document r8a7778/9 HSCIF bindings Document support for the HSCIF serial ports in the Renesas R-Car M1A (R8A7778) and H1 (R8A7779) SoCs. No driver update is needed. Signed-off-by: Ulrich Hecht Reviewed-by: Simon Horman [geert: Patch description] Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 20232ad05d89..dd63151dc8b6 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -29,7 +29,9 @@ Required properties: - "renesas,scif-r8a774c0" for R8A774C0 (RZ/G2E) SCIF compatible UART. - "renesas,hscif-r8a774c0" for R8A774C0 (RZ/G2E) HSCIF compatible UART. - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART. + - "renesas,hscif-r8a7778" for R8A7778 (R-Car M1) HSCIF compatible UART. - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART. + - "renesas,hscif-r8a7779" for R8A7779 (R-Car H1) HSCIF compatible UART. - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART. - "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART. - "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART. -- cgit v1.2.3 From 7f0c77f35b1b8e0970b4be0aeccb85467b525df7 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Wed, 9 Jan 2019 14:42:05 +0530 Subject: dt-bindings: serial: omap_serial: add clocks entry Document clocks property used to pass phandle to functional clk. Signed-off-by: Vignesh R Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/omap_serial.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt index c35d5ece1156..0a9b5444f4e6 100644 --- a/Documentation/devicetree/bindings/serial/omap_serial.txt +++ b/Documentation/devicetree/bindings/serial/omap_serial.txt @@ -22,6 +22,8 @@ Optional properties: - dma-names : "rx" for receive channel, "tx" for transmit channel. - rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt - rs485-rts-active-high: drive RTS high when sending (default is low). +- clocks: phandle to the functional clock as per + Documentation/devicetree/bindings/clock/clock-bindings.txt Example: -- cgit v1.2.3 From 5296bab33b6037897a1e32958ddbc2b3dab405be Mon Sep 17 00:00:00 2001 From: Stefan M Schaeckeler Date: Thu, 17 Jan 2019 08:38:17 -0800 Subject: dt-bindings, EDAC: Add Aspeed AST2500 Add support for EDAC on the Aspeed AST2500 SoC. Signed-off-by: Stefan M Schaeckeler Signed-off-by: Borislav Petkov Reviewed-by: Andrew Jeffery Cc: Joel Stanley Cc: Mark Rutland Cc: Mauro Carvalho Chehab Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-aspeed@lists.ozlabs.org Cc: linux-edac Link: https://lkml.kernel.org/r/1547743097-5236-3-git-send-email-schaecsn@gmx.net --- .../devicetree/bindings/edac/aspeed-sdram-edac.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt new file mode 100644 index 000000000000..6a0f3d90d682 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt @@ -0,0 +1,25 @@ +Aspeed AST2500 SoC EDAC node + +The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error +correction check). + +The memory controller supports SECDED (single bit error correction, double bit +error detection) and single bit error auto scrubbing by reserving 8 bits for +every 64 bit word (effectively reducing available memory to 8/9). + +Note, the bootloader must configure ECC mode in the memory controller. + + +Required properties: +- compatible: should be "aspeed,ast2500-sdram-edac" +- reg: sdram controller register set should be <0x1e6e0000 0x174> +- interrupts: should be AVIC interrupt #0 + + +Example: + + edac: sdram@1e6e0000 { + compatible = "aspeed,ast2500-sdram-edac"; + reg = <0x1e6e0000 0x174>; + interrupts = <0>; + }; -- cgit v1.2.3 From 8b1352a008bc49fce5bf8b86b9e7fe433f387705 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdelin Date: Mon, 14 Jan 2019 15:19:14 -0500 Subject: dt-bindings: iio: chemical: Add bindings for bme680 BME680 is a pressure/temperature/humidity/voc sensor. Signed-off-by: Sebastien Bourdelin Acked-by: Himanshu Jha Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/chemical/bme680.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/chemical/bme680.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/chemical/bme680.txt b/Documentation/devicetree/bindings/iio/chemical/bme680.txt new file mode 100644 index 000000000000..7f3827cfb2ff --- /dev/null +++ b/Documentation/devicetree/bindings/iio/chemical/bme680.txt @@ -0,0 +1,11 @@ +Bosch Sensortec BME680 pressure/temperature/humidity/voc sensors + +Required properties: +- compatible: must be "bosch,bme680" + +Example: + +bme680@76 { + compatible = "bosch,bme680"; + reg = <0x76>; +}; -- cgit v1.2.3 From 1e1ab0b9f5a34caeed2f8b9cedca811054d746b5 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 16 Jan 2019 18:48:54 +0200 Subject: dt-binding: iio: add NPCM ADC documentation Added device tree binding documentation for Nuvoton BMC NPCM Analog-to-Digital Converter(ADC). Signed-off-by: Tomer Maimon Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- .../bindings/iio/adc/nuvoton,npcm-adc.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt new file mode 100644 index 000000000000..1b8132cd9060 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt @@ -0,0 +1,35 @@ +Nuvoton NPCM Analog to Digital Converter (ADC) + +The NPCM ADC is a 10-bit converter for eight channel inputs. + +Required properties: +- compatible: "nuvoton,npcm750-adc" for the NPCM7XX BMC. +- reg: specifies physical base address and size of the registers. +- interrupts: Contain the ADC interrupt with flags for falling edge. + +Optional properties: +- clocks: phandle of ADC reference clock, in case the clock is not + added the ADC will use the default ADC sample rate. +- vref-supply: The regulator supply ADC reference voltage, in case the + vref-supply is not added the ADC will use internal voltage + reference. + +Required Node in the NPCM7xx BMC: +An additional register is present in the NPCM7xx SOC which is +assumed to be in the same device tree, with and marked as +compatible with "nuvoton,npcm750-rst". + +Example: + +adc: adc@f000c000 { + compatible = "nuvoton,npcm750-adc"; + reg = <0xf000c000 0x8>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_ADC>; +}; + +rst: rst@f0801000 { + compatible = "nuvoton,npcm750-rst", "syscon", + "simple-mfd"; + reg = <0xf0801000 0x6C>; +}; -- cgit v1.2.3 From 697818f383fc548cdbfb1528c7067994739ace04 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Sat, 19 Jan 2019 15:42:38 -0500 Subject: dt-bindings: pinctrl: qcom-pmic-gpio: add qcom,pmi8998-gpio binding Add support for the PMI8998 GPIO variant to the Qualcomm PMIC GPIO binding document. Signed-off-by: Brian Masney Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index 759aa1732e48..7f64a7e92c28 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -19,6 +19,7 @@ PMIC's from Qualcomm. "qcom,pm8998-gpio" "qcom,pma8084-gpio" "qcom,pmi8994-gpio" + "qcom,pmi8998-gpio" "qcom,pms405-gpio" And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" -- cgit v1.2.3 From cf892f38e8568a20b853ec6efc2116c3e6e0215f Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 17 Jan 2019 11:23:13 +0100 Subject: dt-bindings: pinctrl: meson: update register descriptions like pull-enable, pull should be optional has this region is available on every controllers. Also, the g12a feature a new region "ds" for the drive-strength All this region thing is one big mess. I suspect that there is only one big GPIO region with holes in it. All registers between the current regions reads '0' so it is probably just spare space to handle more pins. Since we need to continue to handle the existing controllers, switching to one single region now would not simplify things. However, if more organisation layouts and features keep on being added, we may have to look at this again Fixes: 3cd3c83f6752 ("pinctrl: Add compatibles for Amlogic Meson G12A pin controllers") Signed-off-by: Jerome Brunet Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt index 82ead40311f6..a47dd990a8d3 100644 --- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt @@ -23,11 +23,11 @@ The GPIO bank for the controller is represented as a sub-node and it acts as a GPIO controller. Required properties for sub-nodes are: - - reg: should contain address and size for mux, pull-enable, pull and - gpio register sets - - reg-names: an array of strings describing the "reg" entries. Must - contain "mux", "pull" and "gpio". "pull-enable" is optional and - when it is missing the "pull" registers are used instead + - reg: should contain a list of address and size, one tuple for each entry + in reg-names. + - reg-names: an array of strings describing the "reg" entries. + Must contain "mux" and "gpio". + May contain "pull", "pull-enable" and "ds" when appropriate. - gpio-controller: identifies the node as a gpio controller - #gpio-cells: must be 2 -- cgit v1.2.3 From 9b4fce216f538f848a46183650f29603c1ecf4e6 Mon Sep 17 00:00:00 2001 From: Pawe? Chmiel Date: Fri, 7 Dec 2018 11:58:12 -0200 Subject: media: dt-bindings: Add binding for si470x radio Add device tree bindings for si470x family radio receiver driver. Signed-off-by: Pawe? Chmiel Reviewed-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/si470x.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/si470x.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/si470x.txt b/Documentation/devicetree/bindings/media/si470x.txt new file mode 100644 index 000000000000..a9403558362e --- /dev/null +++ b/Documentation/devicetree/bindings/media/si470x.txt @@ -0,0 +1,26 @@ +* Silicon Labs FM Radio receiver + +The Silicon Labs Si470x is family of FM radio receivers with receive power scan +supporting 76-108 MHz, programmable through an I2C interface. +Some of them includes an RDS encoder. + +Required Properties: +- compatible: Should contain "silabs,si470x" +- reg: the I2C address of the device + +Optional Properties: +- interrupts : The interrupt number +- reset-gpios: GPIO specifier for the chips reset line + +Example: + +&i2c2 { + si470x@63 { + compatible = "silabs,si470x"; + reg = <0x63>; + + interrupt-parent = <&gpj2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpj2 5 GPIO_ACTIVE_HIGH>; + }; +}; -- cgit v1.2.3 From 6372f01cddaa9d910d530ba3e389b9f86c7052e4 Mon Sep 17 00:00:00 2001 From: Matt Ranostay Date: Tue, 11 Dec 2018 13:17:00 -0200 Subject: media: dt-bindings: media: video-i2c: add melexis mlx90640 documentation Cc: devicetree@vger.kernel.org Signed-off-by: Matt Ranostay Reviewed-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../bindings/media/i2c/melexis,mlx90640.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/melexis,mlx90640.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/melexis,mlx90640.txt b/Documentation/devicetree/bindings/media/i2c/melexis,mlx90640.txt new file mode 100644 index 000000000000..060d2b7a5893 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/melexis,mlx90640.txt @@ -0,0 +1,20 @@ +* Melexis MLX90640 FIR Sensor + +Melexis MLX90640 FIR sensor support which allows recording of thermal data +with 32x24 resolution excluding 2 lines of coefficient data that is used by +userspace to render processed frames. + +Required Properties: + - compatible : Must be "melexis,mlx90640" + - reg : i2c address of the device + +Example: + + i2c0@1c22000 { + ... + mlx90640@33 { + compatible = "melexis,mlx90640"; + reg = <0x33>; + }; + ... + }; -- cgit v1.2.3 From bf72e42d400ace273931151b3a9bf1f8b846ec45 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Thu, 10 Jan 2019 16:30:12 +0100 Subject: dt-bindings: serial: sh-sci: Document r8a7778/9 HSCIF bindings Document support for the HSCIF serial ports in the Renesas R-Car M1A (R8A7778) and H1 (R8A7779) SoCs. No driver update is needed. Signed-off-by: Ulrich Hecht Reviewed-by: Simon Horman [geert: Patch description] Signed-off-by: Geert Uytterhoeven Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 20232ad05d89..dd63151dc8b6 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -29,7 +29,9 @@ Required properties: - "renesas,scif-r8a774c0" for R8A774C0 (RZ/G2E) SCIF compatible UART. - "renesas,hscif-r8a774c0" for R8A774C0 (RZ/G2E) HSCIF compatible UART. - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART. + - "renesas,hscif-r8a7778" for R8A7778 (R-Car M1) HSCIF compatible UART. - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART. + - "renesas,hscif-r8a7779" for R8A7779 (R-Car H1) HSCIF compatible UART. - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART. - "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART. - "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART. -- cgit v1.2.3 From 05f9f57500e214e7a82bad768c41911393d63881 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Tue, 8 Jan 2019 15:53:42 +0530 Subject: dt-bindings: remoteproc: qcom: Introduce shutdown-ack irq for Q6V5 Introduce shutdown-irq binding required for sysmon shutdown for Q6V5 MSS on SDM845/MSM8996 SoCs and for WCSS Q6V5 on QCS404 SoC. Reviewed-by: Rob Herring Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/remoteproc/qcom,adsp.txt | 17 ++++++++++++++--- .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 15 ++++++++++++--- 2 files changed, 26 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt index 60ee0f73071a..292dfda9770d 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt @@ -19,13 +19,24 @@ on the Qualcomm ADSP Hexagon core. - interrupts-extended: Usage: required Value type: - Definition: must list the watchdog, fatal IRQs ready, handover and - stop-ack IRQs + Definition: reference to the interrupts that match interrupt-names - interrupt-names: Usage: required Value type: - Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack" + Definition: The interrupts needed depends on the compatible + string: + qcom,msm8974-adsp-pil: + qcom,msm8996-adsp-pil: + qcom,msm8996-slpi-pil: + qcom,qcs404-adsp-pas: + qcom,qcs404-cdsp-pas: + qcom,sdm845-adsp-pas: + qcom,sdm845-cdsp-pas: + must be "wdog", "fatal", "ready", "handover", "stop-ack" + qcom,qcs404-wcss-pas: + must be "wdog", "fatal", "ready", "handover", "stop-ack", + "shutdown-ack" - firmware-name: Usage: optional diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index 401e49ebee39..41ca5df5be5a 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -28,13 +28,22 @@ on the Qualcomm Hexagon core. - interrupts-extended: Usage: required Value type: - Definition: must list the watchdog, fatal IRQs ready, handover and - stop-ack IRQs + Definition: reference to the interrupts that match interrupt-names - interrupt-names: Usage: required Value type: - Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack" + Definition: The interrupts needed depends on the the compatible + string: + qcom,q6v5-pil: + qcom,ipq8074-wcss-pil: + qcom,msm8916-mss-pil: + qcom,msm8974-mss-pil: + must be "wdog", "fatal", "ready", "handover", "stop-ack" + qcom,msm8996-mss-pil: + qcom,sdm845-mss-pil: + must be "wdog", "fatal", "ready", "handover", "stop-ack", + "shutdown-ack" - firmware-name: Usage: optional -- cgit v1.2.3 From 3dada33d735b27646720d8fcb105097b40646add Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Mon, 21 Jan 2019 09:57:04 +0000 Subject: dt-bindings: Add vendor prefix for Catalyst Semiconductor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add vendor prefix "catalyst" for Catalyst Semiconductor which is already in use but undocumented. Signed-off-by: Martyn Welch Reviewed-by: Rob Herring Reviewed-by: Andreas Färber Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..a81de3134724 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -65,6 +65,7 @@ bticino Bticino International calxeda Calxeda capella Capella Microsystems, Inc cascoda Cascoda, Ltd. +catalyst Catalyst Semiconductor, Inc. cavium Cavium, Inc. cdns Cadence Design Systems Inc. cdtech CDTech(H.K.) Electronics Limited -- cgit v1.2.3 From 06b3773b5038a618c578f823d5622481e96c0b56 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Wed, 16 Jan 2019 18:10:57 +0200 Subject: dt-bindings: Introduce interconnect binding This binding is intended to represent the relations between interconnect controllers (providers) and consumer device nodes. It will allow creating links between consumers and interconnect paths (exposed by interconnect providers). Reviewed-by: Evan Green Reviewed-by: Rob Herring Signed-off-by: Georgi Djakov Signed-off-by: Greg Kroah-Hartman --- .../bindings/interconnect/interconnect.txt | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/interconnect.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interconnect/interconnect.txt b/Documentation/devicetree/bindings/interconnect/interconnect.txt new file mode 100644 index 000000000000..5a3c575b387a --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/interconnect.txt @@ -0,0 +1,60 @@ +Interconnect Provider Device Tree Bindings +========================================= + +The purpose of this document is to define a common set of generic interconnect +providers/consumers properties. + + += interconnect providers = + +The interconnect provider binding is intended to represent the interconnect +controllers in the system. Each provider registers a set of interconnect +nodes, which expose the interconnect related capabilities of the interconnect +to consumer drivers. These capabilities can be throughput, latency, priority +etc. The consumer drivers set constraints on interconnect path (or endpoints) +depending on the use case. Interconnect providers can also be interconnect +consumers, such as in the case where two network-on-chip fabrics interface +directly. + +Required properties: +- compatible : contains the interconnect provider compatible string +- #interconnect-cells : number of cells in a interconnect specifier needed to + encode the interconnect node id + +Example: + + snoc: interconnect@580000 { + compatible = "qcom,msm8916-snoc"; + #interconnect-cells = <1>; + reg = <0x580000 0x14000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + += interconnect consumers = + +The interconnect consumers are device nodes which dynamically express their +bandwidth requirements along interconnect paths they are connected to. There +can be multiple interconnect providers on a SoC and the consumer may consume +multiple paths from different providers depending on use case and the +components it has to interact with. + +Required properties: +interconnects : Pairs of phandles and interconnect provider specifier to denote + the edge source and destination ports of the interconnect path. + +Optional properties: +interconnect-names : List of interconnect path name strings sorted in the same + order as the interconnects property. Consumers drivers will use + interconnect-names to match interconnect paths with interconnect + specifier pairs. + +Example: + + sdhci@7864000 { + ... + interconnects = <&pnoc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>; + interconnect-names = "sdhc-mem"; + }; -- cgit v1.2.3 From b5d2f741077abc71205e60b5bbd7dfa07b9d6953 Mon Sep 17 00:00:00 2001 From: David Dai Date: Wed, 16 Jan 2019 18:11:00 +0200 Subject: interconnect: qcom: Add sdm845 interconnect provider driver Introduce Qualcomm SDM845 specific provider driver using the interconnect framework. Signed-off-by: David Dai Acked-by: Rob Herring Signed-off-by: Georgi Djakov Signed-off-by: Greg Kroah-Hartman --- .../bindings/interconnect/qcom,sdm845.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt b/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt new file mode 100644 index 000000000000..5c4f1d911630 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt @@ -0,0 +1,24 @@ +Qualcomm SDM845 Network-On-Chip interconnect driver binding +----------------------------------------------------------- + +SDM845 interconnect providers support system bandwidth requirements through +RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is +able to communicate with the BCM through the Resource State Coordinator (RSC) +associated with each execution environment. Provider nodes must reside within +an RPMh device node pertaining to their RSC and each provider maps to a single +RPMh resource. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,sdm845-rsc-hlos" +- #interconnect-cells : should contain 1 + +Examples: + +apps_rsc: rsc { + rsc_hlos: interconnect { + compatible = "qcom,sdm845-rsc-hlos"; + #interconnect-cells = <1>; + }; +}; + -- cgit v1.2.3 From 1a69a73c9b006ae72e06a5e637932bfe2fb7bc05 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 16 Jan 2019 18:37:45 +0000 Subject: dt-bindings: arm: renesas: Add si-linux cat87[45] boards This patch adds board cat874 (powered by the RZ/G2E) and board cat875 (that sits on top of cat874). Both boards are made by Silicon Linux. Signed-off-by: Fabrizio Castro Reviewed-by: Chris Paterson Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 5e9d4864a600..9e1e07b5192e 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -108,6 +108,14 @@ properties: - description: RZ/G2E (R8A774C0) items: + - enum: + - si-linux,cat874 # Silicon Linux RZ/G2E 96board platform (CAT874) + - const: renesas,r8a774c0 + + - items: + - enum: + - si-linux,cat875 # Silicon Linux sub board for CAT874 (CAT875) + - const: si-linux,cat874 - const: renesas,r8a774c0 - description: R-Car M1A (R8A77781) -- cgit v1.2.3 From 5eca99917cb73086908cdb262ca54dff1fce4f6e Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sat, 19 Jan 2019 10:00:26 +0100 Subject: devicetree: property-units: Add femtofarads unit When dealing with capacitance of 0.5 pF then a smaller unit is preferred. Add femtofarads to deal with this. Signed-off-by: Sam Ravnborg Reviewed-by: Rob Herring Cc: Mark Rutland Cc: Alessandro Zummo Cc: Alexandre Belloni Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/property-units.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/property-units.txt b/Documentation/devicetree/bindings/property-units.txt index 45ce054d844d..bfd33734faca 100644 --- a/Documentation/devicetree/bindings/property-units.txt +++ b/Documentation/devicetree/bindings/property-units.txt @@ -31,6 +31,7 @@ Electricity -microwatt-hours: micro Watt-hours -microvolt : micro volts -picofarads : picofarads +-femtofarads : femtofarads Temperature ---------------------------------------- -- cgit v1.2.3 From d08fd7c1b9bd78b10345d2f9b115c5fd362b75cd Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sat, 19 Jan 2019 10:00:27 +0100 Subject: dt-bindings: rtc: Add quartz-load-femtofarads property The quartz-load-femtofarads are relevant for several users. Add it as a common property in rtc. Note that valid values and default values must be documented. Signed-off-by: Sam Ravnborg Suggested-by: Rob Herring Cc: Alessandro Zummo Cc: Alexandre Belloni Cc: Rob Herring Cc: Mark Rutland Reviewed-by: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/rtc.txt | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc.txt b/Documentation/devicetree/bindings/rtc/rtc.txt index b79a4794a928..0cacbc0edd20 100644 --- a/Documentation/devicetree/bindings/rtc/rtc.txt +++ b/Documentation/devicetree/bindings/rtc/rtc.txt @@ -21,12 +21,16 @@ Optional properties The following properties may not be supported by all drivers. However, if a driver wants to support one of the below features, it should adapt the bindings below. -- trickle-resistor-ohms : Selected resistor for trickle charger. Should be given - if trickle charger should be enabled -- trickle-diode-disable : Do not use internal trickle charger diode Should be - given if internal trickle charger diode should be - disabled -- wakeup-source : Enables wake up of host system on alarm +- trickle-resistor-ohms : Selected resistor for trickle charger. Should be given + if trickle charger should be enabled +- trickle-diode-disable : Do not use internal trickle charger diode Should be + given if internal trickle charger diode should be + disabled +- wakeup-source : Enables wake up of host system on alarm +- quartz-load-femtofarads : The capacitive load of the quartz(x-tal), + expressed in femto Farad (fF). + The default value shall be listed (if optional), + and likewise all valid values. Trivial RTCs ------------ -- cgit v1.2.3 From 8c12af15e7340a14e2978814ef28df58962283d6 Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sat, 19 Jan 2019 10:00:28 +0100 Subject: dt-binding: pcf8523: add xtal load capacitance MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The NXP pcf8523 supports two different xtal load capacitance - 7000fF (7pF) HW default - 12500fF (12.5pF) Minimum power consumption, driver default To obtain a precise RTC the pcf8523 must be configured with the correct capacitance load of the xtal. Add a property to specify the xtal capacitance load. The default value matches that of the current Linux driver. With a dedicated binding remove the entry in rtc.txt Signed-off-by: Søren Andersen Signed-off-by: Sam Ravnborg Reviewed-by: Rob Herring Cc: Alessandro Zummo Cc: Alexandre Belloni Cc: Mark Rutland Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/nxp,pcf8523.txt | 18 ++++++++++++++++++ Documentation/devicetree/bindings/rtc/rtc.txt | 1 - 2 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/rtc/nxp,pcf8523.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf8523.txt b/Documentation/devicetree/bindings/rtc/nxp,pcf8523.txt new file mode 100644 index 000000000000..0b1080c60f63 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf8523.txt @@ -0,0 +1,18 @@ +* NXP PCF8523 Real Time Clock + +Required properties: +- compatible: Should contain "nxp,pcf8523". +- reg: I2C address for chip. + +Optional property: +- quartz-load-femtofarads: The capacitive load of the quartz(x-tal), + expressed in femto Farad (fF). Valid values are 7000 and 12500. + Default value (if no value is specified) is 12500fF. + +Example: + +pcf8523: rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + quartz-load-femtofarads = <7000>; +}; diff --git a/Documentation/devicetree/bindings/rtc/rtc.txt b/Documentation/devicetree/bindings/rtc/rtc.txt index 0cacbc0edd20..27a7c1578f6e 100644 --- a/Documentation/devicetree/bindings/rtc/rtc.txt +++ b/Documentation/devicetree/bindings/rtc/rtc.txt @@ -56,7 +56,6 @@ microcrystal,rv3029 Real Time Clock Module with I2C-Bus microcrystal,rv8523 Real Time Clock nxp,pcf2127 Real-time clock nxp,pcf2129 Real-time clock -nxp,pcf8523 Real-time Clock nxp,pcf8563 Real-time clock/calendar nxp,pcf85063 Tiny Real-Time Clock pericom,pt7c4338 Real-time Clock Module -- cgit v1.2.3 From e4a604cbee5470fc116ac9a4f852152070984286 Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sat, 19 Jan 2019 10:00:29 +0100 Subject: dt-binding: pcf85063: add xtal load capacitance MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The NXP pcf85063 supports two different xtal load capacitance - 7000fF (7pF) HW default, Linux driver default - 12500fF (12.5pF) Minimum power consumption To obtain a precise RTC the pcf85063 must be configured with the correct capacitance load of the xtal. Add a property to specify the xtal capacitance load. The default value matches that of the current Linux driver. With a dedicated binding remove the entry in rtc.txt Signed-off-by: Søren Andersen Signed-off-by: Sam Ravnborg Cc: Alessandro Zummo Cc: Alexandre Belloni Cc: Rob Herring Cc: Mark Rutland Cc: Urs Fässler Reviewed-by: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt | 18 ++++++++++++++++++ Documentation/devicetree/bindings/rtc/rtc.txt | 1 - 2 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt b/Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt new file mode 100644 index 000000000000..d3e380ad712d --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt @@ -0,0 +1,18 @@ +* NXP PCF85063 Real Time Clock + +Required properties: +- compatible: Should contain "nxp,pcf85063". +- reg: I2C address for chip. + +Optional property: +- quartz-load-femtofarads: The capacitive load of the quartz(x-tal), + expressed in femto Farad (fF). Valid values are 7000 and 12500. + Default value (if no value is specified) is 7000fF. + +Example: + +pcf85063: rtc@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; +}; diff --git a/Documentation/devicetree/bindings/rtc/rtc.txt b/Documentation/devicetree/bindings/rtc/rtc.txt index 27a7c1578f6e..d86e2850fe1c 100644 --- a/Documentation/devicetree/bindings/rtc/rtc.txt +++ b/Documentation/devicetree/bindings/rtc/rtc.txt @@ -57,7 +57,6 @@ microcrystal,rv8523 Real Time Clock nxp,pcf2127 Real-time clock nxp,pcf2129 Real-time clock nxp,pcf8563 Real-time clock/calendar -nxp,pcf85063 Tiny Real-Time Clock pericom,pt7c4338 Real-time Clock Module ricoh,r2025sd I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC ricoh,r2221tl I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -- cgit v1.2.3 From 1e47704e15f0907d2d8482ec939e3cb500bae558 Mon Sep 17 00:00:00 2001 From: Jan Kotas Date: Tue, 22 Jan 2019 10:42:15 +0000 Subject: dt-bindings: rtc: Add bindings for Cadence RTC This patch adds a DT binding documentation for Cadence RTC controller. Signed-off-by: Jan Kotas Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/cdns,rtc.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/cdns,rtc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/cdns,rtc.txt b/Documentation/devicetree/bindings/rtc/cdns,rtc.txt new file mode 100644 index 000000000000..14a04487b432 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/cdns,rtc.txt @@ -0,0 +1,25 @@ +Cadence Real Time Clock + +The Cadence RTC controller with date, time and alarm capabilities. +The alarm may wake the system from low-power state. + +Required properties: +- compatible: Should be "cdns,rtc-r109v3" +- reg: Specifies base physical address and size of the register area. +- interrupts: A single interrupt specifier. +- clocks: Must contain two entries: + - pclk: APB registers clock + - ref_clk: reference 1Hz or 100Hz clock, depending on IP configuration + See ../clocks/clock-bindings.txt for details. + +Example: + rtc0: rtc@fd080000 { + compatible = "cdns,rtc-r109v3"; + reg = <0xfd080000 0x1000>; + + clock-names = "pclk", "ref_clk"; + clocks = <&sysclock>, <&refclock>; + + interrupt-parent = <&gic>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + }; -- cgit v1.2.3 From cea8e2f3938c510f6041c632fe19e4e95296ae04 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 10 Jan 2019 09:32:01 +0530 Subject: dt-bindings: opp: Introduce opp-level bindings Add opp-level as an additional property in the OPP node to describe the performance level of the device. On some SoCs (especially from Qualcomm and MediaTek) this value is communicated to a remote microprocessor by the CPU, which then takes some actions (like adjusting voltage values across various rails) based on the value passed. Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Rob Herring Acked-by: Viresh Kumar Signed-off-by: Rajendra Nayak Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/opp/opp.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt index c396c4c0af92..76b6c79604a5 100644 --- a/Documentation/devicetree/bindings/opp/opp.txt +++ b/Documentation/devicetree/bindings/opp/opp.txt @@ -129,6 +129,9 @@ Optional properties: - opp-microamp-: Named opp-microamp property. Similar to opp-microvolt- property, but for microamp instead. +- opp-level: A value representing the performance level of the device, + expressed as a 32-bit integer. + - clock-latency-ns: Specifies the maximum possible transition latency (in nanoseconds) for switching to this OPP from any other OPP. -- cgit v1.2.3 From c6e6eff4d48f8b7180f9f94f1615ffe345fd7e5c Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 10 Jan 2019 09:32:03 +0530 Subject: dt-bindings: power: Add qcom rpm power domain driver bindings Add DT bindings to describe the rpm/rpmh power domains found on Qualcomm Technologies, Inc. SoCs. These power domains communicate a performance state to RPM/RPMh, which then translates it into corresponding voltage on a PMIC rail. Reviewed-by: Ulf Hansson Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring Signed-off-by: Rajendra Nayak Signed-off-by: Viresh Kumar Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../devicetree/bindings/power/qcom,rpmpd.txt | 145 +++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/qcom,rpmpd.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.txt b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt new file mode 100644 index 000000000000..980e5413d18f --- /dev/null +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.txt @@ -0,0 +1,145 @@ +Qualcomm RPM/RPMh Power domains + +For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh +which then translates it into a corresponding voltage on a rail + +Required Properties: + - compatible: Should be one of the following + * qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC + * qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of SoC + - #power-domain-cells: number of cells in Power domain specifier + must be 1. + - operating-points-v2: Phandle to the OPP table for the Power domain. + Refer to Documentation/devicetree/bindings/power/power_domain.txt + and Documentation/devicetree/bindings/opp/opp.txt for more details + +Refer to for the level values for +various OPPs for different platforms as well as Power domain indexes + +Example: rpmh power domain controller and OPP table + +#include + +opp-level values specified in the OPP tables for RPMh power domains +should use the RPMH_REGULATOR_LEVEL_* constants from + + + rpmhpd: power-controller { + compatible = "qcom,sdm845-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + +Example: rpm power domain controller and OPP table + + rpmpd: power-controller { + compatible = "qcom,msm8996-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_low: opp1 { + opp-level = <1>; + }; + + rpmpd_opp_ret: opp2 { + opp-level = <2>; + }; + + rpmpd_opp_svs: opp3 { + opp-level = <3>; + }; + + rpmpd_opp_normal: opp4 { + opp-level = <4>; + }; + + rpmpd_opp_high: opp5 { + opp-level = <5>; + }; + + rpmpd_opp_turbo: opp6 { + opp-level = <6>; + }; + }; + }; + +Example: Client/Consumer device using OPP table + + leaky-device0@12350000 { + compatible = "foo,i-leak-current"; + reg = <0x12350000 0x1000>; + power-domains = <&rpmhpd SDM845_MX>; + operating-points-v2 = <&leaky_opp_table>; + }; + + + leaky_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp1 { + opp-hz = /bits/ 64 <144000>; + required-opps = <&rpmhpd_opp_low>; + }; + + opp2 { + opp-hz = /bits/ 64 <400000>; + required-opps = <&rpmhpd_opp_ret>; + }; + + opp3 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp4 { + opp-hz = /bits/ 64 <25000000>; + required-opps = <&rpmpd_opp_normal>; + }; + }; -- cgit v1.2.3 From 00f1ee5361c3f644133ef2d19d2c340d2a730f1d Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 21 Jan 2019 14:43:14 +0530 Subject: dt-bindings: net: Add Qualcomm ethqos binding Add support for Qualcomm ethqos found in some SoCs like QCS404. Signed-off-by: Vinod Koul Reviewed-by: Rob Herring Signed-off-by: David S. Miller --- .../devicetree/bindings/net/qcom,ethqos.txt | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/qcom,ethqos.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/qcom,ethqos.txt b/Documentation/devicetree/bindings/net/qcom,ethqos.txt new file mode 100644 index 000000000000..fcf5035810b5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/qcom,ethqos.txt @@ -0,0 +1,64 @@ +Qualcomm Ethernet ETHQOS device + +This documents dwmmac based ethernet device which supports Gigabit +ethernet for version v2.3.0 onwards. + +This device has following properties: + +Required properties: + +- compatible: Should be qcom,qcs404-ethqos" + +- reg: Address and length of the register set for the device + +- reg-names: Should contain register names "stmmaceth", "rgmii" + +- clocks: Should contain phandle to clocks + +- clock-names: Should contain clock names "stmmaceth", "pclk", + "ptp_ref", "rgmii" + +- interrupts: Should contain phandle to interrupts + +- interrupt-names: Should contain interrupt names "macirq", "eth_lpi" + +Rest of the properties are defined in stmmac.txt file in same directory + + +Example: + +ethernet: ethernet@7a80000 { + compatible = "qcom,qcs404-ethqos"; + reg = <0x07a80000 0x10000>, + <0x07a96000 0x100>; + reg-names = "stmmaceth", "rgmii"; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + clocks = <&gcc GCC_ETH_AXI_CLK>, + <&gcc GCC_ETH_SLAVE_AHB_CLK>, + <&gcc GCC_ETH_PTP_CLK>, + <&gcc GCC_ETH_RGMII_CLK>; + interrupts = , + ; + interrupt-names = "macirq", "eth_lpi"; + snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + + snps,txpbl = <8>; + snps,rxpbl = <2>; + snps,aal; + snps,tso; + + phy-handle = <&phy1>; + phy-mode = "rgmii"; + + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "snps,dwmac-mdio"; + phy1: phy@4 { + device_type = "ethernet-phy"; + reg = <0x4>; + }; + }; + +}; -- cgit v1.2.3 From 5ff2698b3301c37246f1f79dc9bdcd378b000dbe Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Mon, 21 Jan 2019 18:41:40 +0800 Subject: dt-binding: ptp_qoriq: document "fsl,extts-fifo" property Documented "fsl,extts-fifo" property. Signed-off-by: Yangbo Lu Reviewed-by: Rob Herring Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/ptp/ptp-qoriq.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt b/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt index c5d0e7998e2b..8e7f8551d190 100644 --- a/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt +++ b/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt @@ -17,6 +17,8 @@ Clock Properties: - fsl,tmr-fiper1 Fixed interval period pulse generator. - fsl,tmr-fiper2 Fixed interval period pulse generator. - fsl,max-adj Maximum frequency adjustment in parts per billion. + - fsl,extts-fifo The presence of this property indicates hardware + support for the external trigger stamp FIFO. These properties set the operational parameters for the PTP clock. You must choose these carefully for the clock to work right. -- cgit v1.2.3 From 5fa98c2eda35fcd1a1d91a9785c390f54688240c Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 22 Jan 2019 09:10:10 -0600 Subject: dt-bindings: Fix dt_binding_check target for in tree builds On in tree builds, subsequent builds will incorrectly include the intermediate file 'processed-schema.yaml' with the input schema files resulting in a build error. Update the find command to ignore processed-schema.yaml. Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile index 6e5cef0ed6fb..50daa0b3b032 100644 --- a/Documentation/devicetree/bindings/Makefile +++ b/Documentation/devicetree/bindings/Makefile @@ -17,7 +17,11 @@ extra-y += $(DT_TMP_SCHEMA) quiet_cmd_mk_schema = SCHEMA $@ cmd_mk_schema = $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $(filter-out FORCE, $^) -DT_DOCS = $(shell cd $(srctree)/$(src) && find * -name '*.yaml') +DT_DOCS = $(shell \ + cd $(srctree)/$(src) && \ + find * \( -name '*.yaml' ! -name $(DT_TMP_SCHEMA) \) \ + ) + DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS)) extra-y += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES)) -- cgit v1.2.3 From 45b5d2b7a976309c31f13795ad63a9488d0d7bbd Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Tue, 22 Jan 2019 11:46:37 +0200 Subject: regulator: bindings: ROHM bd70528 regulator bindings ROHM bd70528 is a ultra low power PMIC which includes 3 bucks, 3 LDOs and 2 LED drivers. Document the bindings for them. Signed-off-by: Matti Vaittinen Signed-off-by: Mark Brown --- .../bindings/regulator/rohm,bd70528-regulator.txt | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/rohm,bd70528-regulator.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd70528-regulator.txt b/Documentation/devicetree/bindings/regulator/rohm,bd70528-regulator.txt new file mode 100644 index 000000000000..698cfc3bc3dd --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/rohm,bd70528-regulator.txt @@ -0,0 +1,68 @@ +ROHM BD70528 Power Management Integrated Circuit regulator bindings + +Required properties: + - regulator-name: should be "buck1", "buck2", "buck3", "ldo1", "ldo2", "ldo3", + "led_ldo1", "led_ldo2" + +List of regulators provided by this controller. BD70528 regulators node +should be sub node of the BD70528 MFD node. See BD70528 MFD bindings at +Documentation/devicetree/bindings/mfd/rohm,bd70528-pmic.txt + +The valid names for BD70528 regulator nodes are: +BUCK1, BUCK2, BUCK3, LDO1, LDO2, LDO3, LED_LDO1, LED_LDO2 + +Optional properties: +- Any optional property defined in bindings/regulator/regulator.txt + +Example: +regulators { + buck1: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-ramp-delay = <125>; + }; + buck2: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-ramp-delay = <125>; + }; + buck3: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-ramp-delay = <250>; + }; + ldo1: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + ldo2: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + ldo3: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + }; + led_ldo1: LED_LDO1 { + regulator-name = "led_ldo1"; + regulator-min-microvolt = <200000>; + regulator-max-microvolt = <300000>; + }; + led_ldo2: LED_LDO2 { + regulator-name = "led_ldo2"; + regulator-min-microvolt = <200000>; + regulator-max-microvolt = <300000>; + }; +}; -- cgit v1.2.3 From 257afa58e608d5f790b4c0f6e0334f69881f6de4 Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Tue, 15 Jan 2019 18:32:34 +0800 Subject: dt-bindings: power: sc27xx: Add one IIO channel to read charge voltage Add one IIO channel named "charge_vol" to read the charge voltage for the SC27XX fuel gauge controller. Signed-off-by: Baolin Wang Reviewed-by: Rob Herring Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt b/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt index fc35ac577401..0a5705b8b592 100644 --- a/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt +++ b/Documentation/devicetree/bindings/power/supply/sc27xx-fg.txt @@ -9,8 +9,8 @@ Required properties: "sprd,sc2731-fgu". - reg: The address offset of fuel gauge unit. - battery-detect-gpios: GPIO for battery detection. -- io-channels: Specify the IIO ADC channel to get temperature. -- io-channel-names: Should be "bat-temp". +- io-channels: Specify the IIO ADC channels to get temperature and charge voltage. +- io-channel-names: Should be "bat-temp" or "charge-vol". - nvmem-cells: A phandle to the calibration cells provided by eFuse device. - nvmem-cell-names: Should be "fgu_calib". - monitored-battery: Phandle of battery characteristics devicetree node. @@ -47,8 +47,8 @@ Example: compatible = "sprd,sc2731-fgu"; reg = <0xa00>; battery-detect-gpios = <&pmic_eic 9 GPIO_ACTIVE_HIGH>; - io-channels = <&pmic_adc 5>; - io-channel-names = "bat-temp"; + io-channels = <&pmic_adc 5>, <&pmic_adc 14>; + io-channel-names = "bat-temp", "charge-vol"; nvmem-cells = <&fgu_calib>; nvmem-cell-names = "fgu_calib"; monitored-battery = <&bat>; -- cgit v1.2.3 From 0113613faf0214b5e04ccf9149c330ee67f9779c Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Mon, 21 Jan 2019 07:22:54 +0100 Subject: Revert "Input: olpc_apsp - enable the SP clock" Turns out this is not such a great idea. Once the SP clock is disabled, it's not sufficient to just enable in order to bring the SP core back up. It seems that the kernel has no business managing this clock. Just let the firmware keep it enabled. This reverts commit ed22cee91a88c47e564478b012fdbcb079653499. Link: https://lore.kernel.org/lkml/154783267051.169631.3197836544646625747@swboyd.mtv.corp.google.com/ Signed-off-by: Lubomir Rintel Acked-by: Dmitry Torokhov Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/serio/olpc,ap-sp.txt | 4 ---- 1 file changed, 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serio/olpc,ap-sp.txt b/Documentation/devicetree/bindings/serio/olpc,ap-sp.txt index 36603419d6f8..0e72183f52bc 100644 --- a/Documentation/devicetree/bindings/serio/olpc,ap-sp.txt +++ b/Documentation/devicetree/bindings/serio/olpc,ap-sp.txt @@ -4,14 +4,10 @@ Required properties: - compatible : "olpc,ap-sp" - reg : base address and length of SoC's WTM registers - interrupts : SP-AP interrupt -- clocks : phandle + clock-specifier for the clock that drives the WTM -- clock-names: should be "sp" Example: ap-sp@d4290000 { compatible = "olpc,ap-sp"; reg = <0xd4290000 0x1000>; interrupts = <40>; - clocks = <&soc_clocks MMP2_CLK_SP>; - clock-names = "sp"; } -- cgit v1.2.3 From 895ad6b0ccf71ec1f8d5bc4d9f15b525feb160a8 Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Tue, 18 Dec 2018 11:32:37 -0700 Subject: drm/msm: drop interrupt-names Each GPU core only uses one interrupt so we don't to look up an interrupt by name and thereby we don't need interrupt-names. Signed-off-by: Jordan Crouse Reviewed-by: Rob Herring Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/gpu.txt | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index ac8df3b871f9..f8759145ce1a 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -27,7 +27,6 @@ Example: reg = <0x04300000 0x20000>; reg-names = "kgsl_3d0_reg_memory"; interrupts = ; - interrupt-names = "kgsl_3d0_irq"; clock-names = "core", "iface", -- cgit v1.2.3 From 420601d25c0c8dd0749ccfb9bd59526c64b4cc35 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Jan 2019 16:19:01 -0600 Subject: dt-bindings: clock: Convert fixed-clock binding to json-schema Convert the fixed-clock binding to DT schema format using json-schema. Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Signed-off-by: Rob Herring [sboyd@kernel.org: Drop full stop on title] Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/fixed-clock.txt | 23 ----------- .../devicetree/bindings/clock/fixed-clock.yaml | 44 ++++++++++++++++++++++ 2 files changed, 44 insertions(+), 23 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/fixed-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/fixed-clock.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.txt b/Documentation/devicetree/bindings/clock/fixed-clock.txt deleted file mode 100644 index 0641a663ad69..000000000000 --- a/Documentation/devicetree/bindings/clock/fixed-clock.txt +++ /dev/null @@ -1,23 +0,0 @@ -Binding for simple fixed-rate clock sources. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "fixed-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- clock-frequency : frequency of clock in Hz. Should be a single cell. - -Optional properties: -- clock-accuracy : accuracy of clock in ppb (parts per billion). - Should be a single cell. -- clock-output-names : From common clock binding. - -Example: - clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - clock-accuracy = <100>; - }; diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.yaml b/Documentation/devicetree/bindings/clock/fixed-clock.yaml new file mode 100644 index 000000000000..b657ecd0ef1c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fixed-clock.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fixed-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Binding for simple fixed-rate clock sources + +maintainers: + - Michael Turquette + - Stephen Boyd + +properties: + compatible: + const: fixed-clock + + "#clock-cells": + const: 0 + + clock-frequency: true + + clock-accuracy: + description: accuracy of clock in ppb (parts per billion). + $ref: /schemas/types.yaml#/definitions/uint32 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clock-frequency + +additionalProperties: false + +examples: + - | + clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + clock-accuracy = <100>; + }; +... -- cgit v1.2.3 From f79bae1666f8af6ce0c2da0b2057675ba6185a25 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Jan 2019 16:19:02 -0600 Subject: dt-bindings: clock: Convert fixed-factor-clock to json-schema Convert the fixed-factor-clock binding to DT schema format using json-schema. Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Signed-off-by: Rob Herring [sboyd@kernel.org: Drop full stop on title] Signed-off-by: Stephen Boyd --- .../bindings/clock/fixed-factor-clock.txt | 28 ----------- .../bindings/clock/fixed-factor-clock.yaml | 56 ++++++++++++++++++++++ 2 files changed, 56 insertions(+), 28 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/fixed-factor-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt deleted file mode 100644 index 189467a7188a..000000000000 --- a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt +++ /dev/null @@ -1,28 +0,0 @@ -Binding for simple fixed factor rate clock sources. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "fixed-factor-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- clock-div: fixed divider. -- clock-mult: fixed multiplier. -- clocks: parent clock. - -Optional properties: -- clock-output-names : From common clock binding. - -Some clocks that require special treatments are also handled by that -driver, with the compatibles: - - allwinner,sun4i-a10-pll3-2x-clk - -Example: - clock { - compatible = "fixed-factor-clock"; - clocks = <&parentclk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml b/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml new file mode 100644 index 000000000000..b567f8092f8c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Binding for simple fixed factor rate clock sources + +maintainers: + - Michael Turquette + - Stephen Boyd + +properties: + compatible: + enum: + - allwinner,sun4i-a10-pll3-2x-clk + - fixed-factor-clock + + "#clock-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-div: + description: Fixed divider + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 1 + + clock-mult: + description: Fixed multiplier + $ref: /schemas/types.yaml#/definitions/uint32 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - clocks + - "#clock-cells" + - clock-div + - clock-mult + +additionalProperties: false + +examples: + - | + clock { + compatible = "fixed-factor-clock"; + clocks = <&parentclk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; +... -- cgit v1.2.3 From d62cd1b802d0842275ddafd8ba4ed82832968cd0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Jan 2019 11:23:05 +0800 Subject: dt-bindings: display: sun4i-drm: Add compatible strings for A23 display The A23's display pipeline is similar to the A33. Differences include: - Display backend supports larger layers, 8192x8192 instead of 2048x2048 - TCON has DMA input - There is no SAT module packed in the display backend Add compatible strings for the display pipeline and its components. As the MIPI DSI output device is not officially documented, and there are no A23 reference devices to test it, it is not covered by this patch. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20190125032314.20915-3-wens@csie.org --- Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index f426bdb42f18..31ab72cba3d4 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -156,6 +156,7 @@ Required properties: * allwinner,sun6i-a31-tcon * allwinner,sun6i-a31s-tcon * allwinner,sun7i-a20-tcon + * allwinner,sun8i-a23-tcon * allwinner,sun8i-a33-tcon * allwinner,sun8i-a83t-tcon-lcd * allwinner,sun8i-a83t-tcon-tv @@ -276,6 +277,7 @@ Required properties: - compatible: value must be one of: * allwinner,sun6i-a31-drc * allwinner,sun6i-a31s-drc + * allwinner,sun8i-a23-drc * allwinner,sun8i-a33-drc * allwinner,sun9i-a80-drc - reg: base address and size of the memory-mapped region. @@ -303,6 +305,7 @@ Required properties: * allwinner,sun5i-a13-display-backend * allwinner,sun6i-a31-display-backend * allwinner,sun7i-a20-display-backend + * allwinner,sun8i-a23-display-backend * allwinner,sun8i-a33-display-backend * allwinner,sun9i-a80-display-backend - reg: base address and size of the memory-mapped region. @@ -360,6 +363,7 @@ Required properties: * allwinner,sun5i-a13-display-frontend * allwinner,sun6i-a31-display-frontend * allwinner,sun7i-a20-display-frontend + * allwinner,sun8i-a23-display-frontend * allwinner,sun8i-a33-display-frontend * allwinner,sun9i-a80-display-frontend - reg: base address and size of the memory-mapped region. @@ -419,6 +423,7 @@ Required properties: * allwinner,sun6i-a31-display-engine * allwinner,sun6i-a31s-display-engine * allwinner,sun7i-a20-display-engine + * allwinner,sun8i-a23-display-engine * allwinner,sun8i-a33-display-engine * allwinner,sun8i-a83t-display-engine * allwinner,sun8i-h3-display-engine -- cgit v1.2.3 From 58097b0e05c0dc70345c02cd83117f134574024e Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Wed, 23 Jan 2019 09:30:12 -0500 Subject: dt-bindings: arm: renesas: Document RZ/A2M EVB Add the RZ/A2M Evaluation board. Signed-off-by: Chris Brandt Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/renesas.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 9e1e07b5192e..cb9b4417e8a1 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -30,6 +30,8 @@ properties: - description: RZ/A2 (R7S9210) items: + - enum: + - renesas,rza2mevb # RZ/A2M Eval Board (RTK7921053S00000BE) - const: renesas,r7s9210 - description: SH-Mobile AG5 (R8A73A00/SH73A0) -- cgit v1.2.3 From 176f011bda551f2bb884dc25595859c3b35ac479 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Thu, 24 Jan 2019 07:34:37 +0100 Subject: dt-bindings: gnss: add w2sg0004 compatible string Add w2sg0004 compatible string since devices without wakeup pins are now supported. Signed-off-by: Andreas Kemnade Reviewed-by: Rob Herring Signed-off-by: Johan Hovold --- Documentation/devicetree/bindings/gnss/sirfstar.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gnss/sirfstar.txt b/Documentation/devicetree/bindings/gnss/sirfstar.txt index 648d183cdb77..f4252b6b660b 100644 --- a/Documentation/devicetree/bindings/gnss/sirfstar.txt +++ b/Documentation/devicetree/bindings/gnss/sirfstar.txt @@ -12,6 +12,7 @@ Required properties: "fastrax,uc430" "linx,r4" + "wi2wi,w2sg0004" "wi2wi,w2sg0008i" "wi2wi,w2sg0084i" -- cgit v1.2.3 From f9eb86fddaf2e9a40c79e6ae69865eb6c8913a6e Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Thu, 24 Jan 2019 07:34:39 +0100 Subject: dt-bindings: gnss: add lna-supply property Add lna-supply property. Signed-off-by: Andreas Kemnade Reviewed-by: Rob Herring Signed-off-by: Johan Hovold --- Documentation/devicetree/bindings/gnss/gnss.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gnss/gnss.txt b/Documentation/devicetree/bindings/gnss/gnss.txt index f1e4a2ff47c5..f547bd4549fe 100644 --- a/Documentation/devicetree/bindings/gnss/gnss.txt +++ b/Documentation/devicetree/bindings/gnss/gnss.txt @@ -17,6 +17,7 @@ Required properties: represents Optional properties: +- lna-supply : Separate supply for an LNA - enable-gpios : GPIO used to enable the device - timepulse-gpios : Time pulse GPIO -- cgit v1.2.3 From 3e65b2b43132cc188e4830b71e9f232c0acc47fb Mon Sep 17 00:00:00 2001 From: Mark Zhang Date: Fri, 11 Jan 2019 10:38:46 +0800 Subject: dt-bindings: tegra: Add Shield TV device tree binding documentation Add the device tree binding documentation for NVIDIA Shield TV. Signed-off-by: Mark Zhang Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index fbcde8a7e067..60b38eb5c61a 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -87,9 +87,11 @@ properties: - const: nvidia,tegra124 - items: - enum: + - nvidia,darcy - nvidia,p2371-0000 - nvidia,p2371-2180 - nvidia,p2571 + - nvidia,p2894-0050-a08 - const: nvidia,tegra210 - items: - enum: -- cgit v1.2.3 From 4915255bfcae85ffed97150df7c445120f67a64f Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Tue, 8 Jan 2019 12:51:39 -0200 Subject: media: i2c: mt9m001: dt: add binding for mt9m001 Add device tree binding documentation for the MT9M001 CMOS image sensor. Cc: Guennadi Liakhovetski Signed-off-by: Akinobu Mita Reviewed-by: Rob Herring Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/i2c/mt9m001.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/mt9m001.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/mt9m001.txt b/Documentation/devicetree/bindings/media/i2c/mt9m001.txt new file mode 100644 index 000000000000..c920552b03ef --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/mt9m001.txt @@ -0,0 +1,38 @@ +MT9M001: 1/2-Inch Megapixel Digital Image Sensor + +The MT9M001 is an SXGA-format with a 1/2-inch CMOS active-pixel digital +image sensor. It is programmable through I2C interface. + +Required Properties: + +- compatible: shall be "onnn,mt9m001". +- clocks: reference to the master clock into sensor + +Optional Properties: + +- reset-gpios: GPIO handle which is connected to the reset pin of the chip. + Active low. +- standby-gpios: GPIO handle which is connected to the standby pin of the chip. + Active high. + +The device node must contain one 'port' child node with one 'endpoint' child +sub-node for its digital output video port, in accordance with the video +interface bindings defined in: +Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + + &i2c1 { + camera-sensor@5d { + compatible = "onnn,mt9m001"; + reg = <0x5d>; + reset-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + standby-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + clocks = <&camera_clk>; + port { + mt9m001_out: endpoint { + remote-endpoint = <&vcap_in>; + }; + }; + }; + }; -- cgit v1.2.3 From 0e79cb7010f237a1d63b74cbfa51783eb162a3b2 Mon Sep 17 00:00:00 2001 From: Timo Alho Date: Thu, 24 Jan 2019 19:03:55 +0200 Subject: dt-bindings: firmware: Add bindings for Tegra210 BPMP The BPMP is a specific processor in Tegra210 chip, which is designed for boot process handling, assisting in entering deep low power states (suspend to ram), and offloading DRAM memory clock scaling on some platforms. Signed-off-by: Timo Alho Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/firmware/nvidia,tegra210-bpmp.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra210-bpmp.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra210-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra210-bpmp.txt new file mode 100644 index 000000000000..68d814e8c09d --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra210-bpmp.txt @@ -0,0 +1,35 @@ +NVIDIA Tegra210 Boot and Power Management Processor (BPMP) + +The Boot and Power Management Processor (BPMP) is a co-processor found +in Tegra210 SoC. It is designed to handle the early stages of the boot +process as well as to assisting in entering deep low power state +(suspend to ram), and also offloading DRAM memory clock scaling on +some platforms. The binding document defines the resources that would +be used by the BPMP T210 firmware driver, which can create the +interprocessor communication (IPC) between the CPU and BPMP. + +Required properties: +- compatible + Array of strings + One of: + - "nvidia,tegra210-bpmp" +- reg: physical base address and length for HW synchornization primitives + 1) base address and length to Tegra 'atomics' hardware + 2) base address and length to Tegra 'semaphore' hardware +- interrupts: specifies the interrupt number for receiving messages ("rx") + and for triggering messages ("tx") + +Optional properties: +- #clock-cells : Should be 1 for platforms where DRAM clock control is + offloaded to bpmp. + +Example: + +bpmp@70016000 { + compatible = "nvidia,tegra210-bpmp"; + reg = <0x0 0x70016000 0x0 0x2000 + 0x0 0x60001000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "tx", "rx"; +}; -- cgit v1.2.3 From 22daf9104902456654da984a31989301b4151967 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Jan 2019 15:47:40 +0100 Subject: dt-bindings: firmware: tegra186-bpmp: Remove name property This property is not used by device trees and was likely supposed to be a hint as to what the BPMP node should be named, rather than describing a property of the BPMP node. Suggested-by: Jon Hunter Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt index 0c10802c8327..ff380dadb5f9 100644 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt @@ -8,7 +8,6 @@ which can create the interprocessor communication (IPC) between the CPU and BPMP. Required properties: -- name : Should be bpmp - compatible Array of strings One of: -- cgit v1.2.3 From bfd74e65c47ff325924fe5bd90789b1db422c9cc Mon Sep 17 00:00:00 2001 From: Shunli Wang Date: Tue, 22 Jan 2019 14:39:09 +0800 Subject: ASoC: mediatek: mt8183: add audio afe document Signed-off-by: Shunli Wang Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/mt8183-afe-pcm.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt new file mode 100644 index 000000000000..396ba38619f6 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt @@ -0,0 +1,36 @@ +Mediatek AFE PCM controller for mt8183 + +Required properties: +- compatible = "mediatek,mt68183-audio"; +- reg: register location and size +- interrupts: should contain AFE interrupt +- power-domains: should define the power domain +- clocks: Must contain an entry for each entry in clock-names +- clock-names: should have these clock names: + "infra_sys_audio_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_aud_intbus", + "top_sys_pll3_d4", + "top_clk26m_clk"; + +Example: + + afe: mt8183-afe-pcm@11220000 { + compatible = "mediatek,mt8183-audio"; + reg = <0 0x11220000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8183_POWER_DOMAIN_AUDIO>; + clocks = <&infrasys CLK_INFRA_AUDIO>, + <&infrasys CLK_INFRA_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_MUX_AUDIO>, + <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&topckgen CLK_TOP_SYSPLL_D2_D4>, + <&clk26m>; + clock-names = "infra_sys_audio_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_aud_intbus", + "top_sys_pll_d2_d4", + "top_clk26m_clk"; + }; -- cgit v1.2.3 From 7ca80f232e810b758ba72daef8f189c34a20bd32 Mon Sep 17 00:00:00 2001 From: Shunli Wang Date: Tue, 22 Jan 2019 14:39:11 +0800 Subject: ASoC: mediatek: mt6358: add codec document Signed-off-by: Shunli Wang Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/mt6358.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mt6358.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/mt6358.txt b/Documentation/devicetree/bindings/sound/mt6358.txt new file mode 100644 index 000000000000..5465730013a1 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt6358.txt @@ -0,0 +1,18 @@ +Mediatek MT6358 Audio Codec + +The communication between MT6358 and SoC is through Mediatek PMIC wrapper. +For more detail, please visit Mediatek PMIC wrapper documentation. + +Must be a child node of PMIC wrapper. + +Required properties: + +- compatible : "mediatek,mt6358-sound". +- Avdd-supply : power source of AVDD + +Example: + +mt6358_snd { + compatible = "mediatek,mt6358-sound"; + Avdd-supply = <&mt6358_vaud28_reg>; +}; -- cgit v1.2.3 From afa974b771281fd89e8fdcb71152152f17fb8303 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 17 Jan 2019 19:02:43 +0900 Subject: kbuild: add real-prereqs shorthand for $(filter-out FORCE,$^) In Kbuild, if_changed and friends must have FORCE as a prerequisite. Hence, $(filter-out FORCE,$^) or $(filter-out $(PHONY),$^) is a common idiom to get the names of all the prerequisites except phony targets. Add real-prereqs as a shorthand. Note: We cannot replace $(filter %.o,$^) in cmd_link_multi-m because $^ may include auto-generated dependencies from the .*.cmd file when a single object module is changed into a multi object module. Refer to commit 69ea912fda74 ("kbuild: remove unneeded link_multi_deps"). I added some comment to avoid accidental breakage. Signed-off-by: Masahiro Yamada Acked-by: Rob Herring --- Documentation/devicetree/bindings/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile index 6e5cef0ed6fb..e4eb5d1ea3b5 100644 --- a/Documentation/devicetree/bindings/Makefile +++ b/Documentation/devicetree/bindings/Makefile @@ -15,7 +15,7 @@ DT_TMP_SCHEMA := processed-schema.yaml extra-y += $(DT_TMP_SCHEMA) quiet_cmd_mk_schema = SCHEMA $@ - cmd_mk_schema = $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $(filter-out FORCE, $^) + cmd_mk_schema = $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $(real-prereqs) DT_DOCS = $(shell cd $(srctree)/$(src) && find * -name '*.yaml') DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS)) -- cgit v1.2.3 From 4cab5bf616f6513b2111ce80f634a9a07c037a0a Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 21 Jan 2019 18:10:42 -0800 Subject: dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs The driver now supports i.MX8MQ, so update bindings accordingly. Cc: p.zabel@pengutronix.de Cc: Fabio Estevam Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Andrey Smirnov Signed-off-by: Philipp Zabel --- Documentation/devicetree/bindings/reset/fsl,imx7-src.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt index 1ab1d109318e..2ecf33815d18 100644 --- a/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt +++ b/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt @@ -5,7 +5,9 @@ Please also refer to reset.txt in this directory for common reset controller binding usage. Required properties: -- compatible: Should be "fsl,imx7d-src", "syscon" +- compatible: + - For i.MX7 SoCs should be "fsl,imx7d-src", "syscon" + - For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon" - reg: should be register base and length as documented in the datasheet - interrupts: Should contain SRC interrupt @@ -44,4 +46,5 @@ Example: For list of all valid reset indicies see - + for i.MX7 and + for i.MX8MQ -- cgit v1.2.3 From 0807caf647dd150cbc3f3efaff7b6a9136aa7e6f Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 15 Jan 2019 10:44:05 -0800 Subject: dt-bindings: reset: Add document for Broadcom STB reset controller Add a binding document for the Broadcom STB reset controller, also known as SW_INIT-style reset controller. Signed-off-by: Florian Fainelli Reviewed-by: Rob Herring Signed-off-by: Philipp Zabel --- .../bindings/reset/brcm,brcmstb-reset.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt b/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt new file mode 100644 index 000000000000..6e5341b4f891 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt @@ -0,0 +1,27 @@ +Broadcom STB SW_INIT-style reset controller +=========================================== + +Broadcom STB SoCs have a SW_INIT-style reset controller with separate +SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit +reset lines. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: should be brcm,brcmstb-reset +- reg: register base and length +- #reset-cells: must be set to 1 + +Example: + + reset: reset-controller@8404318 { + compatible = "brcm,brcmstb-reset"; + reg = <0x8404318 0x30>; + #reset-cells = <1>; + }; + + ðernet_switch { + resets = <&reset>; + reset-names = "switch"; + }; -- cgit v1.2.3 From b266d6e496a8c61a2d120960678b1bd97803a0ad Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Mon, 21 Jan 2019 14:32:46 -0700 Subject: dt-bindings: usb: Add support for msm8998 msm8998 USB has a dwc3 controller just like the existing sdm845 support. Signed-off-by: Jeffrey Hugo Reviewed-by: Bjorn Andersson Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt index 95afdcf3c337..cb695aa3fba4 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Compatible list, contains "qcom,dwc3" "qcom,msm8996-dwc3" for msm8996 SOC. + "qcom,msm8998-dwc3" for msm8998 SOC. "qcom,sdm845-dwc3" for sdm845 SOC. - reg: Offset and length of register set for QSCRATCH wrapper - power-domains: specifies a phandle to PM domain provider node -- cgit v1.2.3 From d26c05781e08472861dcad4764d4f1585051638c Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Thu, 10 Jan 2019 17:04:29 +0200 Subject: dt-bindings: usb: keystone-usb: Add ti,am654-dwc3 support The AM654 SoC from TI contains a DWC3 controller. Add support for it. Reviewed-by: Rob Herring Signed-off-by: Roger Quadros Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/keystone-usb.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/keystone-usb.txt b/Documentation/devicetree/bindings/usb/keystone-usb.txt index f96e09f784cc..77df82e36138 100644 --- a/Documentation/devicetree/bindings/usb/keystone-usb.txt +++ b/Documentation/devicetree/bindings/usb/keystone-usb.txt @@ -3,7 +3,9 @@ TI Keystone Soc USB Controller DWC3 GLUE Required properties: - - compatible: should be "ti,keystone-dwc3". + - compatible: should be + "ti,keystone-dwc3" for Keystone 2 SoCs + "ti,am654-dwc3" for AM654 SoC - #address-cells, #size-cells : should be '1' if the device has sub-nodes with 'reg' property. - reg : Address and length of the register set for the USB subsystem on @@ -21,7 +23,7 @@ SoCs only: - clock-names: Must be "usb". -The following are mandatory properties for Keystone 2 66AK2G SoCs only: +The following are mandatory properties for 66AK2G and AM654: - power-domains: Should contain a phandle to a PM domain provider node and an args specifier containing the USB device id -- cgit v1.2.3 From 35ed6229c0f0d079f28b22b60b0af3114f9226fb Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:22:18 +0000 Subject: usb: gadget: udc: renesas_usb3: Add bindings for r8a774c0 Document RZ/G2E (R8A774C0) SoC bindings. Reviewed-by: Rob Herring Reviewed-by: Simon Horman Reviewed-by: Yoshihiro Shimoda Signed-off-by: Fabrizio Castro Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/renesas_usb3.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/renesas_usb3.txt b/Documentation/devicetree/bindings/usb/renesas_usb3.txt index d366555166d0..35039e720515 100644 --- a/Documentation/devicetree/bindings/usb/renesas_usb3.txt +++ b/Documentation/devicetree/bindings/usb/renesas_usb3.txt @@ -3,6 +3,7 @@ Renesas Electronics USB3.0 Peripheral driver Required properties: - compatible: Must contain one of the following: - "renesas,r8a774a1-usb3-peri" + - "renesas,r8a774c0-usb3-peri" - "renesas,r8a7795-usb3-peri" - "renesas,r8a7796-usb3-peri" - "renesas,r8a77965-usb3-peri" -- cgit v1.2.3 From 539cf1039165ac59d217d916bc8f88bde8be73bd Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:21:03 +0000 Subject: dt-bindings: usb: renesas_usbhs: Add r8a774c0 support Document RZ/G2E (R8A774C0) SoC bindings. Reviewed-by: Rob Herring Reviewed-by: Simon Horman Reviewed-by: Yoshihiro Shimoda Signed-off-by: Fabrizio Castro Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt index 90719f501852..d93b6a1504f2 100644 --- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt +++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt @@ -7,6 +7,7 @@ Required properties: - "renesas,usbhs-r8a7744" for r8a7744 (RZ/G1N) compatible device - "renesas,usbhs-r8a7745" for r8a7745 (RZ/G1E) compatible device - "renesas,usbhs-r8a774a1" for r8a774a1 (RZ/G2M) compatible device + - "renesas,usbhs-r8a774c0" for r8a774c0 (RZ/G2E) compatible device - "renesas,usbhs-r8a7790" for r8a7790 (R-Car H2) compatible device - "renesas,usbhs-r8a7791" for r8a7791 (R-Car M2-W) compatible device - "renesas,usbhs-r8a7792" for r8a7792 (R-Car V2H) compatible device -- cgit v1.2.3 From cdbbb8ec5a8078630b777e0b56e3b39c1e7cd76a Mon Sep 17 00:00:00 2001 From: Yogesh Narayan Gaur Date: Tue, 15 Jan 2019 12:00:20 +0000 Subject: dt-bindings: spi: add binding file for NXP FlexSPI controller Add binding file for NXP FlexSPI controller Signed-off-by: Yogesh Narayan Gaur Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/spi-nxp-fspi.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt new file mode 100644 index 000000000000..2cd67eb727d4 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt @@ -0,0 +1,39 @@ +* NXP Flex Serial Peripheral Interface (FSPI) + +Required properties: + - compatible : Should be "nxp,lx2160a-fspi" + - reg : First contains the register location and length, + Second contains the memory mapping address and length + - reg-names : Should contain the resource reg names: + - fspi_base: configuration register address space + - fspi_mmap: memory mapped address space + - interrupts : Should contain the interrupt for the device + +Required SPI slave node properties: + - reg : There are two buses (A and B) with two chip selects each. + This encodes to which bus and CS the flash is connected: + - <0>: Bus A, CS 0 + - <1>: Bus A, CS 1 + - <2>: Bus B, CS 0 + - <3>: Bus B, CS 1 + +Example showing the usage of two SPI NOR slave devices on bus A: + +fspi0: spi@20c0000 { + compatible = "nxp,lx2160a-fspi"; + reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <0 25 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "fspi_en", "fspi"; + + mt35xu512aba0: flash@0 { + reg = <0>; + .... + }; + + mt35xu512aba1: flash@1 { + reg = <1>; + .... + }; +}; -- cgit v1.2.3 From c1c9d41319c35daa099b2e6cd1325e3ae55cfda8 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Tue, 22 Jan 2019 10:17:13 +0000 Subject: dt-bindings: imx: Add pinctrl binding doc for imx8mm Add binding doc imx8mm pinctrl driver. Signed-off-by: Bai Ping Acked-by: Aisheng Dong Signed-off-by: Linus Walleij --- .../bindings/pinctrl/fsl,imx8mm-pinctrl.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt new file mode 100644 index 000000000000..524a16fca666 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt @@ -0,0 +1,36 @@ +* Freescale IMX8MM IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory +for common binding part and usage. + +Required properties: +- compatible: "fsl,imx8mm-iomuxc" +- reg: should contain the base physical address and size of the iomuxc + registers. + +Required properties in sub-nodes: +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in + . The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX8M Mini + Reference Manual for detailed CONFIG settings. + +Examples: + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mm-iomuxc"; + reg = <0x0 0x30330000 0x0 0x10000>; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; +}; -- cgit v1.2.3 From 24de022b8171fb84f87c22ad1714018fd982c834 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 25 Jan 2019 03:21:30 +0530 Subject: dt-bindings: display: Add Sitronix ST7701 panel documentation Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI LCD panel with inbuilt ST7701 chip. The default regulator names in ST7701 chip is renamed in Techstar TS8550B so, add specific binding names for them. Signed-off-by: Jagan Teki Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20190124215131.17452-1-jagan@amarulasolutions.com --- .../bindings/display/panel/sitronix,st7701.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/sitronix,st7701.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/sitronix,st7701.txt b/Documentation/devicetree/bindings/display/panel/sitronix,st7701.txt new file mode 100644 index 000000000000..ccd17597f1f6 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7701.txt @@ -0,0 +1,30 @@ +Sitronix ST7701 based LCD panels + +ST7701 designed for small and medium sizes of TFT LCD display, is +capable of supporting up to 480RGBX864 in resolution. It provides +several system interfaces like MIPI/RGB/SPI. + +Techstar TS8550B is 480x854, 2-lane MIPI DSI LCD panel which has +inbuilt ST7701 chip. + +Required properties: +- compatible: must be "sitronix,st7701" and one of + * "techstar,ts8550b" +- reset-gpios: a GPIO phandle for the reset pin + +Required properties for techstar,ts8550b: +- reg: DSI virtual channel used by that screen +- VCC-supply: analog regulator for MIPI circuit +- IOVCC-supply: I/O system regulator + +Optional properties: +- backlight: phandle for the backlight control. + +panel@0 { + compatible = "techstar,ts8550b", "sitronix,st7701"; + reg = <0>; + VCC-supply = <®_dldo2>; + IOVCC-supply = <®_dldo2>; + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */ + backlight = <&backlight>; +}; -- cgit v1.2.3 From 6f4fcfe0297c3b5d71157d2898a706025cc83c2b Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 7 Nov 2018 19:18:39 +0100 Subject: dt-bindings: Add vendor prefix for LeMaker This introduces a new device-tree binding vendor prefix for Shenzhen LeMaker Technology Co., Ltd. This vendor was already in use but it was not documented until now. Signed-off-by: Paul Kocialkowski Reviewed-by: Rob Hering Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20181107181843.27628-5-contact@paulk.fr --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..1d168ed55f8e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -211,6 +211,7 @@ laird Laird PLC lantiq Lantiq Semiconductor lattice Lattice Semiconductor lego LEGO Systems A/S +lemaker Shenzhen LeMaker Technology Co., Ltd. lenovo Lenovo Group Ltd. lg LG Corporation libretech Shenzhen Libre Technology Co., Ltd -- cgit v1.2.3 From 78d1773f8eb59a03d5e34176cdb3776638bf3403 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 7 Nov 2018 19:18:40 +0100 Subject: dt-bindings: display: Add bindings for the LeMaker BL035-RGB-002 LCD panel This adds the device-tree bindings for the LeMaker BL035-RGB-002 3.5" QVGA TFT LCD panel, compatible with simple-panel. Signed-off-by: Paul Kocialkowski Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20181107181843.27628-6-contact@paulk.fr --- .../bindings/display/panel/lemaker,bl035-rgb-002.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/lemaker,bl035-rgb-002.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/lemaker,bl035-rgb-002.txt b/Documentation/devicetree/bindings/display/panel/lemaker,bl035-rgb-002.txt new file mode 100644 index 000000000000..74ee7ea6b493 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/lemaker,bl035-rgb-002.txt @@ -0,0 +1,12 @@ +LeMaker BL035-RGB-002 3.5" QVGA TFT LCD panel + +Required properties: +- compatible: should be "lemaker,bl035-rgb-002" +- power-supply: as specified in the base binding + +Optional properties: +- backlight: as specified in the base binding +- enable-gpios: as specified in the base binding + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- cgit v1.2.3 From 20e3412b0db2928d91c7540940080c42afbd8c84 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 14 Jan 2019 09:43:26 +0000 Subject: dt-bindings: Add vendor prefix for PDA Precision Design Associates, Inc. Precision Design Associates, Inc. (PDA) manufactures standard and custom capacitive touch screens, LCD's embedded controllers and custom embedded software. They specialize in industrial, rugged and outdoor applications. Website: http://www.pdaatl.com/ Signed-off-by: Eugen Hristev Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/1547458584-29548-2-git-send-email-eugen.hristev@microchip.com --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1d168ed55f8e..4f225ce815d8 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -298,6 +298,7 @@ ovti OmniVision Technologies oxsemi Oxford Semiconductor, Ltd. panasonic Panasonic Corporation parade Parade Technologies Inc. +pda Precision Design Associates, Inc. pericom Pericom Technology Inc. pervasive Pervasive Displays, Inc. phicomm PHICOMM Co., Ltd. -- cgit v1.2.3 From b3b54ed1731cfd809c5d02b3334977619cece3bf Mon Sep 17 00:00:00 2001 From: Cristian Birsan Date: Mon, 14 Jan 2019 09:43:28 +0000 Subject: dt-bindings: display: Add support for PDA 91-00156-A0 panel PDA 91-00156-A0 5.0 is a 5.0" WVGA TFT LCD panel. This panel with backlight is found in PDA 5" LCD screen (TM5000 series or AC320005-5). Adding device tree bindings for this panel. Signed-off-by: Cristian Birsan [eugen.hristev@microchip.com]: specified backlight and supply bindings Signed-off-by: Eugen Hristev Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/1547458584-29548-3-git-send-email-eugen.hristev@microchip.com --- .../devicetree/bindings/display/panel/pda,91-00156-a0.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt b/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt new file mode 100644 index 000000000000..1639fb17a9f0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt @@ -0,0 +1,14 @@ +PDA 91-00156-A0 5.0" WVGA TFT LCD panel + +Required properties: +- compatible: should be "pda,91-00156-a0" +- power-supply: this panel requires a single power supply. A phandle to a +regulator needs to be specified here. Compatible with panel-common binding which +is specified in the panel-common.txt in this directory. +- backlight: this panel's backlight is controlled by an external backlight +controller. A phandle to this controller needs to be specified here. +Compatible with panel-common binding which is specified in the panel-common.txt +in this directory. + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- cgit v1.2.3 From 262ff68fce8fe388bfa60efc95e394cf0a149563 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 28 Jan 2019 14:27:46 +0000 Subject: ASoC: dt-bindings: update wcd9335 bindings. This patch updates wcd9335 bindings with recommended properties. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/qcom,wcd9335.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd9335.txt b/Documentation/devicetree/bindings/sound/qcom,wcd9335.txt index 1d8d49e30af7..5d6ea66a863f 100644 --- a/Documentation/devicetree/bindings/sound/qcom,wcd9335.txt +++ b/Documentation/devicetree/bindings/sound/qcom,wcd9335.txt @@ -34,12 +34,12 @@ Required properties with SLIMbus Interface: Definition: Interrupt names of WCD INTR1 and INTR2 Should be: "intr1", "intr2" -- reset-gpio: +- reset-gpios: Usage: required Value type: Definition: Reset gpio line -- qcom,ifd: +- slim-ifc-dev: Usage: required Value type: Definition: SLIM interface device @@ -104,13 +104,13 @@ Required properties with SLIMbus Interface: Value type: Definition: Must be 1 -codec@1{ +audio-codec@1{ compatible = "slim217,1a0"; reg = <1 0>; interrupts = <&msmgpio 54 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "intr2" - reset-gpio = <&msmgpio 64 0>; - qcom,ifd = <&wc9335_ifd>; + reset-gpios = <&msmgpio 64 0>; + slim-ifc-dev = <&wc9335_ifd>; clock-names = "mclk", "native"; clocks = <&rpmcc RPM_SMD_DIV_CLK1>, <&rpmcc RPM_SMD_BB_CLK1>; -- cgit v1.2.3 From 4571a7d814add6bddc91594c0d5862df1504c183 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 28 Jan 2019 21:55:02 +0100 Subject: dt-bindings: sram: sunxi: Add compatible for the H6 SRAM C1 This introduces a new compatible for the H6 SRAM C1 section, that is compatible with the SRAM C1 section as found on the A10. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/sram/sunxi-sram.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt index ab5a70bb9a64..380246a805f2 100644 --- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt +++ b/Documentation/devicetree/bindings/sram/sunxi-sram.txt @@ -63,6 +63,7 @@ The valid sections compatible for H5 are: The valid sections compatible for H6 are: - allwinner,sun50i-h6-sram-c, allwinner,sun50i-a64-sram-c + - allwinner,sun50i-h6-sram-c1, allwinner,sun4i-a10-sram-c1 The valid sections compatible for F1C100s are: - allwinner,suniv-f1c100s-sram-d, allwinner,sun4i-a10-sram-d -- cgit v1.2.3 From 494a3503d684b6fc497623bc01e3e16f8def0499 Mon Sep 17 00:00:00 2001 From: Cheng-Yi Chiang Date: Sat, 19 Jan 2019 19:33:31 +0800 Subject: ASoC: Documentation: Add google, cros-ec-codec Add documentation for Chrome EC codec driver. Signed-off-by: Cheng-Yi Chiang Signed-off-by: Mark Brown --- .../bindings/sound/google,cros-ec-codec.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/google,cros-ec-codec.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/google,cros-ec-codec.txt b/Documentation/devicetree/bindings/sound/google,cros-ec-codec.txt new file mode 100644 index 000000000000..1084f7f22eea --- /dev/null +++ b/Documentation/devicetree/bindings/sound/google,cros-ec-codec.txt @@ -0,0 +1,26 @@ +* Audio codec controlled by ChromeOS EC + +Google's ChromeOS EC codec is a digital mic codec provided by the +Embedded Controller (EC) and is controlled via a host-command interface. + +An EC codec node should only be found as a sub-node of the EC node (see +Documentation/devicetree/bindings/mfd/cros-ec.txt). + +Required properties: +- compatible: Must contain "google,cros-ec-codec" +- #sound-dai-cells: Should be 1. The cell specifies number of DAIs. +- max-dmic-gain: A number for maximum gain in dB on digital microphone. + +Example: + +cros-ec@0 { + compatible = "google,cros-ec-spi"; + + ... + + cros_ec_codec: ec-codec { + compatible = "google,cros-ec-codec"; + #sound-dai-cells = <1>; + max-dmic-gain = <43>; + }; +}; -- cgit v1.2.3 From 3f1b66be4aaa5dbe0a16197bfdfc355cf1da7701 Mon Sep 17 00:00:00 2001 From: Nava kishore Manne Date: Fri, 25 Jan 2019 13:16:53 +0530 Subject: dt-bindings: reset: Add bindings for ZynqMP reset driver Add documentation to describe Xilinx ZynqMP reset driver bindings. Signed-off-by: Nava kishore Manne Signed-off-by: Jolly Shah Reviewed-by: Rob Herring Signed-off-by: Michal Simek --- .../bindings/reset/xlnx,zynqmp-reset.txt | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt new file mode 100644 index 000000000000..27a45fe5ecf1 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt @@ -0,0 +1,52 @@ +-------------------------------------------------------------------------- + = Zynq UltraScale+ MPSoC reset driver binding = +-------------------------------------------------------------------------- +The Zynq UltraScale+ MPSoC has several different resets. + +See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information +about zynqmp resets. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required Properties: +- compatible: "xlnx,zynqmp-reset" +- #reset-cells: Specifies the number of cells needed to encode reset + line, should be 1 + +------- +Example +------- + +firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + + zynqmp_reset: reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; + }; +}; + +Specifying reset lines connected to IP modules +============================================== + +Device nodes that need access to reset lines should +specify them as a reset phandle in their corresponding node as +specified in reset.txt. + +For list of all valid reset indicies see + + +Example: + +serdes: zynqmp_phy@fd400000 { + ... + + resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; + reset-names = "sata_rst"; + + ... +}; -- cgit v1.2.3 From b8be1cd9b010da726907a38b7a43d7259db51081 Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Tue, 18 Dec 2018 11:32:37 -0700 Subject: drm/msm: drop interrupt-names Each GPU core only uses one interrupt so we don't to look up an interrupt by name and thereby we don't need interrupt-names. Signed-off-by: Jordan Crouse Reviewed-by: Rob Herring Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/gpu.txt | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index ac8df3b871f9..f8759145ce1a 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -27,7 +27,6 @@ Example: reg = <0x04300000 0x20000>; reg-names = "kgsl_3d0_reg_memory"; interrupts = ; - interrupt-names = "kgsl_3d0_irq"; clock-names = "core", "iface", -- cgit v1.2.3 From 740f9433a85408039aac33eb7f62a6a8d552d983 Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Tue, 18 Dec 2018 11:32:40 -0700 Subject: dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings Update the GPU bindings and document the new bindings for the GMU device found with Adreno a6xx targets. Signed-off-by: Jordan Crouse Reviewed-by: Rob Herring Signed-off-by: Rob Clark --- .../devicetree/bindings/display/msm/gpu.txt | 42 ++++++++++++++++++++-- 1 file changed, 39 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index f8759145ce1a..aad1aef682f7 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -10,14 +10,23 @@ Required properties: If "amd,imageon" is used, there should be no top level msm device. - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt signal from the gpu. -- clocks: device clocks +- clocks: device clocks (if applicable) See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required: +- clock-names: the following clocks are required by a3xx, a4xx and a5xx + cores: * "core" * "iface" * "mem_iface" + For GMU attached devices the GPU clocks are not used and are not required. The + following devices should not list clocks: + - qcom,adreno-630.2 +- iommus: optional phandle to an adreno iommu instance +- operating-points-v2: optional phandle to the OPP operating points +- qcom,gmu: For GMU attached devices a phandle to the GMU device that will + control the power for the GPU. Applicable targets: + - qcom,adreno-630.2 -Example: +Example 3xx/4xx/a5xx: / { ... @@ -37,3 +46,30 @@ Example: <&mmcc MMSS_IMEM_AHB_CLK>; }; }; + +Example a6xx (with GMU): + +/ { + ... + + gpu@5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0x5000000 0x40000>, <0x509e000 0x10>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem"; + + /* + * Look ma, no clocks! The GPU clocks and power are + * controlled entirely by the GMU + */ + + interrupts = ; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + }; +}; -- cgit v1.2.3 From 8aa82766de12d11a7e00d02b6d74349f57a8219e Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Wed, 16 Jan 2019 14:09:51 -0700 Subject: dt-bindings: drm/msm/a6xx: Document GMU bindings Commit 24937c540917 ("dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings") mistakenly omitted the GMU bindings as seen in [1]. Return them to their rightful place. [1] https://patchwork.freedesktop.org/patch/268679/ Signed-off-by: Jordan Crouse Reviewed-by: Rob Herring Signed-off-by: Rob Clark --- .../devicetree/bindings/display/msm/gmu.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt new file mode 100644 index 000000000000..3439b38e60f2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt @@ -0,0 +1,59 @@ +Qualcomm adreno/snapdragon GMU (Graphics management unit) + +The GMU is a programmable power controller for the GPU. the CPU controls the +GMU which in turn handles power controls for the GPU. + +Required properties: +- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu" + for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu" + Note that you need to list the less specific "qcom,adreno-gmu" + for generic matches and the more specific identifier to identify + the specific device. +- reg: Physical base address and length of the GMU registers. +- reg-names: Matching names for the register regions + * "gmu" + * "gmu_pdc" + * "gmu_pdc_seg" +- interrupts: The interrupt signals from the GMU. +- interrupt-names: Matching names for the interrupts + * "hfi" + * "gmu" +- clocks: phandles to the device clocks +- clock-names: Matching names for the clocks + * "gmu" + * "cxo" + * "axi" + * "mnoc" +- power-domains: should be <&clock_gpucc GPU_CX_GDSC> +- iommus: phandle to the adreno iommu +- operating-points-v2: phandle to the OPP operating points + +Example: + +/ { + ... + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb280000 0x10000>, + <0xb480000 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + }; +}; -- cgit v1.2.3 From 0eca80bf07eb51cf7accf44dbf71547fd0bba5dd Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Tue, 29 Jan 2019 14:35:34 +0100 Subject: dt-bindings: regulator: add DT bindings for max77650 Add the DT binding document for max77650 regulators. Signed-off-by: Bartosz Golaszewski Signed-off-by: Mark Brown --- .../bindings/regulator/max77650-regulator.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/max77650-regulator.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/max77650-regulator.txt b/Documentation/devicetree/bindings/regulator/max77650-regulator.txt new file mode 100644 index 000000000000..f1cbe813c30f --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/max77650-regulator.txt @@ -0,0 +1,41 @@ +Regulator driver for MAX77650 PMIC from Maxim Integrated. + +This module is part of the MAX77650 MFD device. For more details +see Documentation/devicetree/bindings/mfd/max77650.txt. + +The regulator controller is represented as a sub-node of the PMIC node +on the device tree. + +The device has a single LDO regulator and a SIMO buck-boost regulator with +three independent power rails. + +Required properties: +-------------------- +- compatible: Must be "maxim,max77650-regulator" + +Each rail must be instantiated under the regulators subnode of the top PMIC +node. Up to four regulators can be defined. For standard regulator properties +refer to Documentation/devicetree/bindings/regulator/regulator.txt. + +Available regulator compatible strings are: "ldo", "sbb0", "sbb1", "sbb2". + +Example: +-------- + + regulators { + compatible = "maxim,max77650-regulator"; + + max77650_ldo: regulator@0 { + regulator-compatible = "ldo"; + regulator-name = "max77650-ldo"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <2937500>; + }; + + max77650_sbb0: regulator@1 { + regulator-compatible = "sbb0"; + regulator-name = "max77650-sbb0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1587500>; + }; + }; -- cgit v1.2.3 From 27e27e6555d3a1dd3c906796af6d8e7eb538857f Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Tue, 29 Jan 2019 16:04:44 +0800 Subject: dt-bindings: ASoC: Add Spreadtrum DMA platform documentation Add documentation for Spreadtrum DMA platform driver. Signed-off-by: Baolin Wang Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/sprd-pcm.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/sprd-pcm.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/sprd-pcm.txt b/Documentation/devicetree/bindings/sound/sprd-pcm.txt new file mode 100644 index 000000000000..4b23e84b2e57 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/sprd-pcm.txt @@ -0,0 +1,23 @@ +* Spreadtrum DMA platfrom bindings + +Required properties: +- compatible: Should be "sprd,pcm-platform". +- dmas: Specify the list of DMA controller phandle and DMA request line ordered pairs. +- dma-names: Identifier string for each DMA request line in the dmas property. + These strings correspond 1:1 with the ordered pairs in dmas. + +Example: + + audio_platform:platform@0 { + compatible = "sprd,pcm-platform"; + dmas = <&agcp_dma 1 1>, <&agcp_dma 2 2>, + <&agcp_dma 3 3>, <&agcp_dma 4 4>, + <&agcp_dma 5 5>, <&agcp_dma 6 6>, + <&agcp_dma 7 7>, <&agcp_dma 8 8>, + <&agcp_dma 9 9>, <&agcp_dma 10 10>; + dma-names = "normal_p_l", "normal_p_r", + "normal_c_l", "normal_c_r", + "voice_c", "fast_p", + "loop_c", "loop_p", + "voip_c", "voip_p"; + }; -- cgit v1.2.3 From 3a50365d8c7924d120050126900ec7eeef77bf02 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 27 Jan 2019 02:04:04 +0100 Subject: serial: 8250: Add OF support for Xscale variant This adds support for device tree probing for the Intel Xscale 8250 variant needed to support device tree on the Intel IXP4xx platforms. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/8250.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/8250.txt b/Documentation/devicetree/bindings/serial/8250.txt index da50321da34d..3cba12f855b7 100644 --- a/Documentation/devicetree/bindings/serial/8250.txt +++ b/Documentation/devicetree/bindings/serial/8250.txt @@ -21,6 +21,7 @@ Required properties: - "altr,16550-FIFO128" - "fsl,16550-FIFO64" - "fsl,ns16550" + - "intel,xscale-uart" - "ti,da830-uart" - "aspeed,ast2400-vuart" - "aspeed,ast2500-vuart" -- cgit v1.2.3 From e81eba88cf371bab8d14cdd5768709090cd9eb95 Mon Sep 17 00:00:00 2001 From: Zhou Yanjie Date: Tue, 29 Jan 2019 01:03:49 +0800 Subject: Dt-bindings: Serial: Add X1000 serial bindings. Add the serial bindings for the X1000 Soc from Ingenic. Signed-off-by: Zhou Yanjie Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/ingenic,uart.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.txt b/Documentation/devicetree/bindings/serial/ingenic,uart.txt index c3c6406d5cfe..24ed8769f4af 100644 --- a/Documentation/devicetree/bindings/serial/ingenic,uart.txt +++ b/Documentation/devicetree/bindings/serial/ingenic,uart.txt @@ -6,7 +6,8 @@ Required properties: - "ingenic,jz4760-uart", - "ingenic,jz4770-uart", - "ingenic,jz4775-uart", - - "ingenic,jz4780-uart". + - "ingenic,jz4780-uart", + - "ingenic,x1000-uart". - reg : offset and length of the register set for the device. - interrupts : should contain uart interrupt. - clocks : phandles to the module & baud clocks. -- cgit v1.2.3 From 05da213f1c7781407acff10438daf4332407bb52 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 23 Jan 2019 11:28:18 +0100 Subject: dt-bindings: serial: Add bindings for nvidia,tegra194-tcu Add bindings for the Tegra Combined UART device used to talk to the UART console on Tegra194 systems. Signed-off-by: Mikko Perttunen Reviewed-by: Rob Herring Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Thierry Reding Signed-off-by: Greg Kroah-Hartman --- .../bindings/serial/nvidia,tegra194-tcu.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt new file mode 100644 index 000000000000..085a8591accd --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt @@ -0,0 +1,35 @@ +NVIDIA Tegra Combined UART (TCU) + +The TCU is a system for sharing a hardware UART instance among multiple +systems within the Tegra SoC. It is implemented through a mailbox- +based protocol where each "virtual UART" has a pair of mailboxes, one +for transmitting and one for receiving, that is used to communicate +with the hardware implementing the TCU. + +Required properties: +- name : Should be tcu +- compatible + Array of strings + One of: + - "nvidia,tegra194-tcu" +- mbox-names: + "rx" - Mailbox for receiving data from hardware UART + "tx" - Mailbox for transmitting data to hardware UART +- mboxes: Mailboxes corresponding to the mbox-names. + +This node is a mailbox consumer. See the following files for details of +the mailbox subsystem, and the specifiers implemented by the relevant +provider(s): + +- .../mailbox/mailbox.txt +- .../mailbox/nvidia,tegra186-hsp.txt + +Example bindings: +----------------- + +tcu: tcu { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; + mbox-names = "rx", "tx"; +}; -- cgit v1.2.3 From c051dc5e3cea482ceb019028ddde67b7cb921e85 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 28 Jan 2019 09:55:29 +0100 Subject: dt-bindings: arm: renesas: Fix SoC mismatch for Stout make dtbs_check: arch/arm/boot/dts/r8a7790-stout.dt.yaml: compatible: ['renesas,stout', 'renesas,r8a7790'] is not valid under any of the given schemas The Stout development board has an R-Car H2 (r8a7790) SoC, not an R-Car H1 (r8a7779). Fixes: 12749350567c819d ("dt-bindings: arm: Convert Renesas board/soc bindings to json-schema") Signed-off-by: Geert Uytterhoeven Reviewed-by: Rob Herring Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/renesas.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index cb9b4417e8a1..19f379863d50 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -130,13 +130,13 @@ properties: items: - enum: - renesas,marzen # Marzen (R0P7779A00010S) - - renesas,stout # Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) - const: renesas,r8a7779 - description: R-Car H2 (R8A77900) items: - enum: - renesas,lager # Lager (RTP0RC7790SEB00010S) + - renesas,stout # Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) - const: renesas,r8a7790 - description: R-Car M2-W (R8A77910) -- cgit v1.2.3 From a26ec8857da387303c6121a8aff7b7544a981690 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 29 Jan 2019 12:39:50 +0100 Subject: dt-bindings: rtc: Add RV1805 to abracon,abx80x bindings Add compatible string for Microcrystal RV1805 RTC, which is compatible with AB1805. The RV1805 uses smaller 10 pin package, while the AB1805 uses larger 16pin package, however the die inside the chip is the same. Signed-off-by: Marek Vasut Cc: Alexandre Belloni Cc: Rob Herring To: devicetree@vger.kernel.org Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/abracon,abx80x.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt b/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt index 18b892d010d8..2405e35a1bc0 100644 --- a/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt +++ b/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt @@ -16,6 +16,7 @@ Required properties: "abracon,ab1803" "abracon,ab1804" "abracon,ab1805" + "microcrystal,rv1805" Using "abracon,abx80x" will enable chip autodetection. - "reg": I2C bus address of the device -- cgit v1.2.3 From 9389b5e9467f71360d83310502de1ba0dc8960f1 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 30 Jan 2019 11:24:06 +1000 Subject: dt-bindings: net: dsa: add new MT7530 binding to support MT7621 Add devicetree binding to support the compatible mt7530 switch as used in the MediaTek MT7621 SoC. Signed-off-by: Greg Ungerer Reviewed-by: Andrew Lunn Reviewed-by: Florian Fainelli Acked-by: Sean Wang Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/dsa/mt7530.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt b/Documentation/devicetree/bindings/net/dsa/mt7530.txt index aa3527f71fdc..47aa205ee0bd 100644 --- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt +++ b/Documentation/devicetree/bindings/net/dsa/mt7530.txt @@ -3,12 +3,16 @@ Mediatek MT7530 Ethernet switch Required properties: -- compatible: Must be compatible = "mediatek,mt7530"; +- compatible: may be compatible = "mediatek,mt7530" + or compatible = "mediatek,mt7621" - #address-cells: Must be 1. - #size-cells: Must be 0. - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part on multi-chip module belong to MT7623A has or the remotely standalone chip as the function MT7623N reference board provided for. + +If compatible mediatek,mt7530 is set then the following properties are required + - core-supply: Phandle to the regulator node necessary for the core power. - io-supply: Phandle to the regulator node necessary for the I/O power. See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt -- cgit v1.2.3 From d8501cc85069f161466016a140e71ea88ee83376 Mon Sep 17 00:00:00 2001 From: Yunfei Dong Date: Thu, 17 Jan 2019 03:39:18 -0200 Subject: media: dt-bindings: media: add 'assigned-clocks' to vcodec examples Fix MTK binding document for MT8173 dtsi changed in order to use standard CCF interface. MT8173 SoC from Mediatek. Signed-off-by: Yunfei Dong Signed-off-by: Qianqian Yan Reviewed-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/mediatek-vcodec.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt index 2a615d84a682..b6b5dde6abd8 100644 --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt @@ -66,6 +66,15 @@ vcodec_dec: vcodec@16000000 { "vencpll", "venc_lt_sel", "vdec_bus_clk_src"; + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, + <&topckgen CLK_TOP_CCI400_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>, + <&apmixedsys CLK_APMIXED_VCODECPLL>, + <&apmixedsys CLK_APMIXED_VENCPLL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, + <&topckgen CLK_TOP_UNIVPLL_D2>, + <&topckgen CLK_TOP_VCODECPLL>; + assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; }; vcodec_enc: vcodec@18002000 { @@ -105,4 +114,8 @@ vcodec_dec: vcodec@16000000 { "venc_sel", "venc_lt_sel_src", "venc_lt_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, + <&topckgen CLK_TOP_VENC_LT_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, + <&topckgen CLK_TOP_UNIVPLL1_D2>; }; -- cgit v1.2.3 From 6216790dd45395b20032b5fac1bed4df64863690 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 28 Jan 2019 15:54:56 +0000 Subject: dt-bindings: nvmem: imx-ocotp: add compatible string for i.MX7ULP Add new compatible string for i.MX7ULP SOC. Signed-off-by: Anson Huang Reviewed-by: Rob Herring Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt index 792bc5fafeb9..ff389cf1606e 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt @@ -11,6 +11,7 @@ Required properties: "fsl,imx6ul-ocotp" (i.MX6UL), "fsl,imx7d-ocotp" (i.MX7D/S), "fsl,imx6sll-ocotp" (i.MX6SLL), + "fsl,imx7ulp-ocotp" (i.MX7ULP), followed by "syscon". - #address-cells : Should be 1 - #size-cells : Should be 1 -- cgit v1.2.3 From 4dbecb9f5b19723a59b15dfd57b1963e9d4bce73 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Mon, 28 Jan 2019 15:54:58 +0000 Subject: dt-bindings: imx-ocotp: Add i.MX6ULL/ULZ support Since the i.MX6ULL/ULZ only supports 8 OTP banks we need to introduce a new compatible. Signed-off-by: Stefan Wahren Reviewed-by: Rob Herring Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt index ff389cf1606e..7a999a135e56 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt @@ -1,7 +1,7 @@ Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings This binding represents the on-chip eFuse OTP controller found on -i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL and i.MX6SLL SoCs. +i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ and i.MX6SLL SoCs. Required properties: - compatible: should be one of @@ -9,6 +9,7 @@ Required properties: "fsl,imx6sl-ocotp" (i.MX6SL), or "fsl,imx6sx-ocotp" (i.MX6SX), "fsl,imx6ul-ocotp" (i.MX6UL), + "fsl,imx6ull-ocotp" (i.MX6ULL/ULZ), "fsl,imx7d-ocotp" (i.MX7D/S), "fsl,imx6sll-ocotp" (i.MX6SLL), "fsl,imx7ulp-ocotp" (i.MX7ULP), -- cgit v1.2.3 From 33d5c207a9ed16e72f49b77b9387aea5a8a42219 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Jan 2019 13:59:55 +0530 Subject: dt-bindings: PCI: dra7xx: Add SoC specific compatible strings Add new compatible strings for dra74x SoC (also used by dra76x) and dra72x. This can be used to perform SoC specific configuration (like configuring PCIe in x2 lane mode). Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori Signed-off-by: Lorenzo Pieralisi Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti-pci.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 452fe48c4fdd..e03d23631f5b 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -1,8 +1,12 @@ TI PCI Controllers PCIe DesignWare Controller - - compatible: Should be "ti,dra7-pcie" for RC - Should be "ti,dra7-pcie-ep" for EP + - compatible: Should be "ti,dra7-pcie" for RC (deprecated) + Should be "ti,dra7-pcie-ep" for EP (deprecated) + Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode + Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode + Should be "ti,dra726-pcie-rc" for dra72x in RC mode + Should be "ti,dra726-pcie-ep" for dra72x in EP mode - phys : list of PHY specifiers (used by generic PHY framework) - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the number of PHYs as specified in *phys* property. -- cgit v1.2.3 From 1c5d2cc7196c8c45c02114858efa4dca69a86583 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Jan 2019 13:59:56 +0530 Subject: dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 Add syscon properties required for configuring PCIe in x2 lane mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti-pci.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index e03d23631f5b..d5cbfe6b0d89 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -13,6 +13,9 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", where is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt + - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control + module and the register offset to specify lane + selection. HOST MODE ========= -- cgit v1.2.3 From a69ab6ad2ee07f98920a45d41cf51a3c2479b6e9 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 22 Jan 2019 09:51:43 +0530 Subject: dt-bindings: arm: fsl: Fix bindings for LS1012A and LS1021A based boards Fix devicetree bindings for Freescale LS1012A and LS1021A SoC based boards. Fixes: a1a38e1f4d1d ("dt-bindings: arm: Convert FSL board/soc bindings to json-schema") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 8a571c7dc11a..af973dc3ee89 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -176,12 +176,20 @@ properties: - fsl,vf610 - fsl,vf610m4 - - description: LS1021A based Boards + - description: LS1012A based Boards items: - enum: - fsl,ls1012a-rdb - fsl,ls1012a-frdm - fsl,ls1012a-qds + - const: fsl,ls1012a + + - description: LS1021A based Boards + items: + - enum: + - fsl,ls1021a-moxa-uc-8410a + - fsl,ls1021a-qds + - fsl,ls1021a-twr - const: fsl,ls1021a - description: LS1043A based Boards -- cgit v1.2.3 From 8cf0c53c307a03202fca34793c5a291d948e191c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 22 Jan 2019 09:51:45 +0530 Subject: dt-bindings: vendor-prefixes: Add EBS-SYSTART GmbH Vendor Prefix Add vendor prefix for EBS-SYSTART GmbH. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index a81de3134724..4b04ebbdabd0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -109,6 +109,7 @@ dongwoon Dongwoon Anatech dptechnics DPTechnics dragino Dragino Technology Co., Limited ea Embedded Artists AB +ebs-systart EBS-SYSTART GmbH ebv EBV Elektronik eckelmann Eckelmann AG edt Emerging Display Technologies -- cgit v1.2.3 From ce1bcf148a127e712671584cfe634a87eebc0cdd Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 22 Jan 2019 09:51:46 +0530 Subject: dt-bindings: arm: fsl: Add devicetree binding for Oxalis Add devicetree binding for LS1012A SoC based Oxalis board. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index af973dc3ee89..7e2cd6ad26bd 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -179,6 +179,7 @@ properties: - description: LS1012A based Boards items: - enum: + - ebs-systart,oxalis - fsl,ls1012a-rdb - fsl,ls1012a-frdm - fsl,ls1012a-qds -- cgit v1.2.3 From 95f2aac6223aed0f81b208c10fad19ee32762b4c Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Thu, 24 Jan 2019 13:22:32 +0000 Subject: dt-bindings: fsl: scu: add fallback compatible string for clock SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs. Let's add a "fsl,scu-clk" fallback compatible string to allow other SoCs to reuse the common part. Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Michael Turquette Acked-by: Stephen Boyd Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 27784b6edfed..5ec6dcafa7c9 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -70,7 +70,9 @@ Clock bindings based on SCU Message Protocol This binding uses the common clock binding[1]. Required properties: -- compatible: Should be "fsl,imx8qxp-clock". +- compatible: Should be one of: + "fsl,imx8qxp-clock" + followed by "fsl,scu-clk" - #clock-cells: Should be 1. Contains the Clock ID value. - clocks: List of clock specifiers, must contain an entry for each required entry in clock-names @@ -137,7 +139,7 @@ firmware { &lsio_mu1 1 3>; clk: clk { - compatible = "fsl,imx8qxp-clk"; + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; #clock-cells = <1>; }; -- cgit v1.2.3 From 2a005397117019cbd4e4a09ab5cf896a16b652c5 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Thu, 24 Jan 2019 13:22:36 +0000 Subject: dt-bindings: fsl: scu: add imx8qm scu clock support Add imx8qm scu clock support Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Michael Turquette Acked-by: Stephen Boyd Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 5ec6dcafa7c9..cef5ee83fbc1 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -71,6 +71,7 @@ This binding uses the common clock binding[1]. Required properties: - compatible: Should be one of: + "fsl,imx8qm-clock" "fsl,imx8qxp-clock" followed by "fsl,scu-clk" - #clock-cells: Should be 1. Contains the Clock ID value. -- cgit v1.2.3 From b9e176e0f9c949ccb30fc28d4fc29c92207354cf Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 28 Dec 2018 23:09:25 +0100 Subject: dt-bindings: bcm: Add Raspberry Pi 3 A+ This adds the root properties for the Raspberry Pi 3 A+ . Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt index 0dcc3ea5adff..245328f36580 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt @@ -30,6 +30,10 @@ Raspberry Pi 2 Model B Required root node properties: compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; +Raspberry Pi 3 Model A+ +Required root node properties: +compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837"; + Raspberry Pi 3 Model B Required root node properties: compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; -- cgit v1.2.3 From 5af01ab3b6d7e0279bb6b90b54ecd921afc83bb2 Mon Sep 17 00:00:00 2001 From: Kamil Konieczny Date: Tue, 22 Jan 2019 10:02:30 +0100 Subject: clk: samsung: dt-bindings: Document Exynos5433 IMEM CMU Document DT bindings of the IMEM CMU providing clocks for the Exynos5433 Security SubSystem (SSS) and SlimSSS IPs. Acked-by: Chanwoo Choi Reviewed-by: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Kamil Konieczny [s.nawrocki@samsung.com: edited commit description] Signed-off-by: Sylwester Nawrocki --- .../devicetree/bindings/clock/exynos5433-clock.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt index 50d5897c9849..183c327a7d6b 100644 --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt @@ -50,6 +50,8 @@ Required Properties: IPs. - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1 which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs. + - "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM + which generates clocks for SSS (Security SubSystem) and SlimSSS IPs. - reg: physical base address of the controller and length of memory mapped region. @@ -168,6 +170,12 @@ Required Properties: - aclk_cam1_400 - aclk_cam1_552 + Input clocks for imem clock controller: + - oscclk + - aclk_imem_sssx_266 + - aclk_imem_266 + - aclk_imem_200 + Optional properties: - power-domains: a phandle to respective power domain node as described by generic PM domain bindings (see power/power_domain.txt for more @@ -469,6 +477,21 @@ Example 2: Examples of clock controller nodes are listed below. power-domains = <&pd_cam1>; }; + cmu_imem: clock-controller@11060000 { + compatible = "samsung,exynos5433-cmu-imem"; + reg = <0x11060000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_imem_sssx_266", + "aclk_imem_266", + "aclk_imem_200"; + clocks = <&xxti>, + <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, + <&cmu_top CLK_DIV_ACLK_IMEM_266>, + <&cmu_top CLK_DIV_ACLK_IMEM_200>; + }; + Example 3: UART controller node that consumes the clock generated by the clock controller. -- cgit v1.2.3 From 4e2256d31f0f24107c36dae35a1d84dff0fced30 Mon Sep 17 00:00:00 2001 From: Craig Tatlor Date: Sat, 11 Aug 2018 17:24:17 +0100 Subject: soc: qcom: smd-rpm: Add sdm660 compatible Add the compatible for the RPM in SDM660, so that rpm resources can be made available. Signed-off-by: Craig Tatlor Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt index ec95705ba692..f3fa313963d5 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt @@ -23,6 +23,7 @@ resources. "qcom,rpm-msm8916" "qcom,rpm-msm8974" "qcom,rpm-msm8998" + "qcom,rpm-sdm660" "qcom,rpm-qcs404" - qcom,smd-channels: -- cgit v1.2.3 From 349c2deafed788826ff1a67e2c7daeb7fcebd051 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Sat, 19 Jan 2019 21:47:53 +0100 Subject: dt-bindings: iio: pressure: add LPS22HH bindings Fix following checkpatch warnings: WARNING: DT compatible string "st,lps22hh" appears un-documented -- check ./Documentation/devicetree/bindings/ .compatible = "st,lps22hh", WARNING: DT compatible string "st,lps22hh" appears un-documented -- check ./Documentation/devicetree/bindings/ .compatible = "st,lps22hh", Fixes: e5aab7b0d88d ("iio:st_pressure:initial lps22hh sensor support") Signed-off-by: Lorenzo Bianconi Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/st-sensors.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt index ddcb95509599..52ee4baec6f0 100644 --- a/Documentation/devicetree/bindings/iio/st-sensors.txt +++ b/Documentation/devicetree/bindings/iio/st-sensors.txt @@ -77,3 +77,4 @@ Pressure sensors: - st,lps22hb-press - st,lps33hw - st,lps35hw +- st,lps22hh -- cgit v1.2.3 From d9f5c4e2374deefb2d3c07727a47c37727b8cbc1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Randolph=20Maa=C3=9Fen?= Date: Mon, 28 Jan 2019 19:50:02 +0100 Subject: dt-bindings: iio: imu: add icm20602 bindings to mpu6050 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adding the invensense ICM-20602 to the compatible list of the mpu6050 driver Signed-off-by: Randolph Maaßen Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt b/Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt index 6ab9a9d196b0..268bf7568e19 100644 --- a/Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt +++ b/Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt @@ -11,6 +11,7 @@ Required properties: "invensense,mpu9250" "invensense,mpu9255" "invensense,icm20608" + "invensense,icm20602" - reg : the I2C address of the sensor - interrupts: interrupt mapping for IRQ. It should be configured with flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or -- cgit v1.2.3 From b64d97300888a51b0c122e96457faa7059b6987b Mon Sep 17 00:00:00 2001 From: Stefan Popa Date: Thu, 31 Jan 2019 18:21:42 +0200 Subject: dt-bindings: iio: adc: Add docs for AD7768-1 Document support for AD7768-1 Analog to Digital Converter. Signed-off-by: Stefan Popa Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/adi,ad7768-1.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.txt b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.txt new file mode 100644 index 000000000000..9f5b88cf680d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.txt @@ -0,0 +1,41 @@ +Analog Devices AD7768-1 ADC device driver + +Required properties for the AD7768-1: + +- compatible: Must be "adi,ad7768-1" +- reg: SPI chip select number for the device +- spi-max-frequency: Max SPI frequency to use + see: Documentation/devicetree/bindings/spi/spi-bus.txt +- clocks: phandle to the master clock (mclk) + see: Documentation/devicetree/bindings/clock/clock-bindings.txt +- clock-names: Must be "mclk". +- interrupts: IRQ line for the ADC + see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt +- vref-supply: vref supply can be used as reference for conversion +- adi,sync-in-gpios: must be the device tree identifier of the SYNC-IN pin. Enables + synchronization of multiple devices that require simultaneous sampling. + A pulse is always required if the configuration is changed in any way, for example + if the filter decimation rate changes. As the line is active low, it should + be marked GPIO_ACTIVE_LOW. + +Optional properties: + + - reset-gpios : GPIO spec for the RESET pin. If specified, it will be asserted during + driver probe. As the line is active low, it should be marked GPIO_ACTIVE_LOW. + +Example: + + adc@0 { + compatible = "adi,ad7768-1"; + reg = <0>; + spi-max-frequency = <2000000>; + spi-cpol; + spi-cpha; + vref-supply = <&adc_vref>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpio>; + adi,sync-in-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>; + clocks = <&ad7768_mclk>; + clock-names = "mclk"; + }; -- cgit v1.2.3 From 59600d045ff411da193a8b5a2999681801ecd430 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 26 Oct 2018 09:55:53 +0100 Subject: dt-bindings: watchdog: renesas-wdt: Document r8a77470 support RZ/G1C (R8A77470) watchdog implementation is compatible with R-Car Gen2, therefore add relevant documentation. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/devicetree/bindings/watchdog/renesas-wdt.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt index ef2b97b72e08..9f365c1a3399 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt @@ -8,6 +8,7 @@ Required properties: - "renesas,r8a7743-wdt" (RZ/G1M) - "renesas,r8a7744-wdt" (RZ/G1N) - "renesas,r8a7745-wdt" (RZ/G1E) + - "renesas,r8a77470-wdt" (RZ/G1C) - "renesas,r8a774a1-wdt" (RZ/G2M) - "renesas,r8a774c0-wdt" (RZ/G2E) - "renesas,r8a7790-wdt" (R-Car H2) -- cgit v1.2.3 From 425da20a98e0ab6ba6b37ff00ab50519d7dd7740 Mon Sep 17 00:00:00 2001 From: KaiChieh Chuang Date: Wed, 30 Jan 2019 14:47:11 +0800 Subject: ASoC: mediatek: add documents for btcvsd driver document for btcvsd driver Signed-off-by: KaiChieh Chuang Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/mtk-btcvsd-snd.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mtk-btcvsd-snd.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/mtk-btcvsd-snd.txt b/Documentation/devicetree/bindings/sound/mtk-btcvsd-snd.txt new file mode 100644 index 000000000000..679e44839b48 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mtk-btcvsd-snd.txt @@ -0,0 +1,24 @@ +Mediatek ALSA BT SCO CVSD/MSBC Driver + +Required properties: +- compatible = "mediatek,mtk-btcvsd-snd"; +- reg: register location and size of PKV and SRAM_BANK2 +- interrupts: should contain BTSCO interrupt +- mediatek,infracfg: the phandles of INFRASYS +- mediatek,offset: Array contains of register offset and mask + infra_misc_offset, + infra_conn_bt_cvsd_mask, + cvsd_mcu_read_offset, + cvsd_mcu_write_offset, + cvsd_packet_indicator_offset + +Example: + + mtk-btcvsd-snd@18000000 { + compatible = "mediatek,mtk-btcvsd-snd"; + reg=<0 0x18000000 0 0x1000>, + <0 0x18080000 0 0x8000>; + interrupts = ; + mediatek,infracfg = <&infrasys>; + mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>; + }; -- cgit v1.2.3 From 1e65b2f1f66358676a07c6352a1ff323f7c9fa5a Mon Sep 17 00:00:00 2001 From: Robert Eshleman Date: Thu, 31 Jan 2019 07:49:16 -0800 Subject: dt-bindings: iio: light: Add max44009 Adds device tree bindings for the max44009 light sensor. Signed-off-by: Robert Eshleman Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/light/max44009.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/light/max44009.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/light/max44009.txt b/Documentation/devicetree/bindings/iio/light/max44009.txt new file mode 100644 index 000000000000..4a98848e35c0 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/light/max44009.txt @@ -0,0 +1,24 @@ +* MAX44009 Ambient Light Sensor + +Required properties: + +- compatible: should be "maxim,max44009" +- reg: the I2C address of the device (default is <0x4a>) + +Optional properties: + +- interrupts: interrupt mapping for GPIO IRQ. Should be configured with + IRQ_TYPE_EDGE_FALLING. + +Refer to interrupt-controller/interrupts.txt for generic interrupt client +node bindings. + +Example: + +light-sensor@4a { + compatible = "maxim,max44009"; + reg = <0x4a>; + + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; +}; -- cgit v1.2.3 From 0bb16830ebb6220f35ee9fc2c60be0958fc5be6f Mon Sep 17 00:00:00 2001 From: Alex Williams Date: Thu, 31 Jan 2019 13:33:28 -0800 Subject: net: nixge: Update device-tree bindings with v3.00 Now the DMA engine is free to float elsewhere in the system map. Signed-off-by: Alex Williams Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/nixge.txt | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/nixge.txt b/Documentation/devicetree/bindings/net/nixge.txt index e55af7f0881a..44a7358b4399 100644 --- a/Documentation/devicetree/bindings/net/nixge.txt +++ b/Documentation/devicetree/bindings/net/nixge.txt @@ -1,8 +1,14 @@ * NI XGE Ethernet controller Required properties: -- compatible: Should be "ni,xge-enet-2.00" -- reg: Address and length of the register set for the device +- compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for + older device trees with DMA engines co-located in the address map, + with the one reg entry to describe the whole device. +- reg: Address and length of the register set for the device. It contains the + information of registers in the same order as described by reg-names. +- reg-names: Should contain the reg names + "dma": DMA engine control and status region + "ctrl": MDIO and PHY control and status region - interrupts: Should contain tx and rx interrupt - interrupt-names: Should be "rx" and "tx" - phy-mode: See ethernet.txt file in the same directory. @@ -12,8 +18,10 @@ Required properties: Examples (10G generic PHY): nixge0: ethernet@40000000 { - compatible = "ni,xge-enet-2.00"; - reg = <0x40000000 0x6000>; + compatible = "ni,xge-enet-3.00"; + reg = <0x40000000 0x4000 + 0x41002000 0x2000>; + reg-names = "dma", "ctrl"; nvmem-cells = <ð1_addr>; nvmem-cell-names = "address"; -- cgit v1.2.3 From 24332d0d06a25d9fe4e7fd0275b9586cc65aea68 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 13 Nov 2018 13:42:05 +0100 Subject: dt-bindings: display: add binding for Innolux ee101ia-01d panel This is a panel handled through the generic lvds-panel binding, so only needs its additional compatible specified. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring Link: https://patchwork.freedesktop.org/patch/msgid/20181113124205.29319-1-heiko@sntech.de --- .../devicetree/bindings/display/panel/innolux,ee101ia-01d.txt | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt b/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt new file mode 100644 index 000000000000..e5ca4ccd55ed --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt @@ -0,0 +1,7 @@ +Innolux Corporation 10.1" EE101IA-01D WXGA (1280x800) LVDS panel + +Required properties: +- compatible: should be "innolux,ee101ia-01d" + +This binding is compatible with the lvds-panel binding, which is specified +in panel-lvds.txt in this directory. -- cgit v1.2.3 From 25db146aa7262bc95c314b2df35db107f5eadd55 Mon Sep 17 00:00:00 2001 From: Jian Hu Date: Fri, 1 Feb 2019 15:53:43 +0100 Subject: dt-bindings: clk: meson: add g12a periph clock controller bindings Add new clock controller compatible and dt-bindings header for the Everything-Else domain of the g12a SoC Reviewed-by: Rob Herring Signed-off-by: Jian Hu Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190201145345.6795-3-jbrunet@baylibre.com --- Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index a6871953bf04..5c8b105be4d6 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,7 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. + "amlogic,g12a-clkc" for G12A SoC. - clocks : list of clock phandle, one for each entry clock-names. - clock-names : should contain the following: * "xtal": the platform xtal -- cgit v1.2.3 From 50fdb52a7cda63828441cc1e7c05f1d0b77e833a Mon Sep 17 00:00:00 2001 From: Youlin Wang Date: Thu, 24 Jan 2019 12:24:16 -0800 Subject: Documentation: bindings: k3dma: Extend the k3dma driver binding to support hisi-asp Extend the k3dma driver binding to support hisi-asp hardware variants. Cc: Vinod Koul Cc: Rob Herring Cc: Mark Rutland Cc: Zhuangluan Su Cc: Tanglei Han Cc: Ryan Grachek Cc: Manivannan Sadhasivam Cc: dmaengine@vger.kernel.org Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Youlin Wang Signed-off-by: Tanglei Han Signed-off-by: John Stultz Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/k3dma.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/k3dma.txt b/Documentation/devicetree/bindings/dma/k3dma.txt index 4945aeac4dc4..10a2f15b08a3 100644 --- a/Documentation/devicetree/bindings/dma/k3dma.txt +++ b/Documentation/devicetree/bindings/dma/k3dma.txt @@ -3,7 +3,9 @@ See dma.txt first Required properties: -- compatible: Should be "hisilicon,k3-dma-1.0" +- compatible: Must be one of +- "hisilicon,k3-dma-1.0" +- "hisilicon,hisi-pcm-asp-dma-1.0" - reg: Should contain DMA registers location and length. - interrupts: Should contain one interrupt shared by all channel - #dma-cells: see dma.txt, should be 1, para number -- cgit v1.2.3 From e2d896c08ca3136f1f4c0cd225cdf09f87fa528b Mon Sep 17 00:00:00 2001 From: John Stultz Date: Thu, 24 Jan 2019 12:24:17 -0800 Subject: Documentation: bindings: dma: Add binding for dma-channel-mask Some dma channels can be reserved for secure mode or other hardware on the SoC, so provide a binding for a bitmask listing the available channels for the kernel to use. This follows the pre-existing bcm,dma-channel-mask binding. Cc: Vinod Koul Cc: Rob Herring Cc: Mark Rutland Cc: Tanglei Han Cc: Zhuangluan Su Cc: Ryan Grachek Cc: Manivannan Sadhasivam Cc: dmaengine@vger.kernel.org Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: John Stultz Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/dma.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/dma.txt b/Documentation/devicetree/bindings/dma/dma.txt index 6312fb00ce8d..eeb4e4d1771e 100644 --- a/Documentation/devicetree/bindings/dma/dma.txt +++ b/Documentation/devicetree/bindings/dma/dma.txt @@ -16,6 +16,9 @@ Optional properties: - dma-channels: Number of DMA channels supported by the controller. - dma-requests: Number of DMA request signals supported by the controller. +- dma-channel-mask: Bitmask of available DMA channels in ascending order + that are not reserved by firmware and are available to + the kernel. i.e. first channel corresponds to LSB. Example: @@ -29,6 +32,7 @@ Example: #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + dma-channel-mask = <0xfffe> }; * DMA router -- cgit v1.2.3 From 2d8ed461dbc9bc734185db92d2b9d1bb7b586b30 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Fri, 1 Feb 2019 16:15:23 -0800 Subject: PCI: imx6: Add support for i.MX8MQ Add code needed to support i.MX8MQ variant. Signed-off-by: Andrey Smirnov Signed-off-by: Lorenzo Pieralisi Reviewed-by: Lucas Stach Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index d514c1f2365f..920ca93870a8 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -9,6 +9,7 @@ Required properties: - "fsl,imx6sx-pcie", - "fsl,imx6qp-pcie" - "fsl,imx7d-pcie" + - "fsl,imx8mq-pcie" - reg: base address and length of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. @@ -45,7 +46,7 @@ Additional required properties for imx6sx-pcie: PCIE_PHY power domains - power-domain-names: Must be "pcie", "pcie_phy" -Additional required properties for imx7d-pcie: +Additional required properties for imx7d-pcie and imx8mq-pcie: - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain - resets: Must contain phandles to PCIe-related reset lines exposed by SRC IP block -- cgit v1.2.3 From 940c2361b56ac82a555ce88d77bf18e80a8f31d0 Mon Sep 17 00:00:00 2001 From: Nava kishore Manne Date: Wed, 6 Feb 2019 16:37:20 +0530 Subject: dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver Add documentation to describe Xilinx ZynqMP nvmem driver bindings. Signed-off-by: Nava kishore Manne Reviewed-by: Rob Herring Acked-by: Srinivas Kandagatla Signed-off-by: Michal Simek --- .../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt new file mode 100644 index 000000000000..4881561b3a02 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt @@ -0,0 +1,46 @@ +-------------------------------------------------------------------------- += Zynq UltraScale+ MPSoC nvmem firmware driver binding = +-------------------------------------------------------------------------- +The nvmem_firmware node provides access to the hardware related data +like soc revision, IDCODE... etc, By using the firmware interface. + +Required properties: +- compatible: should be "xlnx,zynqmp-nvmem-fw" + += Data cells = +Are child nodes of silicon id, bindings of which as described in +bindings/nvmem/nvmem.txt + +------- + Example +------- +firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + + nvmem_firmware { + compatible = "xlnx,zynqmp-nvmem-fw"; + #address-cells = <1>; + #size-cells = <1>; + + /* Data cells */ + soc_revision: soc_revision { + reg = <0x0 0x4>; + }; + }; + }; +}; + += Data consumers = +Are device nodes which consume nvmem data cells. + +For example: + pcap { + ... + + nvmem-cells = <&soc_revision>; + nvmem-cell-names = "soc_revision"; + + ... + }; -- cgit v1.2.3 From 9f21ef41a5c55c8d6f3c2f8a8773126f698f2a7d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 28 Jan 2019 23:25:33 +0100 Subject: i2c: Add DT bindings for Xscale I2C masters This adds a device tree binding for Intel XScale I2C masters. We define compatible strings for the iop3xx and ixp4xx chip families. Signed-off-by: Linus Walleij Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-xscale.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-xscale.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-xscale.txt b/Documentation/devicetree/bindings/i2c/i2c-xscale.txt new file mode 100644 index 000000000000..dcc8390e0d24 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-xscale.txt @@ -0,0 +1,20 @@ +i2c Controller on XScale platforms such as IOP3xx and IXP4xx + +Required properties: +- compatible : Must be one of + "intel,iop3xx-i2c" + "intel,ixp4xx-i2c"; +- reg +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties: +- Child nodes conforming to i2c bus binding + +Example: + +i2c@c8011000 { + compatible = "intel,ixp4xx-i2c"; + reg = <0xc8011000 0x18>; + interrupts = <33 IRQ_TYPE_LEVEL_LOW>; +}; -- cgit v1.2.3 From 70ae5669b5b3f357a5c1d64152508506624a5c5d Mon Sep 17 00:00:00 2001 From: qii wang Date: Mon, 21 Jan 2019 15:59:29 +0800 Subject: dt-bindings: i2c: Add Mediatek MT7629 i2c binding Add MT7629 i2c binding to binding file. Signed-off-by: qii wang Reviewed-by: Rob Herring Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt index e199695b1c96..ee4c32454198 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt @@ -10,6 +10,7 @@ Required properties: "mediatek,mt6589-i2c": for MediaTek MT6589 "mediatek,mt7622-i2c": for MediaTek MT7622 "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623 + "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629 "mediatek,mt8173-i2c": for MediaTek MT8173 - reg: physical base address of the controller and dma base, length of memory mapped region. -- cgit v1.2.3 From 3059ba75ca8badc828d1ab2a60c0160fe5753e18 Mon Sep 17 00:00:00 2001 From: Liang Yang Date: Tue, 15 Jan 2019 23:38:03 +0800 Subject: dt-bindings: nand: meson: add Amlogic NAND controller driver Add Amlogic NAND controller dt-bindings for Meson SoC, Current this driver support GXBB/GXL/AXG platform. Signed-off-by: Liang Yang Signed-off-by: Yixun Lan Signed-off-by: Jianxin Pan Reviewed-by: Rob Herring Signed-off-by: Miquel Raynal --- .../devicetree/bindings/mtd/amlogic,meson-nand.txt | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt new file mode 100644 index 000000000000..3983c11e062c --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt @@ -0,0 +1,60 @@ +Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs + +This file documents the properties in addition to those available in +the MTD NAND bindings. + +Required properties: +- compatible : contains one of: + - "amlogic,meson-gxl-nfc" + - "amlogic,meson-axg-nfc" +- clocks : + A list of phandle + clock-specifier pairs for the clocks listed + in clock-names. + +- clock-names: Should contain the following: + "core" - NFC module gate clock + "device" - device clock from eMMC sub clock controller + "rx" - rx clock phase + "tx" - tx clock phase + +- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC + controller port C + +Optional children nodes: +Children nodes represent the available nand chips. + +Other properties: +see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. + +Example demonstrate on AXG SoC: + + sd_emmc_c_clkc: mmc@7000 { + compatible = "amlogic,meson-axg-mmc-clkc", "syscon"; + reg = <0x0 0x7000 0x0 0x800>; + }; + + nand-controller@7800 { + compatible = "amlogic,meson-axg-nfc"; + reg = <0x0 0x7800 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + + clocks = <&clkc CLKID_SD_EMMC_C>, + <&sd_emmc_c_clkc CLKID_MMC_DIV>, + <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>, + <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>; + clock-names = "core", "device", "rx", "tx"; + amlogic,mmc-syscon = <&sd_emmc_c_clkc>; + + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-on-flash-bbt; + }; + }; -- cgit v1.2.3 From 2e2b7615e310994b4d59c98b7d114449a9f019e5 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Tue, 18 Dec 2018 12:02:42 +0000 Subject: dt-bindings: PCI: rcar: Add device tree support for r8a774c0 Add PCIe support for the RZ/G2E (a.k.a. R8A774C0). Signed-off-by: Fabrizio Castro Signed-off-by: Lorenzo Pieralisi Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Reviewed-by: Simon Horman --- Documentation/devicetree/bindings/pci/rcar-pci.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt index 976ef7bfff93..6904882a0e94 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt @@ -3,6 +3,7 @@ Required properties: compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; "renesas,pcie-r8a7744" for the R8A7744 SoC; + "renesas,pcie-r8a774c0" for the R8A774C0 SoC; "renesas,pcie-r8a7779" for the R8A7779 SoC; "renesas,pcie-r8a7790" for the R8A7790 SoC; "renesas,pcie-r8a7791" for the R8A7791 SoC; @@ -13,7 +14,8 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; "renesas,pcie-r8a77990" for the R8A77990 SoC; "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or RZ/G1 compatible device. - "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device. + "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 or + RZ/G2 compatible device. When compatible with the generic version, nodes must list the SoC-specific version corresponding to the platform first -- cgit v1.2.3 From dd648818dad3ad5ab5151c7f5ca0bb55a0bf71de Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Mon, 4 Feb 2019 09:30:38 -0800 Subject: net: nixge: Make mdio child node optional Make MDIO child optional and only instantiate the MDIO bus if the child is actually present. There are currently no (in-tree) users of this binding; all (out-of-tree) users use overlays that get shipped together with the FPGA images that contain the IP. This will significantly increase maintainabilty of future revisions of this IP. Reviewed-by: Andrew Lunn Signed-off-by: Moritz Fischer Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/nixge.txt | 27 ++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/nixge.txt b/Documentation/devicetree/bindings/net/nixge.txt index 44a7358b4399..bb2929f9c64f 100644 --- a/Documentation/devicetree/bindings/net/nixge.txt +++ b/Documentation/devicetree/bindings/net/nixge.txt @@ -16,6 +16,9 @@ Required properties: - nvmem-cells: Phandle of nvmem cell containing the MAC address - nvmem-cell-names: Should be "address" +Optional properties: +- mdio subnode to indicate presence of MDIO controller + Examples (10G generic PHY): nixge0: ethernet@40000000 { compatible = "ni,xge-enet-3.00"; @@ -33,8 +36,26 @@ Examples (10G generic PHY): phy-mode = "xgmii"; phy-handle = <ðernet_phy1>; - ethernet_phy1: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <4>; + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; }; }; + +Examples (10G generic PHY, no MDIO): + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + }; -- cgit v1.2.3 From baaac2fb0dda4ce2204e6650138cd578c4b11236 Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Mon, 4 Feb 2019 09:30:40 -0800 Subject: dt-bindings: net: Add fixed-link support Update device-tree binding with fixed-link support. With fixed-link support the formerly required property 'phy-handle' is now optional if 'fixed-link' child is present. Signed-off-by: Moritz Fischer Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/nixge.txt | 33 ++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/nixge.txt b/Documentation/devicetree/bindings/net/nixge.txt index bb2929f9c64f..85d7240a9b20 100644 --- a/Documentation/devicetree/bindings/net/nixge.txt +++ b/Documentation/devicetree/bindings/net/nixge.txt @@ -12,12 +12,14 @@ Required properties: - interrupts: Should contain tx and rx interrupt - interrupt-names: Should be "rx" and "tx" - phy-mode: See ethernet.txt file in the same directory. -- phy-handle: See ethernet.txt file in the same directory. - nvmem-cells: Phandle of nvmem cell containing the MAC address - nvmem-cell-names: Should be "address" Optional properties: - mdio subnode to indicate presence of MDIO controller +- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory. + Use instead of phy-handle. +- phy-handle: See ethernet.txt file in the same directory. Examples (10G generic PHY): nixge0: ethernet@40000000 { @@ -59,3 +61,32 @@ Examples (10G generic PHY, no MDIO): phy-mode = "xgmii"; phy-handle = <ðernet_phy1>; }; + +Examples (1G generic fixed-link + MDIO): + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + pause; + link-gpios = <&gpio0 63 GPIO_ACTIVE_HIGH>; + }; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; + + }; -- cgit v1.2.3 From b8bdf0925902b07e45d4d9c8796f7c531cfe9320 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 3 Jan 2019 14:25:32 +0530 Subject: dt-bindings: thermal: Add binding document for SR thermal Add binding document for supported thermal implementation in Stingray. Reviewed-by: Ray Jui Reviewed-by: Scott Branden Reviewed-by: Rob Herring Signed-off-by: Pramod Kumar Signed-off-by: Srinath Mannam Signed-off-by: Eduardo Valentin --- .../bindings/thermal/brcm,sr-thermal.txt | 105 +++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/brcm,sr-thermal.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/brcm,sr-thermal.txt b/Documentation/devicetree/bindings/thermal/brcm,sr-thermal.txt new file mode 100644 index 000000000000..3ab330219d45 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/brcm,sr-thermal.txt @@ -0,0 +1,105 @@ +* Broadcom Stingray Thermal + +This binding describes thermal sensors that is part of Stingray SoCs. + +Required properties: +- compatible : Must be "brcm,sr-thermal" +- reg : Memory where tmon data will be available. +- brcm,tmon-mask: A one cell bit mask of valid TMON sources. + Each bit represents single TMON source. +- #thermal-sensor-cells : Thermal sensor phandler +- polling-delay: Max number of milliseconds to wait between polls. +- thermal-sensors: A list of thermal sensor phandles and specifier. + specifier value is tmon ID and it should be + in correspond with brcm,tmon-mask. +- temperature: trip temperature threshold in millicelsius. + +Example: + tmons { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x8f100000 0x100>; + + tmon: tmon@0 { + compatible = "brcm,sr-thermal"; + reg = <0x0 0x40>; + brcm,tmon-mask = <0x3f>; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + ihost0_thermal: ihost0-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 0>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost1_thermal: ihost1-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 1>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost2_thermal: ihost2-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 2>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost3_thermal: ihost3-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 3>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + crmu_thermal: crmu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 4>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + nitro_thermal: nitro-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 5>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; -- cgit v1.2.3 From c0d7c861bd5792bef9de7192359b05099611bb27 Mon Sep 17 00:00:00 2001 From: Michael Kao Date: Fri, 1 Feb 2019 15:38:12 +0800 Subject: dt-bindings: thermal: add binding document for mt8183 thermal controller This patch adds binding document for mt8183 thermal controller. Signed-off-by: Michael Kao Signed-off-by: Eduardo Valentin --- Documentation/devicetree/bindings/thermal/mediatek-thermal.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt index 41d6a443ad66..f8d7831f3974 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt @@ -13,6 +13,7 @@ Required properties: - "mediatek,mt2701-thermal" : For MT2701 family of SoCs - "mediatek,mt2712-thermal" : For MT2712 family of SoCs - "mediatek,mt7622-thermal" : For MT7622 SoC + - "mediatek,mt8183-thermal" : For MT8183 family of SoCs - reg: Address range of the thermal controller - interrupts: IRQ for the thermal controller - clocks, clock-names: Clocks needed for the thermal controller. required -- cgit v1.2.3 From 93caec0042659bf17ec217b09857bd5eaeca6804 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Fri, 4 Jan 2019 11:06:43 +0800 Subject: dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Add new properties to configure the DFLL PWM regulator support. Cc: devicetree@vger.kernel.org Signed-off-by: Peter De Schrijver Signed-off-by: Joseph Lo Acked-by: Jon Hunter Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/clock/nvidia,tegra124-dfll.txt | 79 +++++++++++++++++++++- 1 file changed, 77 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index dff236f524a7..5558bb5fcf2c 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -8,7 +8,6 @@ the fast CPU cluster. It consists of a free-running voltage controlled oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop control module that will automatically adjust the VDD_CPU voltage by communicating with an off-chip PMIC either via an I2C bus or via PWM signals. -Currently only the I2C mode is supported by these bindings. Required properties: - compatible : should be "nvidia,tegra124-dfll" @@ -45,10 +44,31 @@ Required properties for the control loop parameters: Optional properties for the control loop parameters: - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM. +Optional properties for mode selection: +- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C. + Required properties for I2C mode: - nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode. -Example: +Required properties for PWM mode: +- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds. +- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM + control is disabled and the PWM output is tristated. Note that this voltage is + configured in hardware, typically via a resistor divider. +- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control + is enabled and PWM output is low. Hence, this is the minimum output voltage + that the regulator supports when PWM control is enabled. +- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts + corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th + duty cycle would be: nvidia,pwm-min-microvolts + + nvidia,pwm-voltage-step-microvolts * 2. +- pinctrl-0: I/O pad configuration when PWM control is enabled. +- pinctrl-1: I/O pad configuration when PWM control is disabled. +- pinctrl-names: must include the following entries: + - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled. + - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled. + +Example for I2C: clock@70110000 { compatible = "nvidia,tegra124-dfll"; @@ -76,3 +96,58 @@ clock@70110000 { nvidia,i2c-fs-rate = <400000>; }; + +Example for PWM: + +clock@70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, + <&tegra_car TEGRA210_CLK_DFLL_REF>, + <&tegra_car TEGRA124_CLK_I2C5>;; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + + nvidia,sample-rate = <25000>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + + nvidia,pwm-min-microvolts = <708000>; /* 708mV */ + nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ + nvidia,pwm-to-pmic; + nvidia,pwm-tristate-microvolts = <1000000>; + nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */ + + pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; + pinctrl-0 = <&dvfs_pwm_active_state>; + pinctrl-1 = <&dvfs_pwm_inactive_state>; +}; + +/* pinmux nodes added for completeness. Binding doc can be found in: + * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt + */ + +pinmux: pinmux@700008d4 { + dvfs_pwm_active_state: dvfs_pwm_active { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; + dvfs_pwm_inactive_state: dvfs_pwm_inactive { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; +}; -- cgit v1.2.3 From 7e9d10985856dcbcc8f56f97cb103eb3349b3f12 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 11:06:44 +0800 Subject: dt-bindings: clock: tegra124-dfll: add Tegra210 support Add Tegra210 support for DFLL clock. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter Acked-by: Stephen Boyd Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index 5558bb5fcf2c..958e0ad78c52 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -10,7 +10,9 @@ control module that will automatically adjust the VDD_CPU voltage by communicating with an off-chip PMIC either via an I2C bus or via PWM signals. Required properties: -- compatible : should be "nvidia,tegra124-dfll" +- compatible : should be one of: + - "nvidia,tegra124-dfll": for Tegra124 + - "nvidia,tegra210-dfll": for Tegra210 - reg : Defines the following set of registers, in the order listed: - registers for the DFLL control logic. - registers for the I2C output logic. -- cgit v1.2.3 From 73688f7d535bc3f5b0af2e3fd082a60daa2171be Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 11:06:45 +0800 Subject: dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties The Tegra124 cpufreq driver works only with DFLL clock, which is a hardware-based frequency/voltage controller. The driver doesn't need to control the regulator itself. Hence remove that. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt index b1669fbfb740..031545a29caf 100644 --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt @@ -13,7 +13,6 @@ Required properties: - pll_x: Fast PLL clocksource. - pll_p: Auxiliary PLL used during fast PLL rate changes. - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. -- vdd-cpu-supply: Regulator for CPU voltage Optional properties: - clock-latency: Specify the possible maximum transition latency for clock, @@ -37,7 +36,6 @@ cpus { <&dfll>; clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; - vdd-cpu-supply: <&vdd_cpu>; }; <...> -- cgit v1.2.3 From c79a3ccb191809c356044564859c275fba8e5b0f Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 11:06:46 +0800 Subject: dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties The cpu_lp clock property is only needed when the CPUfreq driver supports CPU cluster switching. But it was not a design for this driver and it didn't handle that as well. So removing this property. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt index 031545a29caf..03196d5ea515 100644 --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt @@ -9,7 +9,6 @@ Required properties: See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - cpu_g: Clock mux for the fast CPU cluster. - - cpu_lp: Clock mux for the low-power CPU cluster. - pll_x: Fast PLL clocksource. - pll_p: Auxiliary PLL used during fast PLL rate changes. - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. @@ -30,11 +29,10 @@ cpus { reg = <0>; clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, - <&tegra_car TEGRA124_CLK_CCLK_LP>, <&tegra_car TEGRA124_CLK_PLL_X>, <&tegra_car TEGRA124_CLK_PLL_P>, <&dfll>; - clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; }; -- cgit v1.2.3 From 90484f9b16292d404d1bb3c78a341750455de29d Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 5 Feb 2019 17:33:27 +0000 Subject: dt-bindings: spi: atmel-quadspi: update example to new clock binding Introduced in: commit b60557876849 ("ARM: dts: at91: sama5d2: switch to new clock binding") Signed-off-by: Tudor Ambarus Reviewed-by: Boris Brezillon Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/atmel-quadspi.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt index b93c1e2f25dd..e9dae6264d89 100644 --- a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt +++ b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt @@ -19,7 +19,7 @@ spi@f0020000 { reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>; reg-names = "qspi_base", "qspi_mmap"; interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; -- cgit v1.2.3 From 18f075145e08c75b46779c060cd28e544df6fbb3 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 5 Feb 2019 17:33:30 +0000 Subject: dt-bindings: spi: atmel-quadspi: make "pclk" mandatory Naming clocks is a good practice. Make "pclk" madatory even if we support unnamed clock in the driver, to be backward compatible with old DTs. Suggested-by: Boris Brezillon Signed-off-by: Tudor Ambarus Reviewed-by: Boris Brezillon Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/atmel-quadspi.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt index e9dae6264d89..50bd257e6826 100644 --- a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt +++ b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt @@ -9,6 +9,7 @@ Required properties: - qspi_mmap: memory mapped address space - interrupts: Should contain the interrupt for the device. - clocks: The phandle of the clock needed by the QSPI controller. +- clock-names: Should contain "pclk" for the peripheral clock. - #address-cells: Should be <1>. - #size-cells: Should be <0>. @@ -20,6 +21,7 @@ spi@f0020000 { reg-names = "qspi_base", "qspi_mmap"; interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; + clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; -- cgit v1.2.3 From 3a6c501e96eefb7fd83fbaf9ac29956036d02896 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 5 Feb 2019 17:33:35 +0000 Subject: dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60 The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. Signed-off-by: Tudor Ambarus Reviewed-by: Boris Brezillon Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/atmel-quadspi.txt | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt index 50bd257e6826..7c40ea694352 100644 --- a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt +++ b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt @@ -1,15 +1,19 @@ * Atmel Quad Serial Peripheral Interface (QSPI) Required properties: -- compatible: Should be "atmel,sama5d2-qspi". +- compatible: Should be one of the following: + - "atmel,sama5d2-qspi" + - "microchip,sam9x60-qspi" - reg: Should contain the locations and lengths of the base registers and the mapped memory. - reg-names: Should contain the resource reg names: - qspi_base: configuration register address space - qspi_mmap: memory mapped address space - interrupts: Should contain the interrupt for the device. -- clocks: The phandle of the clock needed by the QSPI controller. -- clock-names: Should contain "pclk" for the peripheral clock. +- clocks: Should reference the peripheral clock and the QSPI system + clock if available. +- clock-names: Should contain "pclk" for the peripheral clock and "qspick" + for the system clock when available. - #address-cells: Should be <1>. - #size-cells: Should be <0>. -- cgit v1.2.3 From 4f0960ba7a6aedee18d5749e13ac74afe939bf2e Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:21:21 +0000 Subject: dt-bindings: rcar-gen3-phy-usb2: Add r8a774c0 support Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Yoshihiro Shimoda Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt index de7b5393c163..ad9c290d8f15 100644 --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt @@ -5,6 +5,8 @@ This file provides information on what the device node for the R-Car generation Required properties: - compatible: "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1 + SoC. + "renesas,usb2-phy-r8a774c0" if the device is a part of an R8A774C0 SoC. "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795 SoC. -- cgit v1.2.3 From e712792ec0dd90124e7d943a782372679350488d Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Wed, 5 Dec 2018 17:03:25 +0200 Subject: dt-bindings: phy: ti: Add support for AM654x USB2 PHY Add support for USB2 PHY on AM654x SoC. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/ti-phy.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt index 57dfda8a7a1d..8f93c3b694a7 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt @@ -35,6 +35,7 @@ Required properties: DRA7x Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY in DRA7x + Should be "ti,am654-usb2" for the USB2 PHYs on AM654. - reg : Address and length of the register set for the device. - #phy-cells: determine the number of cells that should be given in the phandle while referencing this phy. -- cgit v1.2.3 From 68eab01c2179b6ea5132b069cc89b18ca6ef5cb3 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 9 Jan 2019 18:17:39 +0100 Subject: dt-bindings: phy-rockchip-inno-usb2: add documentation for extcon property Commit 98898f3bc83c8 ("phy: rockchip-inno-usb2: support otg-port for rk3399") introduces the extcon property that is used to detect the cable-state. Document this property in the documentation binding. Fixes: 98898f3bc83c8 ("phy: rockchip-inno-usb2: support otg-port for rk3399") Signed-off-by: Enric Balletbo i Serra Reviewed-by: Heiko Stuebner Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt index 074a7b3b0425..00639baae74a 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt @@ -23,6 +23,8 @@ Optional properties: register files". When set driver will request its phandle as one companion-grf for some special SoCs (e.g RV1108). + - extcon : phandle to the extcon device providing the cable state for + the otg phy. Required nodes : a sub-node is required for each port the phy provides. The sub-node name is used to identify host or otg port, -- cgit v1.2.3 From 0ade2930fccf6fbd1e03832b654bf603f6d1afab Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Mon, 14 Jan 2019 09:36:11 -0700 Subject: dt-bindings: phy-qcom: Add support for msm8998 usb USB on msm8998 utilizes the QUSB2 and QMP phys, similar to sdm845. Signed-off-by: Jeffrey Hugo Reviewed-by: Bjorn Andersson Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 5 +++++ Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt | 1 + 2 files changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index 41a1074228ba..4ff26dbf4310 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -9,6 +9,7 @@ Required properties: "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, + "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998, "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845, "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845, "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845. @@ -42,6 +43,8 @@ Required properties: "aux", "cfg_ahb", "ref". For "qcom,msm8996-qmp-usb3-phy" must contain: "aux", "cfg_ahb", "ref". + For "qcom,msm8998-qmp-usb3-phy" must contain: + "aux", "cfg_ahb", "ref". For "qcom,sdm845-qmp-usb3-phy" must contain: "aux", "cfg_ahb", "ref", "com_aux". For "qcom,sdm845-qmp-usb3-uni-phy" must contain: @@ -61,6 +64,8 @@ Required properties: "phy", "common", "cfg". For "qcom,msm8996-qmp-usb3-phy" must contain "phy", "common". + For "qcom,msm8998-qmp-usb3-phy" must contain + "phy", "common". For "qcom,sdm845-qmp-usb3-phy" must contain: "phy", "common". For "qcom,sdm845-qmp-usb3-uni-phy" must contain: diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt index 03025d97998b..fe29f9e0af6d 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt @@ -6,6 +6,7 @@ QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. Required properties: - compatible: compatible list, contains "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996, + "qcom,msm8998-qusb2-phy" for 10nm PHY on msm8998, "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845. - reg: offset and length of the PHY register set. -- cgit v1.2.3 From 6362f0a68d244bc54610ce8238ec46726bb4019f Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 8 Jan 2019 17:31:21 +0100 Subject: dt-bindings: phy: mvebu-comphy: extend the file to describe a3700 bindings Current file describe COMPHY bindings for the IP available on the CP110 of Armada 7k/8k. Bindings are very close (and serve the same purpose) as the new Armada 3700 COMPHY driver so update this file to describe both. Also add an example of how to use this second compatible (same as for the ESPRESSObin). While doing so, enhance a bit the file by adding upper case where needed. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/phy-mvebu-comphy.txt | 65 ++++++++++++++++++---- 1 file changed, 53 insertions(+), 12 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt index bfcf80341657..cf2cd86db267 100644 --- a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt @@ -1,16 +1,27 @@ -mvebu comphy driver -------------------- +MVEBU comphy drivers +-------------------- -A comphy controller can be found on Marvell Armada 7k/8k on the CP110. It -provides a number of shared PHYs used by various interfaces (network, sata, -usb, PCIe...). +COMPHY controllers can be found on the following Marvell MVEBU SoCs: +* Armada 7k/8k (on the CP110) +* Armada 3700 +It provides a number of shared PHYs used by various interfaces (network, SATA, +USB, PCIe...). Required properties: -- compatible: should be "marvell,comphy-cp110" -- reg: should contain the comphy register location and length. -- marvell,system-controller: should contain a phandle to the - system controller node. +- compatible: should be one of: + * "marvell,comphy-cp110" for Armada 7k/8k + * "marvell,comphy-a3700" for Armada 3700 +- reg: should contain the COMPHY register(s) location(s) and length(s). + * 1 entry for Armada 7k/8k + * 4 entries for Armada 3700 along with the corresponding reg-names + properties, memory areas are: + * Generic COMPHY registers + * Lane 1 (PCIe/GbE) + * Lane 0 (USB3/GbE) + * Lane 2 (SATA/USB3) +- marvell,system-controller: should contain a phandle to the system + controller node (only for Armada 7k/8k) - #address-cells: should be 1. - #size-cells: should be 0. @@ -18,11 +29,11 @@ A sub-node is required for each comphy lane provided by the comphy. Required properties (child nodes): -- reg: comphy lane number. -- #phy-cells : from the generic phy bindings, must be 1. Defines the +- reg: COMPHY lane number. +- #phy-cells : from the generic PHY bindings, must be 1. Defines the input port to use for a given comphy lane. -Example: +Examples: cpm_comphy: phy@120000 { compatible = "marvell,comphy-cp110"; @@ -41,3 +52,33 @@ Example: #phy-cells = <1>; }; }; + + comphy: phy@18300 { + compatible = "marvell,comphy-a3700"; + reg = <0x18300 0x300>, + <0x1F000 0x400>, + <0x5C000 0x400>, + <0xe0178 0x8>; + reg-names = "comphy", + "lane1_pcie_gbe", + "lane0_usb3_gbe", + "lane2_sata_usb3"; + #address-cells = <1>; + #size-cells = <0>; + + + comphy0: phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + + comphy1: phy@1 { + reg = <1>; + #phy-cells = <1>; + }; + + comphy2: phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; -- cgit v1.2.3 From e60958699afa3468cfe36fdd3c2eefdcb5326176 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 29 Jan 2019 10:36:31 +0100 Subject: dt-bindings: phy: mvebu-utmi: add UTMI PHY bindings Add bindings for Marvell Armada 3700 USB2 UTMI+ PHY. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/phy-mvebu-utmi.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt new file mode 100644 index 000000000000..aa99ceec73b0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt @@ -0,0 +1,38 @@ +MVEBU A3700 UTMI PHY +-------------------- + +USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs: +* Armada 3700 + +On Armada 3700, there are two USB controllers, one is compatible with the USB2 +and USB3 specifications and supports OTG. The other one is USB2 compliant and +only supports host mode. Both of these controllers come with a slightly +different UTMI PHY. + +Required Properties: + +- compatible: Should be one of: + * "marvell,a3700-utmi-host-phy" for the PHY connected to + the USB2 host-only controller. + * "marvell,a3700-utmi-otg-phy" for the PHY connected to + the USB3 and USB2 OTG capable controller. +- reg: PHY IP register range. +- marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared + region covering registers related to both the host + controller and the PHY. +- #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0. + + +Example: + + usb2_utmi_host_phy: phy@5f000 { + compatible = "marvell,armada-3700-utmi-host-phy"; + reg = <0x5f000 0x800>; + marvell,usb-misc-reg = <&usb2_syscon>; + #phy-cells = <0>; + }; + + usb2_syscon: system-controller@5f800 { + compatible = "marvell,armada-3700-usb2-host-misc", "syscon"; + reg = <0x5f800 0x800>; + }; -- cgit v1.2.3 From df68734101e9ebad7a48e982cbea1775c170c2a3 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 21 Jan 2019 16:45:52 +0100 Subject: dt-bindings: phy: Move the Cadence D-PHY bindings The Cadence D-PHY bindings was defined as part of the DSI block so far. However, since it's now going to be a separate driver, we need to move the binding to a file of its own. Acked-by: Sakari Ailus Signed-off-by: Maxime Ripard Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/display/bridge/cdns,dsi.txt | 21 --------------------- Documentation/devicetree/bindings/phy/cdns,dphy.txt | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt index f5725bb6c61c..525a4bfd8634 100644 --- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt @@ -31,28 +31,7 @@ Required subnodes: - one subnode per DSI device connected on the DSI bus. Each DSI device should contain a reg property encoding its virtual channel. -Cadence DPHY -============ - -Cadence DPHY block. - -Required properties: -- compatible: should be set to "cdns,dphy". -- reg: physical base address and length of the DPHY registers. -- clocks: DPHY reference clocks. -- clock-names: must contain "psm" and "pll_ref". -- #phy-cells: must be set to 0. - - Example: - dphy0: dphy@fd0e0000{ - compatible = "cdns,dphy"; - reg = <0x0 0xfd0e0000 0x0 0x1000>; - clocks = <&psm_clk>, <&pll_ref_clk>; - clock-names = "psm", "pll_ref"; - #phy-cells = <0>; - }; - dsi0: dsi@fd0c0000 { compatible = "cdns,dsi"; reg = <0x0 0xfd0c0000 0x0 0x1000>; diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.txt b/Documentation/devicetree/bindings/phy/cdns,dphy.txt new file mode 100644 index 000000000000..1095bc4e72d9 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.txt @@ -0,0 +1,20 @@ +Cadence DPHY +============ + +Cadence DPHY block. + +Required properties: +- compatible: should be set to "cdns,dphy". +- reg: physical base address and length of the DPHY registers. +- clocks: DPHY reference clocks. +- clock-names: must contain "psm" and "pll_ref". +- #phy-cells: must be set to 0. + +Example: + dphy0: dphy@fd0e0000{ + compatible = "cdns,dphy"; + reg = <0x0 0xfd0e0000 0x0 0x1000>; + clocks = <&psm_clk>, <&pll_ref_clk>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + }; -- cgit v1.2.3 From 469de49e88a3f877425009d45d6ac801f9aefe19 Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Tue, 29 Jan 2019 15:05:38 -0800 Subject: dt-bindings: mfd: aspeed-lpc: Make parameter optional Memory-region and flash phandle is not a required parameter, it is optional to describe in device tree and needed only use basis. Signed-off-by: Vijay Khemka Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/aspeed-lpc.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index 34dd89087cff..86446074e206 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt @@ -135,6 +135,8 @@ Required properties: - clocks: contains a phandle to the syscon node describing the clocks. There should then be one cell representing the clock to use +Optional properties: + - memory-region: A phandle to a reserved_memory region to be used for the LPC to AHB mapping -- cgit v1.2.3 From fdc98f070b149b038a66e57dea11f2fabb5fdfbc Mon Sep 17 00:00:00 2001 From: Charles Keepax Date: Wed, 30 Jan 2019 11:41:23 +0000 Subject: mfd: lochnagar: Add initial binding documentation Lochnagar is an evaluation and development board for Cirrus Logic Smart CODEC and Amp devices. It allows the connection of most Cirrus Logic devices on mini-cards, as well as allowing connection of various application processor systems to provide a full evaluation platform. This driver supports the board controller chip on the Lochnagar board. Signed-off-by: Charles Keepax Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/cirrus,lochnagar.txt | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/cirrus,lochnagar.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/cirrus,lochnagar.txt b/Documentation/devicetree/bindings/mfd/cirrus,lochnagar.txt new file mode 100644 index 000000000000..004b0158cf4d --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/cirrus,lochnagar.txt @@ -0,0 +1,68 @@ +Cirrus Logic Lochnagar Audio Development Board + +Lochnagar is an evaluation and development board for Cirrus Logic +Smart CODEC and Amp devices. It allows the connection of most Cirrus +Logic devices on mini-cards, as well as allowing connection of +various application processor systems to provide a full evaluation +platform. Audio system topology, clocking and power can all be +controlled through the Lochnagar, allowing the device under test +to be used in a variety of possible use cases. + +Also see these documents for generic binding information: + [1] GPIO : ../gpio/gpio.txt + +And these for relevant defines: + [2] include/dt-bindings/pinctrl/lochnagar.h + [3] include/dt-bindings/clock/lochnagar.h + +And these documents for the required sub-node binding details: + [4] Clock: ../clock/cirrus,lochnagar.txt + [5] Pinctrl: ../pinctrl/cirrus,lochnagar.txt + [6] Regulator: ../regulator/cirrus,lochnagar.txt + +Required properties: + + - compatible : One of the following strings: + "cirrus,lochnagar1" + "cirrus,lochnagar2" + + - reg : I2C slave address + + - reset-gpios : Reset line to the Lochnagar, see [1]. + +Required sub-nodes: + + - lochnagar-clk : Binding for the clocking components, see [4]. + + - lochnagar-pinctrl : Binding for the pin control components, see [5]. + +Optional sub-nodes: + + - Bindings for the regulator components, see [6]. Only available on + Lochnagar 2. + +Optional properties: + + - present-gpios : Host present line, indicating the presence of a + host system, see [1]. This can be omitted if the present line is + tied in hardware. + +Example: + +lochnagar: lochnagar@22 { + compatible = "cirrus,lochnagar2"; + reg = <0x22>; + + reset-gpios = <&gpio0 55 0>; + present-gpios = <&gpio0 60 0>; + + lochnagar-clk { + compatible = "cirrus,lochnagar2-clk"; + ... + }; + + lochnagar-pinctrl { + compatible = "cirrus,lochnagar-pinctrl"; + ... + }; +}; -- cgit v1.2.3 From 684c1b1457a2d83bd3138e244af220f943caef9e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Chmiel?= Date: Fri, 28 Dec 2018 16:19:03 +0100 Subject: dt-bindings: gpu: samsung-rotator: Document s5pv210 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit documents new compatible for s5pv210 soc, which will be also supported by this driver. Signed-off-by: Paweł Chmiel Reviewed-by: Rob Herring Acked-by: Krzysztof Kozlowski Signed-off-by: Inki Dae --- Documentation/devicetree/bindings/gpu/samsung-rotator.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/samsung-rotator.txt b/Documentation/devicetree/bindings/gpu/samsung-rotator.txt index 82cd1ed0be93..3aca2578da0b 100644 --- a/Documentation/devicetree/bindings/gpu/samsung-rotator.txt +++ b/Documentation/devicetree/bindings/gpu/samsung-rotator.txt @@ -2,9 +2,10 @@ Required properties: - compatible : value should be one of the following: - (a) "samsung,exynos4210-rotator" for Rotator IP in Exynos4210 - (b) "samsung,exynos4212-rotator" for Rotator IP in Exynos4212/4412 - (c) "samsung,exynos5250-rotator" for Rotator IP in Exynos5250 + * "samsung,s5pv210-rotator" for Rotator IP in S5PV210 + * "samsung,exynos4210-rotator" for Rotator IP in Exynos4210 + * "samsung,exynos4212-rotator" for Rotator IP in Exynos4212/4412 + * "samsung,exynos5250-rotator" for Rotator IP in Exynos5250 - reg : Physical base address of the IP registers and length of memory mapped region. -- cgit v1.2.3 From 7c536bade37f11833ea358fbb84aca045b157fa4 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Thu, 7 Feb 2019 10:31:38 -0300 Subject: dt-bindings: sound: Document jz4740-codec bindings Add documentation about how to probe the jz4740-codec driver from devicetree. Signed-off-by: Paul Cercueil Signed-off-by: Mark Brown --- .../bindings/sound/ingenic,jz4740-codec.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/ingenic,jz4740-codec.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/ingenic,jz4740-codec.txt b/Documentation/devicetree/bindings/sound/ingenic,jz4740-codec.txt new file mode 100644 index 000000000000..1ffcade87e7b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ingenic,jz4740-codec.txt @@ -0,0 +1,20 @@ +Ingenic JZ4740 codec controller + +Required properties: +- compatible : "ingenic,jz4740-codec" +- reg : codec registers location and length +- clocks : phandle to the AIC clock. +- clock-names: must be set to "aic". +- #sound-dai-cells: Must be set to 0. + +Example: + +codec: audio-codec@10020080 { + compatible = "ingenic,jz4740-codec"; + reg = <0x10020080 0x8>; + + #sound-dai-cells = <0>; + + clocks = <&cgu JZ4740_CLK_AIC>; + clock-names = "aic"; +}; -- cgit v1.2.3 From f58f2b0a9f6ecfd76cb08fe1c4894ab009a30c66 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Thu, 7 Feb 2019 10:31:39 -0300 Subject: dt-bindings: sound: Document jz4725b-codec bindings Add documentation about how to probe the jz4725b-codec driver from devicetree. Signed-off-by: Paul Cercueil Signed-off-by: Mark Brown --- .../bindings/sound/ingenic,jz4725b-codec.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/ingenic,jz4725b-codec.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/ingenic,jz4725b-codec.txt b/Documentation/devicetree/bindings/sound/ingenic,jz4725b-codec.txt new file mode 100644 index 000000000000..05adc0d47b13 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ingenic,jz4725b-codec.txt @@ -0,0 +1,20 @@ +Ingenic JZ4725B codec controller + +Required properties: +- compatible : "ingenic,jz4725b-codec" +- reg : codec registers location and length +- clocks : phandle to the AIC clock. +- clock-names: must be set to "aic". +- #sound-dai-cells: Must be set to 0. + +Example: + +codec: audio-codec@100200a4 { + compatible = "ingenic,jz4725b-codec"; + reg = <0x100200a4 0x8>; + + #sound-dai-cells = <0>; + + clocks = <&cgu JZ4725B_CLK_AIC>; + clock-names = "aic"; +}; -- cgit v1.2.3 From b7f456ced7f0e251ba14d8a5a1dd307096bb5306 Mon Sep 17 00:00:00 2001 From: Erin Lo Date: Thu, 24 Jan 2019 16:07:16 +0800 Subject: dt-bindings: arm: Add bindings for Mediatek MT8183 SoC Platform This adds dt-binding documentation of cpu for Mediatek MT8183. Signed-off-by: Erin Lo Reviewed-by: Rob Herring Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index 8f260e5cfd16..f6d6ed383aa2 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -20,6 +20,7 @@ compatible: Must contain one of "mediatek,mt8127" "mediatek,mt8135" "mediatek,mt8173" + "mediatek,mt8183" Supported boards: @@ -77,3 +78,6 @@ Supported boards: - MTK mt8173 tablet EVB: Required root node properties: - compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; +- Evaluation board for MT8183: + Required root node properties: + - compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; -- cgit v1.2.3 From dd93f84655777d690bbc4e9f65180fe5e0384734 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Tue, 29 Jan 2019 12:31:14 +0800 Subject: dt-bindings: arm: mediatek: remove unused "mediatek, mt7623a" As we fallback to use "mediatek,mt7623" for MT7623a, remove unused root node property "mediatek,mt7623a" in the document. Signed-off-by: Ryder Lee Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index f6d6ed383aa2..f96d74a5c43b 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -15,8 +15,7 @@ compatible: Must contain one of "mediatek,mt6795" "mediatek,mt6797" "mediatek,mt7622" - "mediatek,mt7623" which is referred to MT7623N SoC - "mediatek,mt7623a" + "mediatek,mt7623" "mediatek,mt8127" "mediatek,mt8135" "mediatek,mt8173" -- cgit v1.2.3 From 858a6c310f7761314164e3a49c05f25330595d92 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Tue, 29 Jan 2019 12:31:15 +0800 Subject: dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFB Update binding document for MT7622 BPI-R64 and MT7629 reference board. Signed-off-by: Ryder Lee Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index f96d74a5c43b..56ac7896d6d8 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -16,6 +16,7 @@ compatible: Must contain one of "mediatek,mt6797" "mediatek,mt7622" "mediatek,mt7623" + "mediatek,mt7629" "mediatek,mt8127" "mediatek,mt8135" "mediatek,mt8173" @@ -57,6 +58,9 @@ Supported boards: - Reference board variant 1 for MT7622: Required root node properties: - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; +- Bananapi BPI-R64 for MT7622: + Required root node properties: + - compatible = "bananapi,bpi-r64", "mediatek,mt7622"; - Reference board for MT7623a with eMMC: Required root node properties: - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623"; @@ -68,6 +72,9 @@ Supported boards: - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623"; - Bananapi BPI-R2 board: - compatible = "bananapi,bpi-r2", "mediatek,mt7623"; +- Reference board for MT7629: + Required root node properties: + - compatible = "mediatek,mt7629-rfb", "mediatek,mt7629"; - MTK mt8127 tablet moose EVB: Required root node properties: - compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; -- cgit v1.2.3 From 6c2b3881d0df85fed7e3f43dcc9cbc3e5124bc12 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Jan 2019 11:00:57 +0100 Subject: dt-bindings: display: tegra: Support SOR crossbar configuration The SOR has a crossbar that can map each lane of the SOR to each of the SOR pads. The mapping is usually the same across designs for a specific SoC generation, but every now and then there's a design that doesn't. Allow the crossbar configuration to be specified in device tree to make it possible to support these designs. Signed-off-by: Thierry Reding --- .../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 593be44a53c9..9999255ac5b6 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -238,6 +238,9 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane + of the SOR, identified by the cell's index, is mapped via the crossbar to + the pad specified by the cell's value. Optional properties when driving an eDP output: - nvidia,dpaux: phandle to a DispayPort AUX interface -- cgit v1.2.3 From 8a2fe6c09f2ac17c7605982bc6810ea2b2c2a0d0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 22 Jan 2019 15:25:46 +0000 Subject: dt-bindings: display: renesas: lvds: Document r8a7744 bindings Document the RZ/G1N (R8A7744) LVDS bindings. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart Reviewed-by: Simon Horman Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt index 27a054e1bb5f..900a884ad9f5 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt +++ b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt @@ -8,6 +8,7 @@ Required properties: - compatible : Shall contain one of - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders + - "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders - "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders -- cgit v1.2.3 From c28de6bf856eac0b0d1854d57c7a55b7c65a46e3 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 18 Jan 2019 11:34:20 +0100 Subject: dt-bindings: amlogic: add new compatible devices to clk_measure Add the axg and g12a SoC family compatible to the clock measure bindings Signed-off-by: Jerome Brunet Reviewed-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt index 205a54bcd7c7..6bf6b43f8dd8 100644 --- a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt +++ b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt @@ -9,6 +9,8 @@ Required properties: "amlogic,meson-gx-clk-measure" for GX SoCs "amlogic,meson8-clk-measure" for Meson8 SoCs "amlogic,meson8b-clk-measure" for Meson8b SoCs + "amlogic,meson-axg-clk-measure" for AXG SoCs + "amlogic,meson-g12a-clk-measure" for G12a SoCs - reg: base address and size of the Clock Measurer register space. Example: -- cgit v1.2.3 From 120382714c0456037b23b6e0c12f04bf2736e5e4 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 7 Feb 2019 16:19:05 +0000 Subject: dt-bindings: phy: Armada 38x common phy bindings Add the Marvell Armada 38x common phy bindings. Signed-off-by: Russell King Signed-off-by: David S. Miller --- .../bindings/phy/phy-armada38x-comphy.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-armada38x-comphy.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-armada38x-comphy.txt b/Documentation/devicetree/bindings/phy/phy-armada38x-comphy.txt new file mode 100644 index 000000000000..ad49e5c01334 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-armada38x-comphy.txt @@ -0,0 +1,40 @@ +mvebu armada 38x comphy driver +------------------------------ + +This comphy controller can be found on Marvell Armada 38x. It provides a +number of shared PHYs used by various interfaces (network, sata, usb, +PCIe...). + +Required properties: + +- compatible: should be "marvell,armada-380-comphy" +- reg: should contain the comphy register location and length. +- #address-cells: should be 1. +- #size-cells: should be 0. + +A sub-node is required for each comphy lane provided by the comphy. + +Required properties (child nodes): + +- reg: comphy lane number. +- #phy-cells : from the generic phy bindings, must be 1. Defines the + input port to use for a given comphy lane. + +Example: + + comphy: phy@18300 { + compatible = "marvell,armada-380-comphy"; + reg = <0x18300 0x100>; + #address-cells = <1>; + #size-cells = <0>; + + cpm_comphy0: phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + + cpm_comphy1: phy@1 { + reg = <1>; + #phy-cells = <1>; + }; + }; -- cgit v1.2.3 From 4ca124f4d96d7c976f2753c874d095c0de83d280 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 7 Feb 2019 16:19:21 +0000 Subject: dt-bindings: net: mvneta: add phys property Add an optional phys property to the mvneta binding documentation for the common phy. Reviewed-by: Rob Herring Signed-off-by: Russell King Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt index bedcfd5a52cd..691f886cfc4a 100644 --- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt +++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt @@ -19,7 +19,7 @@ Optional properties: "marvell,armada-370-neta" and 9800B for others. - clock-names: List of names corresponding to clocks property; shall be "core" for core clock and "bus" for the optional bus clock. - +- phys: comphy for the ethernet port, see ../phy/phy-bindings.txt Optional properties (valid only for Armada XP/38x): -- cgit v1.2.3 From 001aca0dbb1d791c676c50a7a610921b6c9b2180 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 30 Jan 2019 21:20:05 +0100 Subject: dt-bindings: Add a prefix for Gateworks Corporation As I am adding a PLD GPIO driver for Gateworks, we need their prefix among the vendors. Cc: Imre Kaloz Cc: Tim Harvey Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..c9af4e33f00b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -141,6 +141,7 @@ focaltech FocalTech Systems Co.,Ltd friendlyarm Guangzhou FriendlyARM Computer Tech Co., Ltd fsl Freescale Semiconductor fujitsu Fujitsu Ltd. +gateworks Gateworks Corporation gcw Game Consoles Worldwide ge General Electric Company geekbuying GeekBuying -- cgit v1.2.3 From 35b21b6ef888e69c42d7dc93bc360084d31e95f4 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 30 Jan 2019 21:31:55 +0100 Subject: gpio: Add DT bindings for Gateworks PLD GPIO This adds device tree bindings for the Gateworks PLD GPIO chip, a simple I2C GPIO controller. Cc: devicetree@vger.kernel.org Cc: Imre Kaloz Cc: Tim Harvey Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gateworks,pld-gpio.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gateworks,pld-gpio.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gateworks,pld-gpio.txt b/Documentation/devicetree/bindings/gpio/gateworks,pld-gpio.txt new file mode 100644 index 000000000000..6e81f8b755c5 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gateworks,pld-gpio.txt @@ -0,0 +1,20 @@ +Gateworks PLD GPIO controller bindings + +The GPIO controller should be a child node on an I2C bus, +see: i2c/i2c.txt for details. + +Required properties: +- compatible: Should be "gateworks,pld-gpio" +- reg: I2C slave address +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Should be <2>. The first cell is the gpio number and + the second cell is used to specify optional parameters. + +Example: + +pld@56 { + compatible = "gateworks,pld-gpio"; + reg = <0x56>; + gpio-controller; + #gpio-cells = <2>; +}; -- cgit v1.2.3 From 1d741f2e977d7783cd706d6759e29cf36be9d412 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 7 Feb 2019 09:24:57 +0000 Subject: dt-bindings: add documentation for banks Add documentation for at91 pin controller banks. Signed-off-by: Claudiu Beznea Acked-by: Ludovic Desroches Signed-off-by: Linus Walleij --- .../bindings/pinctrl/atmel,at91-pinctrl.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index 3e23fece99da..40e33dfc36fd 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt @@ -116,6 +116,18 @@ Some requirements for using atmel,at91rm9200-pinctrl binding: configurations by referring to the phandle of that pin configuration node. 4. The gpio controller must be describe in the pinctrl simple-bus. +For each bank the required properties are: +- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" +- reg: physical base address and length of the controller's registers +- interrupts: interrupt outputs from the controller +- interrupt-controller: marks the device node as an interrupt controller +- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt + for more details. +- gpio-controller +- #gpio-cells: should be 2; the first cell is the GPIO number and the second + cell specifies GPIO flags as defined in . +- clocks: bank clock + Examples: pinctrl@fffff400 { @@ -125,6 +137,17 @@ pinctrl@fffff400 { compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; reg = <0xfffff400 0x600>; + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + atmel,mux-mask = < /* A B */ 0xffffffff 0xffc00c3b /* pioA */ -- cgit v1.2.3 From fde84f194aaddc3988e5cdc0c7088e5cd9683061 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 7 Feb 2019 09:25:01 +0000 Subject: dt-bindings: add bindings for SAM9X60 Add device tree binding for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea Acked-by: Ludovic Desroches Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index 40e33dfc36fd..470283b4ddbf 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt @@ -19,7 +19,7 @@ such as pull-up, multi drive, etc. Required properties for iomux controller: - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" - or "atmel,sama5d3-pinctrl" + or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl" - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be configured in this periph mode. All the periph and bank need to be describe. @@ -117,7 +117,8 @@ Some requirements for using atmel,at91rm9200-pinctrl binding: 4. The gpio controller must be describe in the pinctrl simple-bus. For each bank the required properties are: -- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" +- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or + "microchip,sam9x60-gpio" - reg: physical base address and length of the controller's registers - interrupts: interrupt outputs from the controller - interrupt-controller: marks the device node as an interrupt controller -- cgit v1.2.3 From 5e07a820649bc7e29249c832abc33c1bffd0e2db Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 7 Feb 2019 09:25:08 +0000 Subject: dt-bindings: add documentation for slew rate Add documentation for slew rate. Signed-off-by: Claudiu Beznea Acked-by: Ludovic Desroches Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index 470283b4ddbf..eb39f5051159 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt @@ -100,6 +100,7 @@ DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the 11 - High OUTPUT (1 << 7): indicate this pin need to be configured as an output. OUTPUT_VAL (1 << 8): output val (1 = high, 0 = low) +SLEWRATE (1 << 9): slew rate of the pin: 0 = disable, 1 = enable DEBOUNCE (1 << 16): indicate this pin needs debounce. DEBOUNCE_VAL (0x3fff << 17): debounce value. -- cgit v1.2.3 From 60b71a239bbd286232a547349815d6330f10db7c Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Tue, 29 Jan 2019 12:31:17 +0800 Subject: dt-bindings: interrupt-controller: update bindings for MT7623 This adds missing bindings for MT7623 sysirq. Signed-off-by: Ryder Lee Signed-off-by: Matthias Brugger --- .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt index 33a98eb44949..c5d589108a94 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt @@ -9,6 +9,7 @@ Required properties: "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135 "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127 "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622 + "mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623 "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795 "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797 "mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765 -- cgit v1.2.3 From 0d250bf24a68ec25b4aa2b07c200b7de4607b182 Mon Sep 17 00:00:00 2001 From: James Schulman Date: Thu, 7 Feb 2019 12:12:19 -0600 Subject: ASoC: cs35l36: Add device tree documentation for CS35L36 Add device tree documentation for Cirrus Logic CS35L36 speaker amplifier Signed-off-by: James Schulman Reviewed-by: Charles Keepax Acked-by: Brian Austin Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/cs35l36.txt | 168 +++++++++++++++++++++ 1 file changed, 168 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/cs35l36.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/cs35l36.txt b/Documentation/devicetree/bindings/sound/cs35l36.txt new file mode 100644 index 000000000000..912bd162b477 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs35l36.txt @@ -0,0 +1,168 @@ +CS35L36 Speaker Amplifier + +Required properties: + + - compatible : "cirrus,cs35l36" + + - reg : the I2C address of the device for I2C + + - VA-supply, VP-supply : power supplies for the device, + as covered in + Documentation/devicetree/bindings/regulator/regulator.txt. + + - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost + converter's output voltage in mV. The range is from 2550mV to 12000mV with + increments of 50mV. + (Default) VP + + - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA. + Configures the peak current by monitoring the current through the boost FET. + Range starts at 1600mA and goes to a maximum of 4500mA with increments of + 50mA. + (Default) 4.50 Amps + + - cirrus,boost-ind-nanohenry : Inductor estimation LBST reference value. + Seeds the digital boost converter's inductor estimation block with the initial + inductance value to reference. + + 1000 = 1uH (Default) + 1200 = 1.2uH + +Optional properties: + - cirrus,multi-amp-mode : Boolean to determine if there are more than + one amplifier in the system. If more than one it is best to Hi-Z the ASP + port to prevent bus contention on the output signal + + - cirrus,boost-ctl-select : Boost conerter control source selection. + Selects the source of the BST_CTL target VBST voltage for the boost + converter to generate. + 0x00 - Control Port Value + 0x01 - Class H Tracking (Default) + 0x10 - MultiDevice Sync Value + + - cirrus,amp-pcm-inv : Boolean to determine Amplifier will invert incoming + PCM data + + - cirrus,imon-pol-inv : Boolean to determine Amplifier will invert the + polarity of outbound IMON feedback data + + - cirrus,vmon-pol-inv : Boolean to determine Amplifier will invert the + polarity of outbound VMON feedback data + + - cirrus,dcm-mode-enable : Boost converter automatic DCM Mode enable. + This enables the digital boost converter to operate in a low power + (Discontinuous Conduction) mode during low loading conditions. + + - cirrus,weak-fet-disable : Boolean : The strength of the output drivers is + reduced when operating in a Weak-FET Drive Mode and must not be used to drive + a large load. + + - cirrus,classh-wk-fet-delay : Weak-FET entry delay. Controls the delay + (in ms) before the Class H algorithm switches to the weak-FET voltage + (after the audio falls and remains below the value specified in WKFET_AMP_THLD). + + 0 = 0ms + 1 = 5ms + 2 = 10ms + 3 = 50ms + 4 = 100ms (Default) + 5 = 200ms + 6 = 500ms + 7 = 1000ms + + - cirrus,classh-weak-fet-thld-millivolt : Weak-FET amplifier drive threshold. + Configures the signal threshold at which the PWM output stage enters + weak-FET operation. The range is 50mV to 700mV in 50mV increments. + + - cirrus,temp-warn-threshold : Amplifier overtemperature warning threshold. + Configures the threshold at which the overtemperature warning condition occurs. + When the threshold is met, the overtemperature warning attenuation is applied + and the TEMP_WARN_EINT interrupt status bit is set. + If TEMP_WARN_MASK = 0, INTb is asserted. + + 0 = 105C + 1 = 115C + 2 = 125C (Default) + 3 = 135C + + - cirrus,irq-drive-select : Selects the driver type of the selected interrupt + output. + + 0 = Open-drain + 1 = Push-pull (Default) + + - cirrus,irq-gpio-select : Selects the pin to serve as the programmable + interrupt output. + + 0 = PDM_DATA / SWIRE_SD / INT (Default) + 1 = GPIO + +Optional properties for the "cirrus,vpbr-config" Sub-node + + - cirrus,vpbr-en : VBST brownout prevention enable. Configures whether the + VBST brownout prevention algorithm is enabled or disabled. + + 0 = VBST brownout prevention disabled (default) + 1 = VBST brownout prevention enabled + + See Section 7.31.1 VPBR Config for configuration options & further details + + - cirrus,vpbr-thld : Initial VPBR threshold. Configures the VP brownout + threshold voltage + + - cirrus,cirrus,vpbr-atk-rate : Attenuation attack step rate. Configures the + amount delay between consecutive volume attenuation steps when a brownout + condition is present and the VP brownout condition is in an attacking state. + + - cirrus,vpbr-atk-vol : VP brownout prevention step size. Configures the VP + brownout prevention attacking attenuation step size when operating in either + digital volume or analog gain modes. + + - cirrus,vpbr-max-attn : Maximum attenuation that the VP brownout prevention + can apply to the audio signal. + + - cirrus,vpbr-wait : Configures the delay time between a brownout condition + no longer being present and the VP brownout prevention entering an attenuation + release state. + + - cirrus,vpbr-rel-rate : Attenuation release step rate. Configures the delay + between consecutive volume attenuation release steps when a brownout condition + is not longer present and the VP brownout is in an attenuation release state. + + - cirrus,vpbr-mute-en : During the attack state, if the vpbr-max-attn value + is reached, the error condition still remains, and this bit is set, the audio + is muted. + +Example: + +cs35l36: cs35l36@40 { + compatible = "cirrus,cs35l36"; + reg = <0x40>; + VA-supply = <&dummy_vreg>; + VP-supply = <&dummy_vreg>; + reset-gpios = <&gpio0 54 0>; + interrupt-parent = <&gpio8>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-ctl-millivolt = <10000>; + cirrus,boost-peak-milliamp = <4500>; + cirrus,boost-ctl-select = <0x00>; + cirrus,weak-fet-delay = <0x04>; + cirrus,weak-fet-thld = <0x01>; + cirrus,temp-warn-threshold = <0x01>; + cirrus,multi-amp-mode; + cirrus,irq-drive-select = <0x01>; + cirrus,irq-gpio-select = <0x01>; + + cirrus,vpbr-config { + cirrus,vpbr-en = <0x00>; + cirrus,vpbr-thld = <0x05>; + cirrus,vpbr-atk-rate = <0x02>; + cirrus,vpbr-atk-vol = <0x01>; + cirrus,vpbr-max-attn = <0x09>; + cirrus,vpbr-wait = <0x01>; + cirrus,vpbr-rel-rate = <0x05>; + cirrus,vpbr-mute-en = <0x00>; + }; +}; -- cgit v1.2.3 From 510135535382db7f5ee8727818172e42c9c9cbd5 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 7 Feb 2019 17:57:55 +0100 Subject: dt-bindings: sound: msm8916-wcd-analog: fix example regulator names Fix upper-case regulator names in the binding example which do not match the corresponding required properties. While at it, add a blank line after the required-properties section to improve readability. Signed-off-by: Johan Hovold Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt index fdcea3d12ee5..e7d17dda55db 100644 --- a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt +++ b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt @@ -30,6 +30,7 @@ Required properties - vdd-cdc-io-supply: phandle to VDD_CDC_IO regulator DT node. - vdd-cdc-tx-rx-cx-supply: phandle to VDD_CDC_TX/RX/CX regulator DT node. - vdd-micbias-supply: phandle of VDD_MICBIAS supply's regulator DT node. + Optional Properties: - qcom,mbhc-vthreshold-low: Array of 5 threshold voltages in mV for 5 buttons detection on headset when the mbhc is powered up @@ -92,9 +93,9 @@ spmi_bus { "cdc_ear_cnp_int", "cdc_hphr_cnp_int", "cdc_hphl_cnp_int"; - VDD-CDC-IO-supply = <&pm8916_l5>; - VDD-CDC-TX-RX-CX-supply = <&pm8916_l5>; - VDD-MICBIAS-supply = <&pm8916_l13>; + vdd-cdc-io-supply = <&pm8916_l5>; + vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; + vdd-micbias-supply = <&pm8916_l13>; #sound-dai-cells = <1>; }; }; -- cgit v1.2.3 From b735f41dcb06ae06acab2618b8814fe2dd1fca90 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 8 Feb 2019 15:04:25 +0100 Subject: dt-bindings: regulator: update fixed-regulator example Fixed regulators do not have associated bus addresses and are typically placed directly under the root node where their names must still be unique despite not having a unit address. Fix the malformed example node which had a unit address but no "reg" property by dropping the unit address. Also, try to make the example more useful by using the recommended generic node name "regulator", but with a suffix reflecting the regulator name in order to make it unique. Signed-off-by: Johan Hovold Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/fixed-regulator.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml b/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml index a7607b0baab7..d289c2f7455a 100644 --- a/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml @@ -52,9 +52,9 @@ required: examples: - | - abc: fixedregulator@0 { + reg_1v8: regulator-1v8 { compatible = "regulator-fixed"; - regulator-name = "fixed-supply"; + regulator-name = "1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio1 16 0>; -- cgit v1.2.3 From 148423b7454b6f2cee71e2c43aee99ab24acb434 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 18 Dec 2018 16:12:15 -0800 Subject: dt-bindings: arm: amlogic: add amediatech x96-max bindings Add new vendor for amediatech, and initial board: x96-max Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 1 + Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 2 files changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 8dbc259081e4..7f40cb5f490b 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -109,6 +109,7 @@ Board compatible values (alphabetically, grouped by SoC): - "amlogic,s400" (Meson axg a113d) - "amlogic,u200" (Meson g12a s905d2) + - "amediatech,x96-max" (Meson g12a s905x2) Amlogic Meson Firmware registers Interface ------------------------------------------ diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..4615d4b9d11e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -24,6 +24,7 @@ amarula Amarula Solutions amazon Amazon.com, Inc. amcc Applied Micro Circuits Corporation (APM, formally AMCC) amd Advanced Micro Devices (AMD), Inc. +amediatech Shenzhen Amediatech Technology Co., Ltd amlogic Amlogic, Inc. ampire Ampire Co., Ltd. ams AMS AG -- cgit v1.2.3 From 7d7e58d30e046d3471295a256d15e0b6bdd502c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Fri, 8 Feb 2019 19:24:48 +0100 Subject: dt-bindings: display: ssd1307fb: Remove reset-active-low from examples MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The reset-active-low property has been removed brom the binding a while ago. So remove it from the examples as well. Fixes: 519b4db ("fbdev: ssd1307fb: Remove reset-active-low from the DT binding document") Reviewed-by: Rob Herring Reviewed-by: Alexandre Belloni Cc: Shawn Guo Cc: Fabio Estevam Cc: Maxime Ripard , Signed-off-by: Michal Vokáč Signed-off-by: Bartlomiej Zolnierkiewicz --- Documentation/devicetree/bindings/display/ssd1307fb.txt | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/ssd1307fb.txt b/Documentation/devicetree/bindings/display/ssd1307fb.txt index 209d931ef16c..b67f8caa212c 100644 --- a/Documentation/devicetree/bindings/display/ssd1307fb.txt +++ b/Documentation/devicetree/bindings/display/ssd1307fb.txt @@ -36,7 +36,6 @@ ssd1307: oled@3c { reg = <0x3c>; pwms = <&pwm 4 3000>; reset-gpios = <&gpio2 7>; - reset-active-low; }; ssd1306: oled@3c { @@ -44,7 +43,6 @@ ssd1306: oled@3c { reg = <0x3c>; pwms = <&pwm 4 3000>; reset-gpios = <&gpio2 7>; - reset-active-low; solomon,com-lrremap; solomon,com-invdir; solomon,com-offset = <32>; -- cgit v1.2.3 From 1ace9f00eca6d1e40aea01489a8553f0afb362a0 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Fri, 12 Oct 2018 14:39:26 -0700 Subject: scsi: dt-bindings: ufs: Fix the compatible string definition If you look at the bindings for the UFS Host Controller it says: - compatible: must contain "jedec,ufs-1.1" or "jedec,ufs-2.0", may also list one or more of the following: "qcom,msm8994-ufshc" "qcom,msm8996-ufshc" "qcom,ufshc" My reading of that is that it's fine to just have either of these: 1. "qcom,msm8996-ufshc", "jedec,ufs-2.0" 2. "qcom,ufshc", "jedec,ufs-2.0" As far as I can tell neither of the above is actually a good idea. For #1 it turns out that the driver currently only keys off the compatible string "qcom,ufshc" so it won't actually probe. For #2 the driver won't probe but it's not a good idea to keep the SoC name out of the compatible string. Let's update the compatible string to make it really explicit. We'll include a nod to the existing driver and the old binding and say that we should always include the "qcom,ufshc" string in addition to the SoC compatible string. While we're at it we'll also include another example SoC known to have UFS: sdm845. Fixes: 47555a5c8a11 ("scsi: ufs: make the UFS variant a platform device") Signed-off-by: Douglas Anderson Reviewed-by: Vivek Gautam Reviewed-by: Rob Herring Signed-off-by: Martin K. Petersen --- Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index 8cf59452c675..5111e9130bc3 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -4,11 +4,14 @@ UFSHC nodes are defined to describe on-chip UFS host controllers. Each UFS controller instance should have its own node. Required properties: -- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0", may - also list one or more of the following: - "qcom,msm8994-ufshc" - "qcom,msm8996-ufshc" - "qcom,ufshc" +- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0" + + For Qualcomm SoCs must contain, as below, an + SoC-specific compatible along with "qcom,ufshc" and + the appropriate jedec string: + "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0" + "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0" + "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0" - interrupts : - reg : -- cgit v1.2.3 From 83ef97d1d35c36bec37af6dea51858809c2af527 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 6 Feb 2019 18:56:08 +0100 Subject: net/macb: bindings doc/trivial: fix documentation for sama5d3 10/100 interface This removes a line left while adding the correct compatibility string for sama5d3 10/100 interface. Now use the "atmel,sama5d3-macb" string. Signed-off-by: Nicolas Ferre Reviewed-by: Rob Herring Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/macb.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 3e17ac1d5d58..f5c414b10e27 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -3,8 +3,7 @@ Required properties: - compatible: Should be "cdns,[-]{macb|gem}" Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC. - Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs or the 10/100Mbit IP - available on sama5d3 SoCs. + Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs. Use "cdns,np4-macb" for NP4 SoC devices. Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on -- cgit v1.2.3 From 4973a1276ca89c3f1a1fd32b4c955144e04afd5d Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 6 Feb 2019 18:56:09 +0100 Subject: net/macb: bindings doc: add sam9x60 binding Add the compatibility sting documentation for sam9x60 10/100 interface. Signed-off-by: Nicolas Ferre Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/macb.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index f5c414b10e27..174f292d8a3e 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Should be "cdns,[-]{macb|gem}" Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC. Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs. + Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC. Use "cdns,np4-macb" for NP4 SoC devices. Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on -- cgit v1.2.3 From 9c93da46f9c36ee37e363ea8f6e257bb4ef90965 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 25 Jan 2019 21:59:42 +0530 Subject: dt-bindings: arm: Document Bitmain BM1880 SoC Document Bitmain BM1880 SoC from Bitmain Technologies Ltd along with the Sophon Edge board. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Acked-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/bitmain.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bitmain.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/bitmain.yaml b/Documentation/devicetree/bindings/arm/bitmain.yaml new file mode 100644 index 000000000000..0efdb4ac028e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bitmain.yaml @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bitmain.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bitmain platform device tree bindings + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + items: + - enum: + - bitmain,sophon-edge + - const: bitmain,bm1880 +... -- cgit v1.2.3 From 015f80fffc3267fcac07761bea220eb780fbcb61 Mon Sep 17 00:00:00 2001 From: Martin Kelly Date: Sat, 2 Feb 2019 13:55:58 -0800 Subject: dt-bindings: fix incorrect bmi160 IRQ note The bmi160 bindings say that the BMI160 requires level-triggered, active-low interrupts, but it actually supports all interrupt types, so fix the note to reflect that. Reviewed-by: Rob Herring Signed-off-by: Martin Kelly Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/imu/bmi160.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/imu/bmi160.txt b/Documentation/devicetree/bindings/iio/imu/bmi160.txt index 0c1c105fb503..1aec19997fb5 100644 --- a/Documentation/devicetree/bindings/iio/imu/bmi160.txt +++ b/Documentation/devicetree/bindings/iio/imu/bmi160.txt @@ -9,7 +9,7 @@ Required properties: - spi-max-frequency : set maximum clock frequency (only for SPI) Optional properties: - - interrupts : interrupt mapping for IRQ, must be IRQ_TYPE_LEVEL_LOW + - interrupts : interrupt mapping for IRQ - interrupt-names : set to "INT1" if INT1 pin should be used as interrupt input, set to "INT2" if INT2 pin should be used instead @@ -20,7 +20,7 @@ bmi160@68 { reg = <0x68>; interrupt-parent = <&gpio4>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; interrupt-names = "INT1"; }; -- cgit v1.2.3 From b7905e4c5731636a2148039288bdc77599c14d6a Mon Sep 17 00:00:00 2001 From: Martin Kelly Date: Sat, 2 Feb 2019 13:55:59 -0800 Subject: dt-bindings: bmi160 document open-drain property We have added an optional boolean property for configuring a BMI160 interrupt pin as open-drain, as opposed to the default push-pull, so document this. Signed-off-by: Martin Kelly Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/imu/bmi160.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/imu/bmi160.txt b/Documentation/devicetree/bindings/iio/imu/bmi160.txt index 1aec19997fb5..900c169de00f 100644 --- a/Documentation/devicetree/bindings/iio/imu/bmi160.txt +++ b/Documentation/devicetree/bindings/iio/imu/bmi160.txt @@ -12,6 +12,8 @@ Optional properties: - interrupts : interrupt mapping for IRQ - interrupt-names : set to "INT1" if INT1 pin should be used as interrupt input, set to "INT2" if INT2 pin should be used instead + - drive-open-drain : set if the specified interrupt pin should be configured as + open drain. If not set, defaults to push-pull. Examples: -- cgit v1.2.3 From 86117ba3f9b37de5e9a6adcdae14556f63661d04 Mon Sep 17 00:00:00 2001 From: Artur Rojek Date: Mon, 4 Feb 2019 01:15:12 +0100 Subject: dt-bindings: iio/adc: Add docs for Ingenic JZ47xx SoCs ADC. Add documentation for the ADC controller on JZ47xx SoCs, used by the ingenic-adc driver. Signed-off-by: Artur Rojek Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/ingenic,adc.txt | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/ingenic,adc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/ingenic,adc.txt b/Documentation/devicetree/bindings/iio/adc/ingenic,adc.txt new file mode 100644 index 000000000000..f01159f20d87 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ingenic,adc.txt @@ -0,0 +1,48 @@ +* Ingenic JZ47xx ADC controller IIO bindings + +Required properties: + +- compatible: Should be one of: + * ingenic,jz4725b-adc + * ingenic,jz4740-adc +- reg: ADC controller registers location and length. +- clocks: phandle to the SoC's ADC clock. +- clock-names: Must be set to "adc". +- #io-channel-cells: Must be set to <1> to indicate channels are selected + by index. + +ADC clients must use the format described in iio-bindings.txt, giving +a phandle and IIO specifier pair ("io-channels") to the ADC controller. + +Example: + +#include + +adc: adc@10070000 { + compatible = "ingenic,jz4740-adc"; + #io-channel-cells = <1>; + + reg = <0x10070000 0x30>; + + clocks = <&cgu JZ4740_CLK_ADC>; + clock-names = "adc"; + + interrupt-parent = <&intc>; + interrupts = <18>; +}; + +adc-keys { + ... + compatible = "adc-keys"; + io-channels = <&adc INGENIC_ADC_AUX>; + io-channel-names = "buttons"; + ... +}; + +battery { + ... + compatible = "ingenic,jz4740-battery"; + io-channels = <&adc INGENIC_ADC_BATTERY>; + io-channel-names = "battery"; + ... +}; -- cgit v1.2.3 From b73c2c1a1cde38f94304ef58d542a03a5066c906 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Mon, 4 Feb 2019 13:48:33 +0100 Subject: iio:dac:dac7612: device tree bindings Bindings for dac7612. Cc: devicetree@vger.kernel.org Signed-off-by: Ricardo Ribalda Delgado Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/dac/ti,dac7612.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/dac/ti,dac7612.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/dac/ti,dac7612.txt b/Documentation/devicetree/bindings/iio/dac/ti,dac7612.txt new file mode 100644 index 000000000000..639c94ed83e9 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/ti,dac7612.txt @@ -0,0 +1,28 @@ +* Texas Instruments Dual, 12-Bit Serial Input Digital-to-Analog Converter + +The DAC7612 is a dual, 12-bit digital-to-analog converter (DAC) with guaranteed +12-bit monotonicity performance over the industrial temperature range. +Is is programmable through an SPI interface. + +The internal DACs are loaded when the LOADDACS pin is pulled down. + +http://www.ti.com/lit/ds/sbas106/sbas106.pdf + +Required Properties: +- compatible: Should be one of: + "ti,dac7612" + "ti,dac7612u" + "ti,dac7612ub" +- reg: Definition as per Documentation/devicetree/bindings/spi/spi-bus.txt + +Optional Properties: +- ti,loaddacs-gpios: GPIO descriptor for the LOADDACS pin. +- spi-*: Definition as per Documentation/devicetree/bindings/spi/spi-bus.txt + +Example: + + dac@1 { + compatible = "ti,dac7612"; + reg = <0x1>; + ti,loaddacs-gpios = <&msmgpio 25 GPIO_ACTIVE_LOW>; + }; -- cgit v1.2.3 From 208b920b9028e3f89e1ae436d05c350f1cad6573 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 8 Feb 2019 17:09:40 +0100 Subject: dt-bindings: iio: adc: move lpc32xx-adc out of staging The drivers has been moved out since 0097e20e7771 ("staging:iio:adc:lpc32xx Move out of staging.") in v4.10, so let's align the binding documentation. Signed-off-by: Gregory CLEMENT Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/lpc32xx-adc.txt | 16 ++++++++++++++++ .../devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt | 16 ---------------- 2 files changed, 16 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/adc/lpc32xx-adc.txt delete mode 100644 Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/lpc32xx-adc.txt b/Documentation/devicetree/bindings/iio/adc/lpc32xx-adc.txt new file mode 100644 index 000000000000..b3629d3a9adf --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/lpc32xx-adc.txt @@ -0,0 +1,16 @@ +* NXP LPC32xx SoC ADC controller + +Required properties: +- compatible: must be "nxp,lpc3220-adc" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: The ADC interrupt + +Example: + + adc@40048000 { + compatible = "nxp,lpc3220-adc"; + reg = <0x40048000 0x1000>; + interrupt-parent = <&mic>; + interrupts = <39 0>; + }; diff --git a/Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt b/Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt deleted file mode 100644 index b3629d3a9adf..000000000000 --- a/Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt +++ /dev/null @@ -1,16 +0,0 @@ -* NXP LPC32xx SoC ADC controller - -Required properties: -- compatible: must be "nxp,lpc3220-adc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The ADC interrupt - -Example: - - adc@40048000 { - compatible = "nxp,lpc3220-adc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&mic>; - interrupts = <39 0>; - }; -- cgit v1.2.3 From 4ed754de2d66084d4a7785f565d7c42ad89a3ea9 Mon Sep 17 00:00:00 2001 From: Vijai Kumar K Date: Wed, 23 Jan 2019 18:16:56 +0530 Subject: extcon: Add support for ptn5150 extcon driver PTN5150 is a small thin low power CC (Configurationn Channel) Logic chip supporting the USB Type-C connector application with CC control logic detection and indication functions. Signed-off-by: Vijai Kumar K [cw00.choi: Fix bulid dependency and clean-up code] Signed-off-by: Chanwoo Choi --- .../devicetree/bindings/extcon/extcon-ptn5150.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/extcon/extcon-ptn5150.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/extcon/extcon-ptn5150.txt b/Documentation/devicetree/bindings/extcon/extcon-ptn5150.txt new file mode 100644 index 000000000000..936fbdf12815 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/extcon-ptn5150.txt @@ -0,0 +1,27 @@ +* PTN5150 CC (Configuration Channel) Logic device + +PTN5150 is a small thin low power CC logic chip supporting the USB Type-C +connector application with CC control logic detection and indication functions. +It is interfaced to the host controller using an I2C interface. + +Required properties: +- compatible: should be "nxp,ptn5150" +- reg: specifies the I2C slave address of the device +- int-gpio: should contain a phandle and GPIO specifier for the GPIO pin + connected to the PTN5150's INTB pin. +- vbus-gpio: should contain a phandle and GPIO specifier for the GPIO pin which + is used to control VBUS. +- pinctrl-names : a pinctrl state named "default" must be defined. +- pinctrl-0 : phandle referencing pin configuration of interrupt and vbus + control. + +Example: + ptn5150@1d { + compatible = "nxp,ptn5150"; + reg = <0x1d>; + int-gpio = <&msmgpio 78 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&msmgpio 148 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ptn5150_default>; + status = "okay"; + }; -- cgit v1.2.3 From 1366e010ade86bcc8226fbdd9c0cb71cfd2aa173 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 9 Feb 2019 01:18:12 +0100 Subject: dt-bindings: rtc: add device-tree bindings for the Amlogic Meson RTC The 32-bit Amlogic Meson SoCs (Meson6, Meson8, Meson8b and Meson8m2) have a built-in RTC block. It has the following inputs: - an 32.768kHz crystal oscillator - an interrupt line - a reset line - 0.9V voltage input Signed-off-by: Ben Dooks [resurrected patches from Ben after 2 years] Signed-off-by: Martin Blumenstingl Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/rtc/rtc-meson.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/rtc-meson.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc-meson.txt b/Documentation/devicetree/bindings/rtc/rtc-meson.txt new file mode 100644 index 000000000000..e921fe66a362 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/rtc-meson.txt @@ -0,0 +1,35 @@ +* Amlogic Meson6, Meson8, Meson8b and Meson8m2 RTC + +Required properties: +- compatible: should be one of the following describing the hardware: + * "amlogic,meson6-rtc" + * "amlogic,meson8-rtc" + * "amlogic,meson8b-rtc" + * "amlogic,meson8m2-rtc" + +- reg: physical register space for the controller's memory mapped registers. +- interrupts: the interrupt line of the RTC block. +- clocks: reference to the external 32.768kHz crystal oscillator. +- vdd-supply: reference to the power supply of the RTC block. +- resets: reset controller reference to allow reset of the controller + +Optional properties for the battery-backed non-volatile memory: +- #address-cells: should be 1 to address the battery-backed non-volatile memory +- #size-cells: should be 1 to reference the battery-backed non-volatile memory + +Optional child nodes: +- see ../nvmem/nvmem.txt + +Example: + + rtc: rtc@740 { + compatible = "amlogic,meson6-rtc"; + reg = <0x740 0x14>; + interrupts = ; + clocks = <&rtc32k_xtal>; + vdd-supply = <&rtc_vdd>; + resets = <&reset RESET_RTC>; + + #address-cells = <1>; + #size-cells = <1>; + }; -- cgit v1.2.3 From c184e4ad61e14421f268cbb47603523d6517a646 Mon Sep 17 00:00:00 2001 From: Tomasz Duszynski Date: Sat, 9 Feb 2019 18:36:08 +0100 Subject: dt-bindings: add Plantower to the vendor prefixes Add Plantower to the vendor prefixes. Signed-off-by: Tomasz Duszynski Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..42816baeb381 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -304,6 +304,7 @@ phytec PHYTEC Messtechnik GmbH picochip Picochip Ltd pine64 Pine64 pixcir PIXCIR MICROELECTRONICS Co., Ltd +plantower Plantower Co., Ltd plathome Plat'Home Co., Ltd. plda PLDA plx Broadcom Corporation (formerly PLX Technology) -- cgit v1.2.3 From 4a428cb2d7fb3dfac36fd10f5b51f0d6598e512d Mon Sep 17 00:00:00 2001 From: Tomasz Duszynski Date: Sat, 9 Feb 2019 18:36:09 +0100 Subject: dt-bindings: iio: chemical: pms7003: add device tree support Add device tree support for Plantower PMS7003 particulate matter sensor. Signed-off-by: Tomasz Duszynski Signed-off-by: Jonathan Cameron --- .../bindings/iio/chemical/plantower,pms7003.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.txt b/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.txt new file mode 100644 index 000000000000..7b5f06f324c8 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.txt @@ -0,0 +1,20 @@ +* Plantower PMS7003 particulate matter sensor + +Required properties: +- compatible: must be "plantower,pms7003" +- vcc-supply: phandle to the regulator that provides power to the sensor + +Optional properties: +- plantower,set-gpios: phandle to the GPIO connected to the SET line +- reset-gpios: phandle to the GPIO connected to the RESET line + +Refer to serial/slave-device.txt for generic serial attached device bindings. + +Example: + +&uart0 { + air-pollution-sensor { + compatible = "plantower,pms7003"; + vcc-supply = <®_vcc5v0>; + }; +}; -- cgit v1.2.3 From 66d388ff4a73d2f930fa3c9d5ade259522769ea5 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Sun, 10 Feb 2019 22:47:49 +0200 Subject: dt-binding: iio: remove rst node from NPCM ADC document Remove NPCM7xx rst node for preparing the NPCM ADC document to describe ADC reset binding. Signed-off-by: Tomer Maimon Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt index 1b8132cd9060..eb939fe77836 100644 --- a/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt @@ -14,11 +14,6 @@ Optional properties: vref-supply is not added the ADC will use internal voltage reference. -Required Node in the NPCM7xx BMC: -An additional register is present in the NPCM7xx SOC which is -assumed to be in the same device tree, with and marked as -compatible with "nuvoton,npcm750-rst". - Example: adc: adc@f000c000 { @@ -27,9 +22,3 @@ adc: adc@f000c000 { interrupts = ; clocks = <&clk NPCM7XX_CLK_ADC>; }; - -rst: rst@f0801000 { - compatible = "nuvoton,npcm750-rst", "syscon", - "simple-mfd"; - reg = <0xf0801000 0x6C>; -}; -- cgit v1.2.3 From d28ffb42f4fe470f0e172d17a235d263ef6a4013 Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Fri, 8 Feb 2019 23:13:16 +0100 Subject: dt-bindings: phy-qcom-qmp: Add qcom,msm8998-qmp-ufs-phy Add compatible string for QMP UFS phy on msm8998. Signed-off-by: Marc Gonzalez Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index 4ff26dbf4310..5d181fc3cc18 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -10,6 +10,7 @@ Required properties: "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998, + "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998, "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845, "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845, "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845. @@ -45,6 +46,8 @@ Required properties: "aux", "cfg_ahb", "ref". For "qcom,msm8998-qmp-usb3-phy" must contain: "aux", "cfg_ahb", "ref". + For "qcom,msm8998-qmp-ufs-phy" must contain: + "ref", "ref_aux". For "qcom,sdm845-qmp-usb3-phy" must contain: "aux", "cfg_ahb", "ref", "com_aux". For "qcom,sdm845-qmp-usb3-uni-phy" must contain: @@ -66,6 +69,7 @@ Required properties: "phy", "common". For "qcom,msm8998-qmp-usb3-phy" must contain "phy", "common". + For "qcom,msm8998-qmp-ufs-phy": no resets are listed. For "qcom,sdm845-qmp-usb3-phy" must contain: "phy", "common". For "qcom,sdm845-qmp-usb3-uni-phy" must contain: -- cgit v1.2.3 From ecd927ab7c8d513f1e7ebbc32d27b2919208bf4a Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Mon, 11 Feb 2019 11:14:47 -0600 Subject: Documentation: dt: Add binding info for jz4740-musb driver This commit adds documentation for the device-tree bindings of the jz4740-musb driver, which provides support for the USB gadget mode of the JZ4740 and similar SoCs from Ingenic. Signed-off-by: Paul Cercueil Reviewed-by: Rob Herring Signed-off-by: Bin Liu Signed-off-by: Greg Kroah-Hartman --- .../bindings/usb/ingenic,jz4740-musb.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/ingenic,jz4740-musb.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/ingenic,jz4740-musb.txt b/Documentation/devicetree/bindings/usb/ingenic,jz4740-musb.txt new file mode 100644 index 000000000000..620355cee63f --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ingenic,jz4740-musb.txt @@ -0,0 +1,24 @@ +Ingenic JZ4740 MUSB driver + +Required properties: + +- compatible: Must be "ingenic,jz4740-musb" +- reg: Address range of the UDC register set +- interrupts: IRQ number related to the UDC hardware +- interrupt-names: must be "mc" +- clocks: phandle to the "udc" clock +- clock-names: must be "udc" + +Example: + +udc: usb@13040000 { + compatible = "ingenic,jz4740-musb"; + reg = <0x13040000 0x10000>; + + interrupt-parent = <&intc>; + interrupts = <24>; + interrupt-names = "mc"; + + clocks = <&cgu JZ4740_CLK_UDC>; + clock-names = "udc"; +}; -- cgit v1.2.3 From 36e738bdab536c0bdfa16e999fa66a3b9b776e5d Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 8 Feb 2019 17:11:23 +0000 Subject: misc: dt-bindings: Add Qualcomm Fastrpc bindings The FastRPC driver implements an IPC (Inter-Processor Communication) mechanism that allows for clients to transparently make remote method invocations across DSP and APPS boundaries. This enables developers to offload tasks to the DSP and free up the application processor for other tasks. Co-developed-by: Thierry Escande Signed-off-by: Thierry Escande Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/misc/qcom,fastrpc.txt | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/qcom,fastrpc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/misc/qcom,fastrpc.txt b/Documentation/devicetree/bindings/misc/qcom,fastrpc.txt new file mode 100644 index 000000000000..2a1827ab50d2 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/qcom,fastrpc.txt @@ -0,0 +1,78 @@ +Qualcomm Technologies, Inc. FastRPC Driver + +The FastRPC implements an IPC (Inter-Processor Communication) +mechanism that allows for clients to transparently make remote method +invocations across DSP and APPS boundaries. This enables developers +to offload tasks to the DSP and free up the application processor for +other tasks. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,fastrpc" + +- label + Usage: required + Value type: + Definition: should specify the dsp domain name this fastrpc + corresponds to. must be one of this: "adsp", "mdsp", "sdsp", "cdsp" + +- #address-cells + Usage: required + Value type: + Definition: Must be 1 + +- #size-cells + Usage: required + Value type: + Definition: Must be 0 + += COMPUTE BANKS +Each subnode of the Fastrpc represents compute context banks available +on the dsp. +- All Compute context banks MUST contain the following properties: + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,fastrpc-compute-cb" + +- reg + Usage: required + Value type: + Definition: Context Bank ID. + +- qcom,nsessions: + Usage: Optional + Value type: + Defination: A value indicating how many sessions can share this + context bank. Defaults to 1 when this property + is not specified. + +Example: + +adsp-pil { + compatible = "qcom,msm8996-adsp-pil"; + ... + smd-edge { + label = "lpass"; + fastrpc { + compatible = "qcom,fastrpc"; + qcom,smd-channels = "fastrpcsmd-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + }; + + cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + }; + ... + }; + }; +}; -- cgit v1.2.3 From d4ff6c9efa2e40fe3afc0eac5cf93086c6db962b Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Tue, 29 Jan 2019 12:38:19 -0800 Subject: dt-bindings: soc: Add ZynqMP PM bindings Add documentation to describe Xilinx ZynqMP power management bindings. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Reviewed-by: Rob Herring Signed-off-by: Michal Simek --- .../bindings/power/reset/xlnx,zynqmp-power.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt new file mode 100644 index 000000000000..d366f1eb623a --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt @@ -0,0 +1,25 @@ +-------------------------------------------------------------------- +Device Tree Bindings for the Xilinx Zynq MPSoC Power Management +-------------------------------------------------------------------- +The zynqmp-power node describes the power management configurations. +It will control remote suspend/shutdown interfaces. + +Required properties: + - compatible: Must contain: "xlnx,zynqmp-power" + - interrupts: Interrupt specifier + +------- +Example +------- + +firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + + zynqmp_power: zynqmp-power { + compatible = "xlnx,zynqmp-power"; + interrupts = <0 35 4>; + }; + }; +}; -- cgit v1.2.3 From 8fd27fb4cf76a64d4ea4814b358541477dc7a31e Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Fri, 1 Feb 2019 14:08:48 -0800 Subject: dt-bindings: power: Add ZynqMP power domain bindings Add documentation to describe ZynqMP power domain bindings. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Reviewed-by: Rob Herring Signed-off-by: Michal Simek --- .../bindings/power/xlnx,zynqmp-genpd.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt new file mode 100644 index 000000000000..8d1b8200ebd0 --- /dev/null +++ b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt @@ -0,0 +1,34 @@ +----------------------------------------------------------- +Device Tree Bindings for the Xilinx Zynq MPSoC PM domains +----------------------------------------------------------- +The binding for zynqmp-power-controller follow the common +generic PM domain binding[1]. + +[1] Documentation/devicetree/bindings/power/power_domain.txt + +== Zynq MPSoC Generic PM Domain Node == + +Required property: + - Below property should be in zynqmp-firmware node. + - #power-domain-cells: Number of cells in a PM domain specifier. Must be 1. + +Power domain ID indexes are mentioned in +include/dt-bindings/power/xlnx-zynqmp-power.h. + +------- +Example +------- + +firmware { + zynqmp_firmware: zynqmp-firmware { + ... + #power-domain-cells = <1>; + ... + }; +}; + +sata { + ... + power-domains = <&zynqmp_firmware 28>; + ... +}; -- cgit v1.2.3 From 97a6a2ddc2ea684fadd1021dd350c27d03113397 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 26 Jan 2019 19:30:11 -0200 Subject: dt-bindings: spi: imx: Add an entry for the i.MX8QM compatible Add an entry for the "fsl,imx8mq-ecspi" compatible to describe the ECSPI version present on i.MX8M. Signed-off-by: Fabio Estevam Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt index e3c48b20b1a6..2d3264140cc5 100644 --- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt @@ -10,6 +10,7 @@ Required properties: - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35 - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51 - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc + - "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8M - reg : Offset and length of the register set for the device - interrupts : Should contain CSPI/eCSPI interrupt - clocks : Clock specifiers for both ipg and per clocks. -- cgit v1.2.3 From 2843bf518579e9fa357ba58708c7cff96946d084 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Tue, 12 Feb 2019 12:24:00 +0800 Subject: dt-binding: ptp_qoriq: add little-endian support Specify "little-endian" property if the 1588 timer IP block is little-endian mode. The default endian mode is big-endian. Signed-off-by: Yangbo Lu Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/ptp/ptp-qoriq.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt b/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt index 8e7f8551d190..454c937076a2 100644 --- a/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt +++ b/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt @@ -19,6 +19,9 @@ Clock Properties: - fsl,max-adj Maximum frequency adjustment in parts per billion. - fsl,extts-fifo The presence of this property indicates hardware support for the external trigger stamp FIFO. + - little-endian The presence of this property indicates the 1588 timer + IP block is little-endian mode. The default endian mode + is big-endian. These properties set the operational parameters for the PTP clock. You must choose these carefully for the clock to work right. -- cgit v1.2.3 From b7e312dea1d8378b8f311ce9096759b5accb1939 Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Tue, 5 Feb 2019 00:17:39 +0000 Subject: dt-bindings: imx6q-pcie: Add description of imx7d pcie phy There is a separate PHY device with its own registers on imx7d. It's currently unused, but a PCIe erratum on imx7d will require it for the workaround. Signed-off-by: Trent Piepho Signed-off-by: Lorenzo Pieralisi Acked-by: Lucas Stach --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 920ca93870a8..954f435dca8c 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -54,6 +54,7 @@ Additional required properties for imx7d-pcie and imx8mq-pcie: - "pciephy" - "apps" - "turnoff" +- fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node. Example: @@ -80,3 +81,13 @@ Example: clocks = <&clks 144>, <&clks 206>, <&clks 189>; clock-names = "pcie", "pcie_bus", "pcie_phy"; }; + +* Freescale i.MX7d PCIe PHY + +This is the PHY associated with the IMX7d PCIe controller. It's used by the +PCI-e controller via the fsl,imx7d-pcie-phy phandle. + +Required properties: +- compatible: + - "fsl,imx7d-pcie-phy" +- reg: base address and length of the PCIe PHY controller -- cgit v1.2.3 From 103cda6a3b8d2c10d5f8cd7abad118e9db8f4776 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 12 Feb 2019 18:45:49 +0100 Subject: iio: adc: exynos-adc: Use proper number of channels for Exynos4x12 Exynos4212 and Exynos4412 have only four ADC channels so using "samsung,exynos-adc-v1" compatible (for eight channels ADCv1) on them is wrong. Add a new compatible for Exynos4x12. Signed-off-by: Krzysztof Kozlowski Cc: Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt index a10c1f89037d..e1fe02f3e3e9 100644 --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt @@ -11,11 +11,13 @@ New driver handles the following Required properties: - compatible: Must be "samsung,exynos-adc-v1" - for exynos4412/5250 controllers. + for Exynos5250 controllers. Must be "samsung,exynos-adc-v2" for future controllers. Must be "samsung,exynos3250-adc" for controllers compatible with ADC of Exynos3250. + Must be "samsung,exynos4212-adc" for + controllers compatible with ADC of Exynos4212 and Exynos4412. Must be "samsung,exynos7-adc" for the ADC in Exynos7 and compatibles Must be "samsung,s3c2410-adc" for -- cgit v1.2.3 From ede033e1e863c36729de25b57145fff287415830 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 7 Feb 2019 17:28:55 +0100 Subject: dt-bindings: gpio: document the new pull-up/pull-down flags This commit extends the flags that can be used in GPIO specifiers to indicate if a pull-up resistor or pull-down resistor should be enabled. While some pinctrl DT bindings already offer the capability of configuring pull-up/pull-down resistors at the pin level, a number of simple GPIO controllers don't have any pinmuxing capability, and therefore do not rely on the pinctrl DT bindings. Such simple GPIO controllers however sometimes allow to configure pull-up and pull-down resistors on a per-pin basis, and whether such resistors should be enabled or not is a highly board-specific HW characteristic. By using two additional bits of the GPIO flag specifier, we can easily allow the Device Tree to describe which GPIOs should have their pull-up or pull-down resistors enabled. Even though the two options are mutually exclusive, we still need two bits to encode at least three states: no pull-up/pull-down, pull-up, pull-down. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/gpio.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index f0ba154b5723..a8895d339bfe 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -67,6 +67,18 @@ Optional standard bitfield specifiers for the last cell: https://en.wikipedia.org/wiki/Open_collector - Bit 3: 0 means the output should be maintained during sleep/low-power mode 1 means the output state can be lost during sleep/low-power mode +- Bit 4: 0 means no pull-up resistor should be enabled + 1 means a pull-up resistor should be enabled + This setting only applies to hardware with a simple on/off + control for pull-up configuration. If the hardware has more + elaborate pull-up configuration, it should be represented + using a pin control binding. +- Bit 5: 0 means no pull-down resistor should be enabled + 1 means a pull-down resistor should be enabled + This setting only applies to hardware with a simple on/off + control for pull-down configuration. If the hardware has more + elaborate pull-down configuration, it should be represented + using a pin control binding. 1.1) GPIO specifier best practices ---------------------------------- -- cgit v1.2.3 From be3d960b0aeb97438a044d8d3ce75393d198c020 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 12 Feb 2019 17:28:58 +0100 Subject: dt-bindings: clk: add G12A AO Clock and Reset Bindings Add bindings for the Amlogic G12A AO Clock and Reset controllers. Signed-off-by: Neil Armstrong Acked-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190212162859.20743-2-narmstrong@baylibre.com --- Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt index 79511d7bb321..c41f0be5d438 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt @@ -10,6 +10,7 @@ Required Properties: - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" - GXM (S912) : "amlogic,meson-gxm-aoclkc" - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" + - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc" followed by the common "amlogic,meson-gx-aoclkc" - clocks: list of clock phandle, one for each entry clock-names. - clock-names: should contain the following: -- cgit v1.2.3 From 6dcb144f7da634e4a0f8837e5076ef48e4d6ac12 Mon Sep 17 00:00:00 2001 From: Lanqing Liu Date: Wed, 13 Feb 2019 15:36:10 +0800 Subject: dt-bindings: spi: Add the DMA properties for the SPI dma mode Add the DMA properties for the SPI dma mode. Signed-off-by: Lanqing Liu Signed-off-by: Baolin Wang Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-sprd.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-sprd.txt b/Documentation/devicetree/bindings/spi/spi-sprd.txt index bad211a19da4..3c7eacce0ee3 100644 --- a/Documentation/devicetree/bindings/spi/spi-sprd.txt +++ b/Documentation/devicetree/bindings/spi/spi-sprd.txt @@ -14,6 +14,11 @@ Required properties: address on the SPI bus. Should be set to 1. - #size-cells: Should be set to 0. +Optional properties: +dma-names: Should contain names of the SPI used DMA channel. +dmas: Should contain DMA channels and DMA slave ids which the SPI used + sorted in the same order as the dma-names property. + Example: spi0: spi@70a00000{ compatible = "sprd,sc9860-spi"; @@ -21,6 +26,8 @@ spi0: spi@70a00000{ interrupts = ; clock-names = "spi", "source","enable"; clocks = <&clk_spi0>, <&ext_26m>, <&clk_ap_apb_gates 5>; + dma-names = "rx_chn", "tx_chn"; + dmas = <&apdma 11 11>, <&apdma 12 12>; #address-cells = <1>; #size-cells = <0>; }; -- cgit v1.2.3 From 70b64604fef0fb6fbc3bf6fbd9cd90b73ab0dfa8 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 12 Feb 2019 14:08:08 +0530 Subject: dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence QSPI controller but supports Octal IO(x8 data lines) and Double Data Rate(DDR) mode. Add new compatible to support OSPI controller on TI's AM654 SoCs. Signed-off-by: Vignesh R Reviewed-by: Rob Herring Signed-off-by: Boris Brezillon --- Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt index bb2075df9b38..4345c3a6f530 100644 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt @@ -4,6 +4,7 @@ Required properties: - compatible : should be one of the following: Generic default - "cdns,qspi-nor". For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". + For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the -- cgit v1.2.3 From a2b956463764da57ba4f54d0be7d742b50c2040f Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 21 Dec 2018 18:54:00 -0600 Subject: dt-bindings: arm: l2x0: Convert L2 cache to json-schema Convert the ARM L2 cache controller binding to json-schema. Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/l2c2x0.txt | 114 ---------- Documentation/devicetree/bindings/arm/l2c2x0.yaml | 248 ++++++++++++++++++++++ 2 files changed, 248 insertions(+), 114 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt deleted file mode 100644 index fbe6cb21f4cf..000000000000 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ /dev/null @@ -1,114 +0,0 @@ -* ARM L2 Cache Controller - -ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/ -PL310 and variants) based level 2 cache controller. All these various implementations -of the L2 cache controller have compatible programming models (Note 1). -Some of the properties that are just prefixed "cache-*" are taken from section -3.7.3 of the Devicetree Specification which can be found at: -https://www.devicetree.org/specifications/ - -The ARM L2 cache representation in the device tree should be done as follows: - -Required properties: - -- compatible : should be one of: - "arm,pl310-cache" - "arm,l220-cache" - "arm,l210-cache" - "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache" - "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an - offset needs to be added to the address before passing down to the L2 - cache controller - "marvell,aurora-system-cache": Marvell Controller designed to be - compatible with the ARM one, with system cache mode (meaning - maintenance operations on L1 are broadcasted to the L2 and L2 - performs the same operation). - "marvell,aurora-outer-cache": Marvell Controller designed to be - compatible with the ARM one with outer cache mode. - "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible - with arm,pl310-cache controller. -- cache-unified : Specifies the cache is a unified cache. -- cache-level : Should be set to 2 for a level 2 cache. -- reg : Physical base address and size of cache controller's memory mapped - registers. - -Optional properties: - -- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of - read, write and setup latencies. Minimum valid values are 1. Controllers - without setup latency control should use a value of 0. -- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of - read, write and setup latencies. Controllers without setup latency control - should use 0. Controllers without separate read and write Tag RAM latency - values should only use the first cell. -- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. -- arm,filter-ranges : Starting address and length of window to - filter. Addresses in the filter window are directed to the M1 port. Other - addresses will go to the M0 port. -- arm,io-coherent : indicates that the system is operating in an hardware - I/O coherent mode. Valid only when the arm,pl310-cache compatible - string is used. -- interrupts : 1 combined interrupt. -- cache-size : specifies the size in bytes of the cache -- cache-sets : specifies the number of associativity sets of the cache -- cache-block-size : specifies the size in bytes of a cache block -- cache-line-size : specifies the size in bytes of a line in the cache, - if this is not specified, the line size is assumed to be equal to the - cache block size -- cache-id-part: cache id part number to be used if it is not present - on hardware -- wt-override: If present then L2 is forced to Write through mode -- arm,double-linefill : Override double linefill enable setting. Enable if - non-zero, disable if zero. -- arm,double-linefill-incr : Override double linefill on INCR read. Enable - if non-zero, disable if zero. -- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable - if non-zero, disable if zero. -- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero, - disable if zero. -- arm,prefetch-offset : Override prefetch offset value. Valid values are - 0-7, 15, 23, and 31. -- arm,shared-override : The default behavior of the L220 or PL310 cache - controllers with respect to the shareable attribute is to transform "normal - memory non-cacheable transactions" into "cacheable no allocate" (for reads) - or "write through no write allocate" (for writes). - On systems where this may cause DMA buffer corruption, this property must be - specified to indicate that such transforms are precluded. -- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310). -- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310). -- arm,outer-sync-disable : disable the outer sync operation on the L2 cache. - Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that - will randomly hang unless outer sync operations are disabled. -- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1> - (forcibly enable), property absent (retain settings set by firmware) -- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable), - <1> (forcibly enable), property absent (retain settings set by - firmware) -- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly - disable), <1> (forcibly enable), property absent (OS specific behavior, - preferably retain firmware settings) -- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable), - <1> (forcibly enable), property absent (OS specific behavior, - preferably retain firmware settings) -- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310) -- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero - write (PL310) - -Example: - -L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfff12000 0x1000>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <2 2 2>; - arm,filter-ranges = <0x80000000 0x8000000>; - cache-unified; - cache-level = <2>; - interrupts = <45>; -}; - -Note 1: The description in this document doesn't apply to integrated L2 - cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These - integrated L2 controllers are assumed to be all preconfigured by - early secure boot code. Thus no need to deal with their configuration - in the kernel at all. diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml new file mode 100644 index 000000000000..bfc5c185561c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/l2c2x0.yaml @@ -0,0 +1,248 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/l2c2x0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM L2 Cache Controller + +maintainers: + - Rob Herring + +description: |+ + ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/ + PL220/PL310 and variants) based level 2 cache controller. All these various + implementations of the L2 cache controller have compatible programming + models (Note 1). Some of the properties that are just prefixed "cache-*" are + taken from section 3.7.3 of the Devicetree Specification which can be found + at: + https://www.devicetree.org/specifications/ + + Note 1: The description in this document doesn't apply to integrated L2 + cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These + integrated L2 controllers are assumed to be all preconfigured by + early secure boot code. Thus no need to deal with their configuration + in the kernel at all. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +properties: + compatible: + enum: + - arm,pl310-cache + - arm,l220-cache + - arm,l210-cache + # DEPRECATED by "brcm,bcm11351-a2-pl310-cache" + - bcm,bcm11351-a2-pl310-cache + # For Broadcom bcm11351 chipset where an + # offset needs to be added to the address before passing down to the L2 + # cache controller + - brcm,bcm11351-a2-pl310-cache + # Marvell Controller designed to be + # compatible with the ARM one, with system cache mode (meaning + # maintenance operations on L1 are broadcasted to the L2 and L2 + # performs the same operation). + - marvell,aurora-system-cache + # Marvell Controller designed to be + # compatible with the ARM one with outer cache mode. + - marvell,aurora-outer-cache + # Marvell Tauros3 cache controller, compatible + # with arm,pl310-cache controller. + - marvell,tauros3-cache + + cache-level: + const: 2 + + cache-unified: true + cache-size: true + cache-sets: true + cache-block-size: true + cache-line-size: true + + reg: + maxItems: 1 + + arm,data-latency: + description: Cycles of latency for Data RAM accesses. Specifies 3 cells of + read, write and setup latencies. Minimum valid values are 1. Controllers + without setup latency control should use a value of 0. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - minItems: 2 + maxItems: 3 + items: + minimum: 0 + maximum: 8 + + arm,tag-latency: + description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of + read, write and setup latencies. Controllers without setup latency control + should use 0. Controllers without separate read and write Tag RAM latency + values should only use the first cell. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - minItems: 1 + maxItems: 3 + items: + minimum: 0 + maximum: 8 + + arm,dirty-latency: + description: Cycles of latency for Dirty RAMs. This is a single cell. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 1 + maximum: 8 + + arm,filter-ranges: + description: Starting address and length of window to + filter. Addresses in the filter window are directed to the M1 port. Other + addresses will go to the M0 port. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + minItems: 2 + maxItems: 2 + + arm,io-coherent: + description: indicates that the system is operating in an hardware + I/O coherent mode. Valid only when the arm,pl310-cache compatible + string is used. + type: boolean + + interrupts: + # Either a single combined interrupt or up to 9 individual interrupts + minItems: 1 + maxItems: 9 + + cache-id-part: + description: cache id part number to be used if it is not present + on hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + wt-override: + description: If present then L2 is forced to Write through mode + type: boolean + + arm,double-linefill: + description: Override double linefill enable setting. Enable if + non-zero, disable if zero. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 0, 1 ] + + arm,double-linefill-incr: + description: Override double linefill on INCR read. Enable + if non-zero, disable if zero. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 0, 1 ] + + arm,double-linefill-wrap: + description: Override double linefill on WRAP read. Enable + if non-zero, disable if zero. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 0, 1 ] + + arm,prefetch-drop: + description: Override prefetch drop enable setting. Enable if non-zero, + disable if zero. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 0, 1 ] + + arm,prefetch-offset: + description: Override prefetch offset value. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31 ] + + arm,shared-override: + description: The default behavior of the L220 or PL310 cache + controllers with respect to the shareable attribute is to transform "normal + memory non-cacheable transactions" into "cacheable no allocate" (for reads) + or "write through no write allocate" (for writes). + On systems where this may cause DMA buffer corruption, this property must + be specified to indicate that such transforms are precluded. + type: boolean + + arm,parity-enable: + description: enable parity checking on the L2 cache (L220 or PL310). + type: boolean + + arm,parity-disable: + description: disable parity checking on the L2 cache (L220 or PL310). + type: boolean + + arm,outer-sync-disable: + description: disable the outer sync operation on the L2 cache. + Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that + will randomly hang unless outer sync operations are disabled. + type: boolean + + prefetch-data: + description: | + Data prefetch. Value: <0> (forcibly disable), <1> + (forcibly enable), property absent (retain settings set by firmware) + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 0, 1 ] + + prefetch-instr: + description: | + Instruction prefetch. Value: <0> (forcibly disable), + <1> (forcibly enable), property absent (retain settings set by + firmware) + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 0, 1 ] + + arm,dynamic-clock-gating: + description: | + L2 dynamic clock gating. Value: <0> (forcibly + disable), <1> (forcibly enable), property absent (OS specific behavior, + preferably retain firmware settings) + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 0, 1 ] + + arm,standby-mode: + description: L2 standby mode enable. Value <0> (forcibly disable), + <1> (forcibly enable), property absent (OS specific behavior, + preferably retain firmware settings) + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 0, 1 ] + + arm,early-bresp-disable: + description: Disable the CA9 optimization Early BRESP (PL310) + type: boolean + + arm,full-line-zero-disable: + description: Disable the CA9 optimization Full line of zero + write (PL310) + type: boolean + +required: + - compatible + - cache-unified + - reg + +additionalProperties: false + +examples: + - | + cache-controller@fff12000 { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <2 2 2>; + arm,filter-ranges = <0x80000000 0x8000000>; + cache-unified; + cache-level = <2>; + interrupts = <45>; + }; + +... -- cgit v1.2.3 From 66ed144f147a785fada14c53f06a25079b764043 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 19 Dec 2018 15:16:50 -0600 Subject: dt-bindings: interrupt-controller: Convert ARM GIC to json-schema Convert the ARM GIC binding document to DT schema format using json-schema. Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Signed-off-by: Rob Herring --- .../bindings/interrupt-controller/arm,gic.txt | 171 ---------------- .../bindings/interrupt-controller/arm,gic.yaml | 223 +++++++++++++++++++++ 2 files changed, 223 insertions(+), 171 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt deleted file mode 100644 index 2f3244648646..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +++ /dev/null @@ -1,171 +0,0 @@ -* ARM Generic Interrupt Controller - -ARM SMP cores are often associated with a GIC, providing per processor -interrupts (PPI), shared processor interrupts (SPI) and software -generated interrupts (SGI). - -Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. -Secondary GICs are cascaded into the upward interrupt controller and do not -have PPIs or SGIs. - -Main node required properties: - -- compatible : should be one of: - "arm,arm1176jzf-devchip-gic" - "arm,arm11mp-gic" - "arm,cortex-a15-gic" - "arm,cortex-a7-gic" - "arm,cortex-a9-gic" - "arm,eb11mp-gic" - "arm,gic-400" - "arm,pl390" - "arm,tc11mp-gic" - "brcm,brahma-b15-gic" - "nvidia,tegra210-agic" - "qcom,msm-8660-qgic" - "qcom,msm-qgic2" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 3. - - The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI - interrupts. - - The 2nd cell contains the interrupt number for the interrupt type. - SPI interrupts are in the range [0-987]. PPI interrupts are in the - range [0-15]. - - The 3rd cell is the flags, encoded as follows: - bits[3:0] trigger type and level flags. - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered (invalid for SPIs) - 4 = active high level-sensitive - 8 = active low level-sensitive (invalid for SPIs). - bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of - the 8 possible cpus attached to the GIC. A bit set to '1' indicated - the interrupt is wired to that CPU. Only valid for PPI interrupts. - Also note that the configurability of PPI interrupts is IMPLEMENTATION - DEFINED and as such not guaranteed to be present (most SoC available - in 2014 seem to ignore the setting of this flag and use the hardware - default value). - -- reg : Specifies base physical address(s) and size of the GIC registers. The - first region is the GIC distributor register base and size. The 2nd region is - the GIC cpu interface register base and size. - -Optional -- interrupts : Interrupt source of the parent interrupt controller on - secondary GICs, or VGIC maintenance interrupt on primary GIC (see - below). - -- cpu-offset : per-cpu offset within the distributor and cpu interface - regions, used when the GIC doesn't have banked registers. The offset is - cpu-offset * cpu-nr. - -- clocks : List of phandle and clock-specific pairs, one for each entry - in clock-names. -- clock-names : List of names for the GIC clock input(s). Valid clock names - depend on the GIC variant: - "ic_clk" (for "arm,arm11mp-gic") - "PERIPHCLKEN" (for "arm,cortex-a15-gic") - "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic") - "clk" (for "arm,gic-400" and "nvidia,tegra210") - "gclk" (for "arm,pl390") - -- power-domains : A phandle and PM domain specifier as defined by bindings of - the power controller specified by phandle, used when the GIC - is part of a Power or Clock Domain. - - -Example: - - intc: interrupt-controller@fff11000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0xfff11000 0x1000>, - <0xfff10100 0x100>; - }; - - -* GIC virtualization extensions (VGIC) - -For ARM cores that support the virtualization extensions, additional -properties must be described (they only exist if the GIC is the -primary interrupt controller). - -Required properties: - -- reg : Additional regions specifying the base physical address and - size of the VGIC registers. The first additional region is the GIC - virtual interface control register base and size. The 2nd additional - region is the GIC virtual cpu interface register base and size. - -- interrupts : VGIC maintenance interrupt. - -Example: - - interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c002000 0x2000>, - <0x2c004000 0x2000>, - <0x2c006000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - -* GICv2m extension for MSI/MSI-x support (Optional) - -Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). -This is enabled by specifying v2m sub-node(s). - -Required properties: - -- compatible : The value here should contain "arm,gic-v2m-frame". - -- msi-controller : Identifies the node as an MSI controller. - -- reg : GICv2m MSI interface register base and size - -Optional properties: - -- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect - value, this property should contain the SPI base of - the MSI frame, overriding the HW value. - -- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect - value, this property should contain the number of - SPIs assigned to the frame, overriding the HW value. - -Example: - - interrupt-controller@e1101000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - interrupt-controller; - interrupts = <1 8 0xf04>; - ranges = <0 0 0 0xe1100000 0 0x100000>; - reg = <0x0 0xe1110000 0 0x01000>, - <0x0 0xe112f000 0 0x02000>, - <0x0 0xe1140000 0 0x10000>, - <0x0 0xe1160000 0 0x10000>; - v2m0: v2m@8000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x80000 0 0x1000>; - }; - - .... - - v2mN: v2m@9000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x90000 0 0x1000>; - }; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml new file mode 100644 index 000000000000..758fbd7128e7 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml @@ -0,0 +1,223 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Generic Interrupt Controller v1 and v2 + +maintainers: + - Marc Zyngier + +description: |+ + ARM SMP cores are often associated with a GIC, providing per processor + interrupts (PPI), shared processor interrupts (SPI) and software + generated interrupts (SGI). + + Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. + Secondary GICs are cascaded into the upward interrupt controller and do not + have PPIs or SGIs. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - arm,arm11mp-gic + - arm,cortex-a15-gic + - arm,cortex-a7-gic + - arm,cortex-a5-gic + - arm,cortex-a9-gic + - arm,eb11mp-gic + - arm,gic-400 + - arm,pl390 + - arm,tc11mp-gic + - nvidia,tegra210-agic + - qcom,msm-8660-qgic + - qcom,msm-qgic2 + + - items: + - const: arm,arm1176jzf-devchip-gic + - const: arm,arm11mp-gic + + - items: + - const: brcm,brahma-b15-gic + - const: arm,cortex-a15-gic + + interrupt-controller: true + + "#address-cells": + enum: [ 0, 1 ] + "#size-cells": + const: 1 + + "#interrupt-cells": + const: 3 + description: | + The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI + interrupts. + + The 2nd cell contains the interrupt number for the interrupt type. + SPI interrupts are in the range [0-987]. PPI interrupts are in the + range [0-15]. + + The 3rd cell is the flags, encoded as follows: + bits[3:0] trigger type and level flags. + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered (invalid for SPIs) + 4 = active high level-sensitive + 8 = active low level-sensitive (invalid for SPIs). + bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of + the 8 possible cpus attached to the GIC. A bit set to '1' indicated + the interrupt is wired to that CPU. Only valid for PPI interrupts. + Also note that the configurability of PPI interrupts is IMPLEMENTATION + DEFINED and as such not guaranteed to be present (most SoC available + in 2014 seem to ignore the setting of this flag and use the hardware + default value). + + reg: + description: | + Specifies base physical address(s) and size of the GIC registers. The + first region is the GIC distributor register base and size. The 2nd region + is the GIC cpu interface register base and size. + + For GICv2 with virtualization extensions, additional regions are + required for specifying the base physical address and size of the VGIC + registers. The first additional region is the GIC virtual interface + control register base and size. The 2nd additional region is the GIC + virtual cpu interface register base and size. + minItems: 2 + maxItems: 4 + + interrupts: + description: Interrupt source of the parent interrupt controller on + secondary GICs, or VGIC maintenance interrupt on primary GIC (see + below). + maxItems: 1 + + cpu-offset: + description: per-cpu offset within the distributor and cpu interface + regions, used when the GIC doesn't have banked registers. The offset + is cpu-offset * cpu-nr. + $ref: /schemas/types.yaml#/definitions/uint32 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + description: List of names for the GIC clock input(s). Valid clock names + depend on the GIC variant. + oneOf: + - const: ic_clk # for "arm,arm11mp-gic" + - const: PERIPHCLKEN # for "arm,cortex-a15-gic" + - items: # for "arm,cortex-a9-gic" + - const: PERIPHCLK + - const: PERIPHCLKEN + - const: clk # for "arm,gic-400" and "nvidia,tegra210" + - const: gclk #for "arm,pl390" + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + +patternProperties: + "^v2m@[0-9a-f]+$": + description: | + * GICv2m extension for MSI/MSI-x support (Optional) + + Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). + This is enabled by specifying v2m sub-node(s). + + properties: + compatible: + const: arm,gic-v2m-frame + + msi-controller: true + + reg: + maxItems: 1 + description: GICv2m MSI interface register base and size + + arm,msi-base-spi: + description: When the MSI_TYPER register contains an incorrect value, + this property should contain the SPI base of the MSI frame, overriding + the HW value. + $ref: /schemas/types.yaml#/definitions/uint32 + + arm,msi-num-spis: + description: When the MSI_TYPER register contains an incorrect value, + this property should contain the number of SPIs assigned to the + frame, overriding the HW value. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - compatible + - msi-controller + - reg + + additionalProperties: false + +additionalProperties: false + +examples: + - | + // GICv1 + intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xfff11000 0x1000>, + <0xfff10100 0x100>; + }; + + - | + // GICv2 + interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x2c001000 0x1000>, + <0x2c002000 0x2000>, + <0x2c004000 0x2000>, + <0x2c006000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + - | + // GICv2m extension for MSI/MSI-x support + interrupt-controller@e1101000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + interrupts = <1 8 0xf04>; + ranges = <0 0 0 0xe1100000 0 0x100000>; + reg = <0x0 0xe1110000 0 0x01000>, + <0x0 0xe112f000 0 0x02000>, + <0x0 0xe1140000 0 0x10000>, + <0x0 0xe1160000 0 0x10000>; + + v2m0: v2m@8000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x80000 0 0x1000>; + }; + + //... + + v2mN: v2m@9000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x90000 0 0x1000>; + }; + }; +... -- cgit v1.2.3 From 36c79bc7ef792e8f5e0cc0eb012ad21a7981e908 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 19 Dec 2018 15:16:50 -0600 Subject: dt-bindings: interrupt-controller: Convert ARM GICv3 to json-schema Convert the ARM GICv3 binding document to DT schema format using json-schema. Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Signed-off-by: Rob Herring --- .../bindings/interrupt-controller/arm,gic-v3.txt | 175 ------------- .../bindings/interrupt-controller/arm,gic-v3.yaml | 279 +++++++++++++++++++++ 2 files changed, 279 insertions(+), 175 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt deleted file mode 100644 index b83bb8249074..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ /dev/null @@ -1,175 +0,0 @@ -* ARM Generic Interrupt Controller, version 3 - -AArch64 SMP cores are often associated with a GICv3, providing Private -Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI), -Software Generated Interrupts (SGI), and Locality-specific Peripheral -Interrupts (LPI). - -Main node required properties: - -- compatible : should at least contain "arm,gic-v3" or either - "qcom,msm8996-gic-v3", "arm,gic-v3" for msm8996 SoCs - to address SoC specific bugs/quirks -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. Must be a single cell with a value of at least 3. - If the system requires describing PPI affinity, then the value must - be at least 4. - - The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI - interrupts. Other values are reserved for future use. - - The 2nd cell contains the interrupt number for the interrupt type. - SPI interrupts are in the range [0-987]. PPI interrupts are in the - range [0-15]. - - The 3rd cell is the flags, encoded as follows: - bits[3:0] trigger type and level flags. - 1 = edge triggered - 4 = level triggered - - The 4th cell is a phandle to a node describing a set of CPUs this - interrupt is affine to. The interrupt must be a PPI, and the node - pointed must be a subnode of the "ppi-partitions" subnode. For - interrupt types other than PPI or PPIs that are not partitionned, - this cell must be zero. See the "ppi-partitions" node description - below. - - Cells 5 and beyond are reserved for future use and must have a value - of 0 if present. - -- reg : Specifies base physical address(s) and size of the GIC - registers, in the following order: - - GIC Distributor interface (GICD) - - GIC Redistributors (GICR), one range per redistributor region - - GIC CPU interface (GICC) - - GIC Hypervisor interface (GICH) - - GIC Virtual CPU interface (GICV) - - GICC, GICH and GICV are optional. - -- interrupts : Interrupt source of the VGIC maintenance interrupt. - -Optional - -- redistributor-stride : If using padding pages, specifies the stride - of consecutive redistributors. Must be a multiple of 64kB. - -- #redistributor-regions: The number of independent contiguous regions - occupied by the redistributors. Required if more than one such - region is present. - -- msi-controller: Boolean property. Identifies the node as an MSI - controller. Only present if the Message Based Interrupt - functionnality is being exposed by the HW, and the mbi-ranges - property present. - -- mbi-ranges: A list of pairs , where "intid" is the first - SPI of a range that can be used an MBI, and "span" the size of that - range. Multiple ranges can be provided. Requires "msi-controller" to - be set. - -- mbi-alias: Address property. Base address of an alias of the GICD - region containing only the {SET,CLR}SPI registers to be used if - isolation is required, and if supported by the HW. - -Sub-nodes: - -PPI affinity can be expressed as a single "ppi-partitions" node, -containing a set of sub-nodes, each with the following property: -- affinity: Should be a list of phandles to CPU nodes (as described in -Documentation/devicetree/bindings/arm/cpus.txt). - -GICv3 has one or more Interrupt Translation Services (ITS) that are -used to route Message Signalled Interrupts (MSI) to the CPUs. - -These nodes must have the following properties: -- compatible : Should at least contain "arm,gic-v3-its". -- msi-controller : Boolean property. Identifies the node as an MSI controller -- #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device - which will generate the MSI. -- reg: Specifies the base physical address and size of the ITS - registers. - -Optional: -- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated - address and size of the pre-ITS window. - -The main GIC node must contain the appropriate #address-cells, -#size-cells and ranges properties for the reg property of all ITS -nodes. - -Examples: - - gic: interrupt-controller@2cf00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x0 0x2f000000 0 0x10000>, // GICD - <0x0 0x2f100000 0 0x200000>, // GICR - <0x0 0x2c000000 0 0x2000>, // GICC - <0x0 0x2c010000 0 0x2000>, // GICH - <0x0 0x2c020000 0 0x2000>; // GICV - interrupts = <1 9 4>; - - msi-controller; - mbi-ranges = <256 128>; - - gic-its@2c200000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x2c200000 0 0x20000>; - }; - }; - - gic: interrupt-controller@2c010000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <4>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - redistributor-stride = <0x0 0x40000>; // 256kB stride - #redistributor-regions = <2>; - reg = <0x0 0x2c010000 0 0x10000>, // GICD - <0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31 - <0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63 - <0x0 0x2c040000 0 0x2000>, // GICC - <0x0 0x2c060000 0 0x2000>, // GICH - <0x0 0x2c080000 0 0x2000>; // GICV - interrupts = <1 9 4>; - - gic-its@2c200000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x2c200000 0 0x20000>; - }; - - gic-its@2c400000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x2c400000 0 0x20000>; - }; - - ppi-partitions { - part0: interrupt-partition-0 { - affinity = <&cpu0 &cpu2>; - }; - - part1: interrupt-partition-1 { - affinity = <&cpu1 &cpu3>; - }; - }; - }; - - - device@0 { - reg = <0 0 0 4>; - interrupts = <1 1 4 &part0>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml new file mode 100644 index 000000000000..c34df35a25fc --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -0,0 +1,279 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Generic Interrupt Controller, version 3 + +maintainers: + - Marc Zyngier + +description: | + AArch64 SMP cores are often associated with a GICv3, providing Private + Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI), + Software Generated Interrupts (SGI), and Locality-specific Peripheral + Interrupts (LPI). + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,msm8996-gic-v3 + - const: arm,gic-v3 + - const: arm,gic-v3 + + interrupt-controller: true + + "#address-cells": + enum: [ 0, 1, 2 ] + "#size-cells": + enum: [ 1, 2 ] + + ranges: true + + "#interrupt-cells": + description: | + Specifies the number of cells needed to encode an interrupt source. + Must be a single cell with a value of at least 3. + If the system requires describing PPI affinity, then the value must + be at least 4. + + The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI + interrupts. Other values are reserved for future use. + + The 2nd cell contains the interrupt number for the interrupt type. + SPI interrupts are in the range [0-987]. PPI interrupts are in the + range [0-15]. + + The 3rd cell is the flags, encoded as follows: + bits[3:0] trigger type and level flags. + 1 = edge triggered + 4 = level triggered + + The 4th cell is a phandle to a node describing a set of CPUs this + interrupt is affine to. The interrupt must be a PPI, and the node + pointed must be a subnode of the "ppi-partitions" subnode. For + interrupt types other than PPI or PPIs that are not partitionned, + this cell must be zero. See the "ppi-partitions" node description + below. + + Cells 5 and beyond are reserved for future use and must have a value + of 0 if present. + enum: [ 3, 4 ] + + reg: + description: | + Specifies base physical address(s) and size of the GIC + registers, in the following order: + - GIC Distributor interface (GICD) + - GIC Redistributors (GICR), one range per redistributor region + - GIC CPU interface (GICC) + - GIC Hypervisor interface (GICH) + - GIC Virtual CPU interface (GICV) + + GICC, GICH and GICV are optional. + minItems: 2 + maxItems: 4096 # Should be enough? + + interrupts: + description: + Interrupt source of the VGIC maintenance interrupt. + maxItems: 1 + + redistributor-stride: + description: + If using padding pages, specifies the stride of consecutive + redistributors. Must be a multiple of 64kB. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint64 + - multipleOf: 0x10000 + exclusiveMinimum: 0 + + "#redistributor-regions": + description: + The number of independent contiguous regions occupied by the + redistributors. Required if more than one such region is present. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - maximum: 4096 # Should be enough? + + msi-controller: + description: + Only present if the Message Based Interrupt functionnality is + being exposed by the HW, and the mbi-ranges property present. + + mbi-ranges: + description: + A list of pairs , where "intid" is the first SPI of a range + that can be used an MBI, and "span" the size of that range. Multiple + ranges can be provided. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-matrix + - items: + minItems: 2 + maxItems: 2 + + mbi-alias: + description: + Address property. Base address of an alias of the GICD region containing + only the {SET,CLR}SPI registers to be used if isolation is required, + and if supported by the HW. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + minItems: 1 + maxItems: 2 + + ppi-partitions: + type: object + description: + PPI affinity can be expressed as a single "ppi-partitions" node, + containing a set of sub-nodes. + patternProperties: + "^interrupt-partition-[0-9]+$": + properties: + affinity: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be a list of phandles to CPU nodes (as described in + Documentation/devicetree/bindings/arm/cpus.yaml). + + required: + - affinity + +dependencies: + mbi-ranges: [ msi-controller ] + msi-controller: [ mbi-ranges ] + +required: + - compatible + - interrupts + - reg + +patternProperties: + "^gic-its@": false + "^interrupt-controller@[0-9a-f]+$": false + # msi-controller is preferred, but allow other names + "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$": + type: object + description: + GICv3 has one or more Interrupt Translation Services (ITS) that are + used to route Message Signalled Interrupts (MSI) to the CPUs. + properties: + compatible: + const: arm,gic-v3-its + + msi-controller: true + + "#msi-cells": + description: + The single msi-cell is the DeviceID of the device which will generate + the MSI. + const: 1 + + reg: + description: + Specifies the base physical address and size of the ITS registers. + maxItems: 1 + + socionext,synquacer-pre-its: + description: + (u32, u32) tuple describing the untranslated + address and size of the pre-ITS window. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + minItems: 2 + maxItems: 2 + + required: + - compatible + - msi-controller + - "#msi-cells" + - reg + + additionalProperties: false + +additionalProperties: false + +examples: + - | + gic: interrupt-controller@2cf00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + reg = <0x2f000000 0x10000>, // GICD + <0x2f100000 0x200000>, // GICR + <0x2c000000 0x2000>, // GICC + <0x2c010000 0x2000>, // GICH + <0x2c020000 0x2000>; // GICV + interrupts = <1 9 4>; + + msi-controller; + mbi-ranges = <256 128>; + + msi-controller@2c200000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x2c200000 0x20000>; + }; + }; + + interrupt-controller@2c010000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + redistributor-stride = <0x0 0x40000>; // 256kB stride + #redistributor-regions = <2>; + reg = <0x2c010000 0x10000>, // GICD + <0x2d000000 0x800000>, // GICR 1: CPUs 0-31 + <0x2e000000 0x800000>, // GICR 2: CPUs 32-63 + <0x2c040000 0x2000>, // GICC + <0x2c060000 0x2000>, // GICH + <0x2c080000 0x2000>; // GICV + interrupts = <1 9 4>; + + msi-controller@2c200000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x2c200000 0x20000>; + }; + + msi-controller@2c400000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x2c400000 0x20000>; + }; + + ppi-partitions { + part0: interrupt-partition-0 { + affinity = <&cpu0 &cpu2>; + }; + + part1: interrupt-partition-1 { + affinity = <&cpu1 &cpu3>; + }; + }; + }; + + + device@0 { + reg = <0 4>; + interrupts = <1 1 4 &part0>; + }; + +... -- cgit v1.2.3 From e7224a116f0dac593233143849f25bc095f8d2cc Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Tue, 5 Feb 2019 14:03:44 +0100 Subject: dt-bindings: at24: add the 'num-addresses' property Currently the at24 driver only creates additional i2c dummies for atmel,24c00 and it's hard-coded. Some other chips (like for example Microchip's 24AA02T) also take more slave addresses despite being otherwise compatible with already supported variants. Add a new property to the device tree binding document that defines the total number of i2c slave addresses taken by the device. The addresses are counted starting from the one in the reg property. Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/eeprom/at24.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt index f9a7c984274c..0e456bbc1213 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.txt +++ b/Documentation/devicetree/bindings/eeprom/at24.txt @@ -75,6 +75,8 @@ Optional properties: - address-width: number of address bits (one of 8, 16). + - num-addresses: total number of i2c slave addresses this device takes + Example: eeprom@52 { @@ -82,4 +84,5 @@ eeprom@52 { reg = <0x52>; pagesize = <32>; wp-gpios = <&gpio1 3 0>; + num-addresses = <8>; }; -- cgit v1.2.3 From 27eae9d4cebeb2e2abda7579efac2ea0673e0a14 Mon Sep 17 00:00:00 2001 From: Loys Ollivier Date: Wed, 13 Feb 2019 16:09:26 +0100 Subject: dt-bindings: Add vendor prefix for "GlobalTop Technology, Inc." Add globaltop vendor definition. Signed-off-by: Loys Ollivier Reviewed-by: Rob Herring Signed-off-by: Johan Hovold --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..d80a70343b36 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -150,6 +150,7 @@ geniatech Geniatech, Inc. giantec Giantec Semiconductor, Inc. giantplus Giantplus Technology Co., Ltd. globalscale Globalscale Technologies, Inc. +globaltop GlobalTop Technology, Inc. gmt Global Mixed-mode Technology, Inc. goodix Shenzhen Huiding Technology Co., Ltd. google Google, Inc. -- cgit v1.2.3 From 3bdd7f7433fd1c71b7c5ff1223d29c419e3a9d54 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 1 Feb 2019 14:22:36 +0800 Subject: dt-bindings: interrupt-controller: loongson ls1x intc Dt-bindings doc about Loongson-1 interrupt controller. Reviewed-by: Rob Herring Signed-off-by: Jiaxun Yang Signed-off-by: Marc Zyngier --- .../interrupt-controller/loongson,ls1x-intc.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.txt new file mode 100644 index 000000000000..a63ed9fcb535 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.txt @@ -0,0 +1,24 @@ +Loongson ls1x Interrupt Controller + +Required properties: + +- compatible : should be "loongson,ls1x-intc". Valid strings are: + +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 2. +- interrupts : Specifies the CPU interrupt the controller is connected to. + +Example: + +intc: interrupt-controller@1fd01040 { + compatible = "loongson,ls1x-intc"; + reg = <0x1fd01040 0x18>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; +}; -- cgit v1.2.3 From 2d803dbe1c2190be303d3c0891be21210d48b92d Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 3 Jan 2019 17:13:28 +0100 Subject: dt-bindings: gpio: pca953x: document the nxp,pcal6416 The NXP PCAL6416 is a variant of the PCA GPIO expander, with 16 GPIOs. Signed-off-by: Thomas Petazzoni Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/gpio/gpio-pca953x.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt index 4e3c550e319a..fb144e2b6522 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt @@ -16,6 +16,7 @@ Required properties: nxp,pca9574 nxp,pca9575 nxp,pca9698 + nxp,pcal6416 nxp,pcal6524 nxp,pcal9555a maxim,max7310 -- cgit v1.2.3 From f43d1b388f9be4aa47ed42c33659243a675c5c76 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Thu, 14 Feb 2019 11:34:50 +0200 Subject: devicetree: bindings: bd718x7: document HW state related ROHM specific properties Add ROHM BD71837 / BD71847 specific device tree bindings for controlling the PMIC shutdown/reset states and voltages for different HW states. The PMIC was designed to be used with NXP i.MX8 SoC and it supports SNVS low power state which seems to be typical for NXP i.MX SoCs. However, when SNVS is used we must not allow SW to control enabling/disabling those regulators which are crucial for system to boot as there is a HW limitation which causes SW controlled regulators to be kept shut down after SNVS reset. Allow setting the SNVS to be used as reset target state and allow marking those regulators which are critical for boot. Signed-off-by: Matti Vaittinen Tested-by: Angus Ainslie Reviewed-by: Angus Ainslie Signed-off-by: Mark Brown --- .../devicetree/bindings/mfd/rohm,bd71837-pmic.txt | 17 ++++++++++ .../bindings/regulator/rohm,bd71837-regulator.txt | 38 ++++++++++++++++++++++ 2 files changed, 55 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt b/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt index a4b056761eaa..d5f68ac78d15 100644 --- a/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt +++ b/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt @@ -23,6 +23,20 @@ Required properties: Optional properties: - clock-output-names : Should contain name for output clock. +- rohm,reset-snvs-powered : Transfer BD718x7 to SNVS state at reset. + +The BD718x7 supports two different HW states as reset target states. States +are called as SNVS and READY. At READY state all the PMIC power outputs go +down and OTP is reload. At the SNVS state all other logic and external +devices apart from the SNVS power domain are shut off. Please refer to NXP +i.MX8 documentation for further information regarding SNVS state. When a +reset is done via SNVS state the PMIC OTP data is not reload. This causes +power outputs that have been under SW control to stay down when reset has +switched power state to SNVS. If reset is done via READY state the power +outputs will be returned to HW control by OTP loading. Thus the reset +target state is set to READY by default. If SNVS state is used the boot +crucial regulators must have the regulator-always-on and regulator-boot-on +properties set in regulator node. Example: @@ -43,6 +57,7 @@ Example: #clock-cells = <0>; clocks = <&osc 0>; clock-output-names = "bd71837-32k-out"; + rohm,reset-snvs-powered; regulators { buck1: BUCK1 { @@ -50,8 +65,10 @@ Example: regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; + regulator-always-on; regulator-ramp-delay = <1250>; }; + // [...] }; }; diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt b/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt index 4b98ca26e61a..cbce62c22b60 100644 --- a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt @@ -27,8 +27,38 @@ BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6 LDO1, LDO2, LDO3, LDO4, LDO5, LDO6 Optional properties: +- rohm,dvs-run-voltage : PMIC default "RUN" state voltage in uV. + See below table for bucks which support this. +- rohm,dvs-idle-voltage : PMIC default "IDLE" state voltage in uV. + See below table for bucks which support this. +- rohm,dvs-suspend-voltage : PMIC default "SUSPEND" state voltage in uV. + See below table for bucks which support this. - Any optional property defined in bindings/regulator/regulator.txt +Supported default DVS states: + +BD71837: +buck | dvs-run-voltage | dvs-idle-voltage | dvs-suspend-voltage +----------------------------------------------------------------------------- +1 | supported | supported | supported +---------------------------------------------------------------------------- +2 | supported | supported | not supported +---------------------------------------------------------------------------- +3 | supported | not supported | not supported +---------------------------------------------------------------------------- +4 | supported | not supported | not supported +---------------------------------------------------------------------------- +rest | not supported | not supported | not supported + +BD71847: +buck | dvs-run-voltage | dvs-idle-voltage | dvs-suspend-voltage +----------------------------------------------------------------------------- +1 | supported | supported | supported +---------------------------------------------------------------------------- +2 | supported | supported | not supported +---------------------------------------------------------------------------- +rest | not supported | not supported | not supported + Example: regulators { buck1: BUCK1 { @@ -36,7 +66,11 @@ regulators { regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; + regulator-always-on; regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <900000>; + rohm,dvs-idle-voltage = <850000>; + rohm,dvs-suspend-voltage = <800000>; }; buck2: BUCK2 { regulator-name = "buck2"; @@ -45,18 +79,22 @@ regulators { regulator-boot-on; regulator-always-on; regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; }; buck3: BUCK3 { regulator-name = "buck3"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; + rohm,dvs-run-voltage = <1000000>; }; buck4: BUCK4 { regulator-name = "buck4"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; + rohm,dvs-run-voltage = <1000000>; }; buck5: BUCK5 { regulator-name = "buck5"; -- cgit v1.2.3 From 5bb57a7488c64a391107b2002d4e1f7d6bda00aa Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 8 Jan 2019 10:56:31 +0530 Subject: dt-bindings: input: ti-tsc-adc: Add new compatible for AM654 SoCs AM654 SoCs has ADC IP which is similar to AM335x, but without the touchscreen part. Add new compatible to handle AM654 SoCs. Also, it seems that existing compatible strings used in the kernel DTs were never documented. So, document them now. Signed-off-by: Vignesh R Reviewed-by: Rob Herring Acked-by: Dmitry Torokhov Signed-off-by: Tero Kristo --- .../devicetree/bindings/input/touchscreen/ti-tsc-adc.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt b/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt index b1163bf97146..aad5e34965eb 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt @@ -2,7 +2,12 @@ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Required properties: +- mfd + compatible: Should be + "ti,am3359-tscadc" for AM335x/AM437x SoCs + "ti,am654-tscadc", "ti,am3359-tscadc" for AM654 SoCs - child "tsc" + compatible: Should be "ti,am3359-tsc". ti,wires: Wires refer to application modes i.e. 4/5/8 wire touchscreen support on the platform. ti,x-plate-resistance: X plate resistance @@ -25,6 +30,9 @@ Required properties: AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7. XP = 0, XN = 1, YP = 2, YN = 3. - child "adc" + compatible: Should be + "ti,am3359-adc" for AM335x/AM437x SoCs + "ti,am654-adc", "ti,am3359-adc" for AM654 SoCs ti,adc-channels: List of analog inputs available for ADC. AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7. -- cgit v1.2.3 From 3deb254d655931e72d195a5921db5af5f7b6572a Mon Sep 17 00:00:00 2001 From: Loys Ollivier Date: Wed, 13 Feb 2019 16:09:27 +0100 Subject: dt-bindings: gnss: add mediatek binding Add binding for Mediatek-based GNSS receivers. Signed-off-by: Loys Ollivier Reviewed-by: Rob Herring [ johan: rename backup supply ] Signed-off-by: Johan Hovold --- .../devicetree/bindings/gnss/mediatek.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/gnss/mediatek.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gnss/mediatek.txt b/Documentation/devicetree/bindings/gnss/mediatek.txt new file mode 100644 index 000000000000..80cb802813c5 --- /dev/null +++ b/Documentation/devicetree/bindings/gnss/mediatek.txt @@ -0,0 +1,35 @@ +Mediatek-based GNSS Receiver DT binding + +Mediatek chipsets are used in GNSS-receiver modules produced by several +vendors and can use a UART interface. + +Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic +properties. + +Required properties: + +- compatible : Must be + + "globaltop,pa6h" + +- vcc-supply : Main voltage regulator (pin name: VCC) + +Optional properties: + +- current-speed : Default UART baud rate +- gnss-fix-gpios : GPIO used to determine device position fix state + (pin name: FIX, 3D_FIX) +- reset-gpios : GPIO used to reset the device (pin name: RESET, NRESET) +- timepulse-gpios : Time pulse GPIO (pin name: PPS1, 1PPS) +- vbackup-supply : Backup voltage regulator (pin name: VBAT, VBACKUP) + +Example: + +serial@1234 { + compatible = "ns16550a"; + + gnss { + compatible = "globaltop,pa6h"; + vcc-supply = <&vcc_3v3>; + }; +}; -- cgit v1.2.3 From 10e7122107bd426a6ac33bcb17392978a72ca13b Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Tue, 12 Feb 2019 02:34:05 +0000 Subject: dt-bindings: rtc: Update for new chip in isl1208 series Since this documents multiple chips controlled by the isl1208 driver, name it isil,isl1208.txt, as the convention is to use the base driver name in the bindings document for drivers with multiple devices. Include all chips supported by this driver in the docs. Make it clear which properties apply to which chips. Expand documentation for existing isil,evienb property to explain operation in more detail. Existing docs just describe it in terms of setting a bit in a register. CC: Alessandro Zummo CC: Alexandre Belloni CC: Rob Herring CC: Mark Rutland CC: devicetree@vger.kernel.org Signed-off-by: Trent Piepho Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/rtc/isil,isl1208.txt | 38 ++++++++++++++++++++++ .../devicetree/bindings/rtc/isil,isl1219.txt | 29 ----------------- 2 files changed, 38 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl1208.txt delete mode 100644 Documentation/devicetree/bindings/rtc/isil,isl1219.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/isil,isl1208.txt b/Documentation/devicetree/bindings/rtc/isil,isl1208.txt new file mode 100644 index 000000000000..51f003006f04 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/isil,isl1208.txt @@ -0,0 +1,38 @@ +Intersil ISL1209/19 I2C RTC/Alarm chip with event in + +ISL12X9 have additional pins EVIN and #EVDET for tamper detection, while the +ISL1208 and ISL1218 do not. They are all use the same driver with the bindings +described here, with chip specific properties as noted. + +Required properties supported by the device: + - "compatible": Should be one of the following: + - "isil,isl1208" + - "isil,isl1209" + - "isil,isl1218" + - "isil,isl1219" + - "reg": I2C bus address of the device + +Optional properties: + - "interrupt-names": list which may contains "irq" and "evdet" + evdet applies to isl1209 and isl1219 only + - "interrupts": list of interrupts for "irq" and "evdet" + evdet applies to isl1209 and isl1219 only + - "isil,ev-evienb": Enable or disable internal pull on EVIN pin + Applies to isl1209 and isl1219 only + Possible values are 0 and 1 + Value 0 enables internal pull-up on evin pin, 1 disables it. + Default will leave the non-volatile configuration of the pullup + as is. + +Example isl1219 node with #IRQ pin connected to SoC gpio1 pin12 and #EVDET pin +connected to SoC gpio2 pin 24 and internal pull-up enabled in EVIN pin. + + isl1219: rtc@68 { + compatible = "isil,isl1219"; + reg = <0x68>; + interrupt-names = "irq", "evdet"; + interrupts-extended = <&gpio1 12 IRQ_TYPE_EDGE_FALLING>, + <&gpio2 24 IRQ_TYPE_EDGE_FALLING>; + isil,ev-evienb = <1>; + }; + diff --git a/Documentation/devicetree/bindings/rtc/isil,isl1219.txt b/Documentation/devicetree/bindings/rtc/isil,isl1219.txt deleted file mode 100644 index c3efd48e91c2..000000000000 --- a/Documentation/devicetree/bindings/rtc/isil,isl1219.txt +++ /dev/null @@ -1,29 +0,0 @@ -Intersil ISL1219 I2C RTC/Alarm chip with event in - -ISL1219 has additional pins EVIN and #EVDET for tamper detection. - -Required properties supported by the device: - - - "compatible": must be "isil,isl1219" - - "reg": I2C bus address of the device - -Optional properties: - - - "interrupt-names": list which may contains "irq" and "evdet" - - "interrupts": list of interrupts for "irq" and "evdet" - - "isil,ev-evienb": if present EV.EVIENB bit is set to the specified - value for proper operation. - - -Example isl1219 node with #IRQ pin connected to SoC gpio1 pin12 - and #EVDET pin connected to SoC gpio2 pin 24: - - isl1219: rtc@68 { - compatible = "isil,isl1219"; - reg = <0x68>; - interrupt-names = "irq", "evdet"; - interrupts-extended = <&gpio1 12 IRQ_TYPE_EDGE_FALLING>, - <&gpio2 24 IRQ_TYPE_EDGE_FALLING>; - isil,ev-evienb = <1>; - }; - -- cgit v1.2.3 From e6e7376cfd7b3f9b63de3a22792f64d9bfb2ab53 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 13 Feb 2019 00:21:36 +0100 Subject: rtc: rv3028: add new driver Add a driver for the MicroCrystal RV-3028. It is a SMT Real-Time Clock Module that incorporates an integrated CMOS circuit together with an XTAL. It has an i2c interface. The driver handles date/time, alarms, trickle charging, timestamping, frequency offset correction, EEPROM and NVRAM. Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/rtc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc.txt b/Documentation/devicetree/bindings/rtc/rtc.txt index d86e2850fe1c..3e6a215e7304 100644 --- a/Documentation/devicetree/bindings/rtc/rtc.txt +++ b/Documentation/devicetree/bindings/rtc/rtc.txt @@ -52,6 +52,7 @@ emmicro,em3027 EM Microelectronic EM3027 Real-time Clock isil,isl1208 Intersil ISL1208 Low Power RTC with Battery Backed SRAM isil,isl1218 Intersil ISL1218 Low Power RTC with Battery Backed SRAM isil,isl12022 Intersil ISL12022 Real-time Clock +microcrystal,rv3028 Real Time Clock Module with I2C-Bus microcrystal,rv3029 Real Time Clock Module with I2C-Bus microcrystal,rv8523 Real Time Clock nxp,pcf2127 Real-time clock -- cgit v1.2.3 From 243b44e157598b34cbc62f925cb4b8f725e69b68 Mon Sep 17 00:00:00 2001 From: Artem Panfilov Date: Sun, 17 Feb 2019 21:53:21 +0300 Subject: dt-bindings: rtc: add ABEOZ9 Add ABEOZ9 to the list of trivial RTCs Signed-off-by: Artem Panfilov Reviewed-by: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/rtc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc.txt b/Documentation/devicetree/bindings/rtc/rtc.txt index 3e6a215e7304..fc79d7133218 100644 --- a/Documentation/devicetree/bindings/rtc/rtc.txt +++ b/Documentation/devicetree/bindings/rtc/rtc.txt @@ -43,6 +43,7 @@ possibly an interrupt line. Compatible Vendor / Chip ========== ============= abracon,abb5zes3 AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface +abracon,abeoz9 AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output dallas,ds1672 Dallas DS1672 Real-time Clock dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM -- cgit v1.2.3 From 376211557302c1d851452579e5dc7f87d297f572 Mon Sep 17 00:00:00 2001 From: Rohit kumar Date: Fri, 30 Nov 2018 12:59:09 +0530 Subject: dt-binding: remoteproc: Remove lpass_aon clock from adsp pil clock list LPASS_Audio_Wrapper_AON clock is on by default. Remove it from lpass clock list to avoid voting for it. Reviewed-by: Rob Herring Signed-off-by: Rohit kumar Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/remoteproc/qcom,adsp-pil.txt | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp-pil.txt b/Documentation/devicetree/bindings/remoteproc/qcom,adsp-pil.txt index a842a782b557..66af2c30944f 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp-pil.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp-pil.txt @@ -35,7 +35,7 @@ on the Qualcomm Technology Inc. ADSP Hexagon core. Value type: Definition: List of clock input name strings sorted in the same order as the clocks property. Definition must have - "xo", "sway_cbcr", "lpass_aon", "lpass_ahbs_aon_cbcr", + "xo", "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep" and "qdsp6ss_core". @@ -100,13 +100,12 @@ ADSP, as it is found on SDM845 boards. clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_LPASS_SWAY_CLK>, - <&lpasscc LPASS_AUDIO_WRAPPER_AON_CLK>, <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>, <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>, <&lpasscc LPASS_QDSP6SS_XO_CLK>, <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>, <&lpasscc LPASS_QDSP6SS_CORE_CLK>; - clock-names = "xo", "sway_cbcr", "lpass_aon", + clock-names = "xo", "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core"; -- cgit v1.2.3 From 076d792b17468632cb104b6de8d2cf6cd426fed1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 28 Jan 2019 03:58:43 -0500 Subject: media: dt-bindings: media: sun6i: Add A64 CSI compatible Allwinner A64 CSI is a single channel time-multiplexed BT.656 protocol interface. Add separate compatible string for A64 since it require explicit change in sun6i_csi driver to update default CSI_SCLK rate. Signed-off-by: Jagan Teki Reviewed-by: Rob Herring Acked-by: Maxime Ripard Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/sun6i-csi.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt index cc37cf7fd051..0dd540bb03db 100644 --- a/Documentation/devicetree/bindings/media/sun6i-csi.txt +++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt @@ -8,6 +8,7 @@ Required properties: * "allwinner,sun6i-a31-csi" * "allwinner,sun8i-h3-csi" * "allwinner,sun8i-v3s-csi" + * "allwinner,sun50i-a64-csi" - reg: base address and size of the memory-mapped region. - interrupts: interrupt associated to this IP - clocks: phandles to the clocks feeding the CSI -- cgit v1.2.3 From e260d78736db0c74240df2243c299be7b0d0b182 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 15:20:24 -0500 Subject: media: vsp1: Add RZ/G support Document RZ/G1 and RZ/G2 support. Signed-off-by: Fabrizio Castro Signed-off-by: Laurent Pinchart Reviewed-by: Simon Horman Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/renesas,vsp1.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.txt b/Documentation/devicetree/bindings/media/renesas,vsp1.txt index 16427017cb45..cd5a955b2ea0 100644 --- a/Documentation/devicetree/bindings/media/renesas,vsp1.txt +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.txt @@ -2,13 +2,13 @@ The VSP is a video processing engine that supports up-/down-scaling, alpha blending, color space conversion and various other image processing features. -It can be found in the Renesas R-Car second generation SoCs. +It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs. Required properties: - compatible: Must contain one of the following values - - "renesas,vsp1" for the R-Car Gen2 VSP1 - - "renesas,vsp2" for the R-Car Gen3 VSP2 + - "renesas,vsp1" for the R-Car Gen2 and RZ/G1 VSP1 + - "renesas,vsp2" for the R-Car Gen3 and RZ/G2 VSP2 - reg: Base address and length of the registers block for the VSP. - interrupts: VSP interrupt specifier. -- cgit v1.2.3 From b8eb83457e79fc745abea3abcd6c95b1428a05ee Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 15:20:33 -0500 Subject: media: dt-bindings: media: renesas-fcp: Add RZ/G2 support Document RZ/G2 support. Signed-off-by: Fabrizio Castro Signed-off-by: Laurent Pinchart Reviewed-by: Simon Horman Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/renesas,fcp.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/renesas,fcp.txt b/Documentation/devicetree/bindings/media/renesas,fcp.txt index 3ec91803ba58..79c37395b396 100644 --- a/Documentation/devicetree/bindings/media/renesas,fcp.txt +++ b/Documentation/devicetree/bindings/media/renesas,fcp.txt @@ -2,8 +2,9 @@ Renesas R-Car Frame Compression Processor (FCP) ----------------------------------------------- The FCP is a companion module of video processing modules in the Renesas R-Car -Gen3 SoCs. It provides data compression and decompression, data caching, and -conversion of AXI transactions in order to reduce the memory bandwidth. +Gen3 and RZ/G2 SoCs. It provides data compression and decompression, data +caching, and conversion of AXI transactions in order to reduce the memory +bandwidth. There are three types of FCP: FCP for Codec (FCPC), FCP for VSP (FCPV) and FCP for FDP (FCPF). Their configuration and behaviour depend on the module they -- cgit v1.2.3 From 3f44193780fb5180026f463fbf9c89b13bd5f318 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Wed, 6 Feb 2019 10:13:18 -0500 Subject: media: dt-bindings: add bindings for i.MX7 media driver Add bindings documentation for i.MX7 media drivers. The imx7 MIPI CSI2 and imx7 CMOS Sensor Interface. Signed-off-by: Rui Miguel Silva Reviewed-by: Rob Herring Acked-by: Sakari Ailus Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/imx7-csi.txt | 45 +++++++++++ .../devicetree/bindings/media/imx7-mipi-csi2.txt | 90 ++++++++++++++++++++++ 2 files changed, 135 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/imx7-csi.txt create mode 100644 Documentation/devicetree/bindings/media/imx7-mipi-csi2.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/imx7-csi.txt b/Documentation/devicetree/bindings/media/imx7-csi.txt new file mode 100644 index 000000000000..3c07bc676bc3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx7-csi.txt @@ -0,0 +1,45 @@ +Freescale i.MX7 CMOS Sensor Interface +===================================== + +csi node +-------- + +This is device node for the CMOS Sensor Interface (CSI) which enables the chip +to connect directly to external CMOS image sensors. + +Required properties: + +- compatible : "fsl,imx7-csi"; +- reg : base address and length of the register set for the device; +- interrupts : should contain CSI interrupt; +- clocks : list of clock specifiers, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details; +- clock-names : must contain "axi", "mclk" and "dcic" entries, matching + entries in the clock property; + +The device node shall contain one 'port' child node with one child 'endpoint' +node, according to the bindings defined in: +Documentation/devicetree/bindings/media/video-interfaces.txt. + +In the following example a remote endpoint is a video multiplexer. + +example: + + csi: csi@30710000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "fsl,imx7-csi"; + reg = <0x30710000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "axi", "mclk", "dcic"; + + port { + csi_from_csi_mux: endpoint { + remote-endpoint = <&csi_mux_to_csi>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/imx7-mipi-csi2.txt b/Documentation/devicetree/bindings/media/imx7-mipi-csi2.txt new file mode 100644 index 000000000000..71fd74ed3ec8 --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx7-mipi-csi2.txt @@ -0,0 +1,90 @@ +Freescale i.MX7 Mipi CSI2 +========================= + +mipi_csi2 node +-------------- + +This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is +compatible with previous version of Samsung D-phy. + +Required properties: + +- compatible : "fsl,imx7-mipi-csi2"; +- reg : base address and length of the register set for the device; +- interrupts : should contain MIPI CSIS interrupt; +- clocks : list of clock specifiers, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details; +- clock-names : must contain "pclk", "wrap" and "phy" entries, matching + entries in the clock property; +- power-domains : a phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details. +- reset-names : should include following entry "mrst"; +- resets : a list of phandle, should contain reset entry of + reset-names; +- phy-supply : from the generic phy bindings, a phandle to a regulator that + provides power to MIPI CSIS core; + +Optional properties: + +- clock-frequency : The IP's main (system bus) clock frequency in Hz, default + value when this property is not specified is 166 MHz; +- fsl,csis-hs-settle : differential receiver (HS-RX) settle time; + +The device node should contain two 'port' child nodes with one child 'endpoint' +node, according to the bindings defined in: + Documentation/devicetree/bindings/ media/video-interfaces.txt. + The following are properties specific to those nodes. + +port node +--------- + +- reg : (required) can take the values 0 or 1, where 0 shall be + related to the sink port and port 1 shall be the source + one; + +endpoint node +------------- + +- data-lanes : (required) an array specifying active physical MIPI-CSI2 + data input lanes and their mapping to logical lanes; this + shall only be applied to port 0 (sink port), the array's + content is unused only its length is meaningful, + in this case the maximum length supported is 2; + +example: + + mipi_csi: mipi-csi@30750000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "fsl,imx7-mipi-csi2"; + reg = <0x30750000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "pclk", "wrap", "phy"; + clock-frequency = <166000000>; + power-domains = <&pgc_mipi_phy>; + phy-supply = <®_1p0d>; + resets = <&src IMX7_RESET_MIPI_PHY_MRST>; + reset-names = "mrst"; + fsl,csis-hs-settle = <3>; + + port@0 { + reg = <0>; + + mipi_from_sensor: endpoint { + remote-endpoint = <&ov2680_to_mipi>; + data-lanes = <1>; + }; + }; + + port@1 { + reg = <1>; + + mipi_vc0_to_csi_mux: endpoint { + remote-endpoint = <&csi_mux_from_mipi_vc0>; + }; + }; + }; -- cgit v1.2.3 From dbdd4f69125c397c2bbded44d1969b1135ec09a0 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Thu, 27 Dec 2018 16:13:49 +0100 Subject: devicetree: hwmon: Add bindings documentation for HIH6130 Add bindings documentation for HIH6130 driver. Signed-off-by: Andreas Kemnade Reviewed-by: Rob Herring Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/hih6130.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/hih6130.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/hih6130.txt b/Documentation/devicetree/bindings/hwmon/hih6130.txt new file mode 100644 index 000000000000..2c43837af4c2 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/hih6130.txt @@ -0,0 +1,12 @@ +Honeywell Humidicon HIH-6130 humidity/temperature sensor +-------------------------------------------------------- + +Requires node properties: +- compatible : "honeywell,hi6130" +- reg : the I2C address of the device. This is 0x27. + +Example: + hih6130@27 { + compatible = "honeywell,hih6130"; + reg = <0x27>; + }; -- cgit v1.2.3 From 35ca16c84e9b1919349b274e19e647790b6fd4ad Mon Sep 17 00:00:00 2001 From: Xiaoting Liu Date: Thu, 10 Jan 2019 10:24:33 +0800 Subject: dt-bindings: hwmon: add dps650ab documentation Bindings for Delta Electronics DPS-650-AB power supply. Signed-off-by: Xiaoting Liu Reviewed-by: Rob Herring Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/dps650ab.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/dps650ab.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/dps650ab.txt b/Documentation/devicetree/bindings/hwmon/dps650ab.txt new file mode 100644 index 000000000000..76780e795899 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/dps650ab.txt @@ -0,0 +1,11 @@ +Bindings for Delta Electronics DPS-650-AB power supply + +Required properties: +- compatible : "delta,dps650ab" +- reg : I2C address, one of 0x58, 0x59. + +Example: + dps650ab@58 { + compatible = "delta,dps650ab"; + reg = <0x58>; + }; -- cgit v1.2.3 From 2e1ce20149ea3cd1cee95a07c51a5b8873c20463 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Thu, 17 Jan 2019 15:12:52 -0800 Subject: dt-bindings: hwmon: (ina3221) Add ti,single-shot property By default, ina3221, as a hardware monitor, continuously measures the inputs and generates corresponding data. However, for battery powered devices, this mode might be power consuming. This patch adds a "ti,single-shot" property to allow changing the default continuous mode to single-shot operating mode. Signed-off-by: Nicolin Chen Reviewed-by: Rob Herring Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/ina3221.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/ina3221.txt b/Documentation/devicetree/bindings/hwmon/ina3221.txt index a7b25caa2b8e..fa63b6171407 100644 --- a/Documentation/devicetree/bindings/hwmon/ina3221.txt +++ b/Documentation/devicetree/bindings/hwmon/ina3221.txt @@ -6,6 +6,16 @@ Texas Instruments INA3221 Device Tree Bindings - reg: I2C address Optional properties: + - ti,single-shot: This chip has two power modes: single-shot (chip takes one + measurement and then shuts itself down) and continuous ( + chip takes continuous measurements). The continuous mode is + more reliable and suitable for hardware monitor type device, + but the single-shot mode is more power-friendly and useful + for battery-powered device which cares power consumptions + while still needs some measurements occasionally. + If this property is present, the single-shot mode will be + used, instead of the default continuous one for monitoring. + = The node contains optional child nodes for three channels = = Each child node describes the information of input source = -- cgit v1.2.3 From 1abf33061898b90246e2f1bbc15a722714ceaa1c Mon Sep 17 00:00:00 2001 From: Jeremy Gebben Date: Mon, 4 Feb 2019 13:19:04 -0700 Subject: dt-bindings: Add LM96000 as a trivial device The LM96000 is a temperature sensor and fan controller based on the LM85. Signed-off-by: Jeremy Gebben Reviewed-by: Rob Herring Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index cc64ec63a6ad..d79fb22bde39 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -322,6 +322,8 @@ properties: - ti,ads7830 # Temperature Monitoring and Fan Control - ti,amc6821 + # Temperature sensor with integrated fan control + - ti,lm96000 # I2C Touch-Screen Controller - ti,tsc2003 # Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface -- cgit v1.2.3 From cde999e2a7b238ef46875a724d3630e168d94f4d Mon Sep 17 00:00:00 2001 From: Pascal PAILLET-LME Date: Tue, 19 Feb 2019 10:04:32 +0000 Subject: dt-bindings: regulator: remove interrupt-parent description on stpmic1 The interrupt parent description is not needed as the parent is a parent node with 'interrupt-controller' property. Signed-off-by: pascal paillet Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt | 3 --- 1 file changed, 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt b/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt index a3f476240565..de27897d3f3a 100644 --- a/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt @@ -29,7 +29,6 @@ Optional properties: if set, all regulators are switched off in case of over-current detection on this regulator, if not set, the driver only sends an over-current event. -- interrupt-parent: phandle to the parent interrupt controller - interrupts: index of current limit detection interrupt - -supply: phandle to the parent supply/regulator node each regulator supply can be described except vref_ddr. @@ -43,7 +42,6 @@ regulators { vdd_core: buck1 { regulator-name = "vdd_core"; interrupts = ; - interrupt-parent = <&pmic>; st,mask-reset; regulator-pull-down; regulator-min-microvolt = <700000>; @@ -53,7 +51,6 @@ regulators { v3v3: buck4 { regulator-name = "v3v3"; interrupts = ; - interrupt-parent = <&mypmic>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; -- cgit v1.2.3 From f369788894a483f9e703b13c0841ee0069eed758 Mon Sep 17 00:00:00 2001 From: Pascal PAILLET-LME Date: Tue, 19 Feb 2019 10:04:33 +0000 Subject: dt-bindings: regulator: remove regulator pull-down support for stpmic1 Regulator high pull down are enabled by default so remove support in the driver. Signed-off-by: Pascal Paillet Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt b/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt index de27897d3f3a..bf9385b11da6 100644 --- a/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt @@ -23,8 +23,6 @@ Switches are fixed voltage regulators with only enable/disable capability. Optional properties: - st,mask-reset: mask reset for this regulator: the regulator configuration is maintained during pmic reset. -- regulator-pull-down: enable high pull down - if not specified light pull down is used - regulator-over-current-protection: if set, all regulators are switched off in case of over-current detection on this regulator, -- cgit v1.2.3 From 714a74f13e812889491ffb07647f48406ec2a84b Mon Sep 17 00:00:00 2001 From: Pascal PAILLET-LME Date: Tue, 19 Feb 2019 10:04:34 +0000 Subject: dt-bindings: regulator: Add active discharge support for stpmic1 Add support for active discharge for USB power switches. Signed-off-by: pascal paillet Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt b/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt index bf9385b11da6..6189df71ea98 100644 --- a/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt @@ -30,6 +30,7 @@ Optional properties: - interrupts: index of current limit detection interrupt - -supply: phandle to the parent supply/regulator node each regulator supply can be described except vref_ddr. +- regulator-active-discharge: can be used on pwr_sw1 and pwr_sw2. Example: regulators { -- cgit v1.2.3 From d98afe1353b6dbd1527f3833da70d8525e6dbae3 Mon Sep 17 00:00:00 2001 From: Bogdan Togorean Date: Fri, 15 Feb 2019 12:26:33 +0200 Subject: ASoC: adau1977: Fix reset-gpios typo This change fixes a typo in the dt-binding examples (reset_gpio -> reset-gpios). Even though 'reset-gpio' is a valid construct for gpiolib the naming 'reset-gpios' is more suited for dt-bindings documentation. Signed-off-by: Bogdan Togorean Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/adi,adau1977.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/adi,adau1977.txt b/Documentation/devicetree/bindings/sound/adi,adau1977.txt index e79aeef73f28..11acd94b1665 100644 --- a/Documentation/devicetree/bindings/sound/adi,adau1977.txt +++ b/Documentation/devicetree/bindings/sound/adi,adau1977.txt @@ -17,7 +17,7 @@ Required properties: Documentation/devicetree/bindings/regulator/regulator.txt Optional properties: - - reset-gpio: the reset pin for the chip, for more details consult + - reset-gpios: the reset pin for the chip, for more details consult Documentation/devicetree/bindings/gpio/gpio.txt - DVDD-supply: supply voltage for the digital core, please consult @@ -40,7 +40,7 @@ Examples: AVDD-supply = <®ulator>; DVDD-supply = <®ulator_digital>; - reset_gpio = <&gpio 10 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio 10 GPIO_ACTIVE_LOW>; }; adau1977_i2c: adau1977@11 { @@ -50,5 +50,5 @@ Examples: AVDD-supply = <®ulator>; DVDD-supply = <®ulator_digital>; - reset_gpio = <&gpio 10 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio 10 GPIO_ACTIVE_LOW>; }; -- cgit v1.2.3 From 36ed8ebc7a2bdd1296cbc9059f2b76166af0fc59 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 6 Feb 2019 19:04:25 +0100 Subject: dt-bindings: arm: atmel: add new sam9x60 SFR binding Add this SFR compatible definition for the sam9x60 SoC. Will be needed in OHCI driver: ohci-at91.c. Signed-off-by: Nicolas Ferre Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 14f319f694b7..3363d9ae4e74 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -147,6 +147,7 @@ required properties: - compatible: Should be "atmel,-sfr", "syscon" or "atmel,-sfrbu", "syscon" can be "sama5d3", "sama5d4" or "sama5d2". + It also can be "microchip,sam9x60-sfr", "syscon". - reg: Should contain registers location and length sfr@f0038000 { -- cgit v1.2.3 From fb7a97456e324b4ac13044db17a4f5b974e49e33 Mon Sep 17 00:00:00 2001 From: Bogdan Togorean Date: Tue, 19 Feb 2019 16:11:38 +0200 Subject: ASoC: adau1977: Add MICBIAS example in DT bindings Add MICBIAS property to the optional devicetree bindings. Signed-off-by: Bogdan Togorean Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/adi,adau1977.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/adi,adau1977.txt b/Documentation/devicetree/bindings/sound/adi,adau1977.txt index e79aeef73f28..87c16e6f2e7c 100644 --- a/Documentation/devicetree/bindings/sound/adi,adau1977.txt +++ b/Documentation/devicetree/bindings/sound/adi,adau1977.txt @@ -23,6 +23,12 @@ Optional properties: - DVDD-supply: supply voltage for the digital core, please consult Documentation/devicetree/bindings/regulator/regulator.txt +- adi,micbias: configures the voltage setting for the MICBIAS pin. + Select 0/1/2/3/4/5/6/7/8 to specify MICBIAS voltage + 5V/5.5V/6V/6.5V/7V/7.5V/8V/8.5V/9V + If not specified the default value will be "7" meaning 8.5 Volts. + This property is only valid for the ADAU1977 + For required properties on SPI, please consult Documentation/devicetree/bindings/spi/spi-bus.txt @@ -40,6 +46,7 @@ Examples: AVDD-supply = <®ulator>; DVDD-supply = <®ulator_digital>; + adi,micbias = <3>; reset_gpio = <&gpio 10 GPIO_ACTIVE_LOW>; }; -- cgit v1.2.3 From 3b155e873a38c3b28e419da759cfe86c74b1c870 Mon Sep 17 00:00:00 2001 From: Yash Shah Date: Tue, 19 Feb 2019 17:10:06 +0530 Subject: spi: sifive: Add DT documentation for SiFive SPI controller DT documentation for SPI controller added. Signed-off-by: Palmer Dabbelt Signed-off-by: Emil Renner Berthing Signed-off-by: Yash Shah Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/spi-sifive.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-sifive.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.txt b/Documentation/devicetree/bindings/spi/spi-sifive.txt new file mode 100644 index 000000000000..3f5c6e438972 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-sifive.txt @@ -0,0 +1,37 @@ +SiFive SPI controller Device Tree Bindings +------------------------------------------ + +Required properties: +- compatible : Should be "sifive,-spi" and "sifive,spi". + Supported compatible strings are: + "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated + onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive + SPI v0 IP block with no chip integration tweaks. + Please refer to sifive-blocks-ip-versioning.txt for details +- reg : Physical base address and size of SPI registers map + A second (optional) range can indicate memory mapped flash +- interrupts : Must contain one entry +- interrupt-parent : Must be core interrupt controller +- clocks : Must reference the frequency given to the controller +- #address-cells : Must be '1', indicating which CS to use +- #size-cells : Must be '0' + +Optional properties: +- sifive,fifo-depth : Depth of hardware queues; defaults to 8 +- sifive,max-bits-per-word : Maximum bits per word; defaults to 8 + +SPI RTL that corresponds to the IP block version numbers can be found here: +https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi + +Example: + spi: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic>; + interrupts = <51>; + clocks = <&tlclk>; + #address-cells = <1>; + #size-cells = <0>; + sifive,fifo-depth = <8>; + sifive,max-bits-per-word = <8>; + }; -- cgit v1.2.3 From 5ddfed2bffcd2a6f624c5f9224d31d434e44812f Mon Sep 17 00:00:00 2001 From: Artur Rojek Date: Sun, 17 Feb 2019 15:29:12 +0100 Subject: dt-bindings: power: supply: Add voltage-max-design-microvolt property Add documentation for the "voltage-max-design-microvolt" property. Signed-off-by: Artur Rojek Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/supply/battery.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/battery.txt b/Documentation/devicetree/bindings/power/supply/battery.txt index 89871ab8c704..5c913d4cf36c 100644 --- a/Documentation/devicetree/bindings/power/supply/battery.txt +++ b/Documentation/devicetree/bindings/power/supply/battery.txt @@ -16,6 +16,7 @@ Required Properties: Optional Properties: - voltage-min-design-microvolt: drained battery voltage + - voltage-max-design-microvolt: fully charged battery voltage - energy-full-design-microwatt-hours: battery design energy - charge-full-design-microamp-hours: battery design capacity - precharge-current-microamp: current for pre-charge phase @@ -48,6 +49,7 @@ Example: bat: battery { compatible = "simple-battery"; voltage-min-design-microvolt = <3200000>; + voltage-max-design-microvolt = <4200000>; energy-full-design-microwatt-hours = <5290000>; charge-full-design-microamp-hours = <1430000>; precharge-current-microamp = <256000>; -- cgit v1.2.3 From 6a88b285d5317e84fd792d7b06b36f3a2958dbe2 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 6 Feb 2019 19:12:19 +0100 Subject: dt-bindings: arm: atmel: add missing samx7 to reset controller Add this missing compatibility string to the Reset Controller compatible string chip list. Signed-off-by: Nicolas Ferre Reviewed-by: Rob Herring Acked-by: Alexandre Belloni Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 14f319f694b7..36952cc39993 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -21,7 +21,7 @@ Its subnodes can be: RSTC Reset Controller required properties: - compatible: Should be "atmel,-rstc". - can be "at91sam9260" or "at91sam9g45" or "sama5d3" + can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7" - reg: Should contain registers location and length - clocks: phandle to input clock. -- cgit v1.2.3 From e03423c4530e96e65274551a1139ce0f9f5db0ed Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 6 Feb 2019 19:12:20 +0100 Subject: dt-bindings: arm: atmel: add new sam9x60 reset controller binding Update the Reset Controller's binding to add new SoC compatibility string. Signed-off-by: Nicolas Ferre Reviewed-by: Rob Herring Acked-by: Alexandre Belloni Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 36952cc39993..badce6ef3ab3 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -22,6 +22,7 @@ Its subnodes can be: RSTC Reset Controller required properties: - compatible: Should be "atmel,-rstc". can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7" + it also can be "microchip,sam9x60-rstc" - reg: Should contain registers location and length - clocks: phandle to input clock. -- cgit v1.2.3 From cc8ed1a9d65c537742b40658d94e0ebea9cb0e81 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 5 Jan 2019 12:58:57 +0530 Subject: scsi: dt-bindings: ufs: Add HI3670 UFS controller binding Add devicetree binding for HI3670 UFS controller. HI3760 SoC is very similar to HI3660 SoC with almost same IPs. Only major difference in terms of UFS is the PHY. HI3670 has 10nm PHY. But since the original driver (HI3660 UFS) cannot make HI3670 UFS functional, a separate compatible is added for HI3670 without any fallback. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Acked-by: Wei Li Signed-off-by: Martin K. Petersen --- Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt index a48c44817367..0b83df1a5418 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt @@ -6,9 +6,10 @@ Each UFS Host Controller should have its own node. Required properties: - compatible : compatible list, contains one of the following - "hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs - host controller present on Hi36xx chipset. + host controller present on Hi3660 chipset. + "hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs + host controller present on Hi3670 chipset. - reg : should contain UFS register address space & UFS SYS CTRL register address, -- interrupt-parent : interrupt device - interrupts : interrupt number - clocks : List of phandle and clock specifier pairs - clock-names : List of clock input name strings sorted in the same -- cgit v1.2.3 From bae2bf97939aebd74dfd8f0b76b4902a19e63eef Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 20 Feb 2019 17:25:18 +0200 Subject: dt-bindings: net: ti: deprecate cpsw-phy-sel bindings The cpsw-phy-sel driver was replaced with new PHY driver phy-gmii-sel, so deprecate cpsw-phy-sel bindings. Reviewed-by: Rob Herring Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/net/cpsw-phy-sel.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt b/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt index 764c0c79b43d..5d76f991c027 100644 --- a/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt +++ b/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt @@ -1,4 +1,4 @@ -TI CPSW Phy mode Selection Device Tree Bindings +TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED) ----------------------------------------------- Required properties: -- cgit v1.2.3 From e1a6ba5dcb9b31c652214b49cada5529e6a38988 Mon Sep 17 00:00:00 2001 From: Xiaowei Bao Date: Thu, 21 Feb 2019 11:16:17 +0800 Subject: dt-bindings: add DT binding for the layerscape PCIe controller with EP mode Add the documentation for the Device Tree binding for the layerscape PCIe controller with EP mode. Signed-off-by: Xiaowei Bao Signed-off-by: Lorenzo Pieralisi Reviewed-by: Minghuan Lian Reviewed-by: Zhiqiang Hou Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 9b2b8d66d1f4..e20ceaab9b38 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -13,6 +13,7 @@ information. Required properties: - compatible: should contain the platform identifier such as: + RC mode: "fsl,ls1021a-pcie" "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" "fsl,ls2088a-pcie" @@ -20,6 +21,8 @@ Required properties: "fsl,ls1046a-pcie" "fsl,ls1043a-pcie" "fsl,ls1012a-pcie" + EP mode: + "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. -- cgit v1.2.3 From f2a9eb975ab2e848af68db26646793f5d9d097e8 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 20 Feb 2019 16:43:03 -0800 Subject: regulator: fan53555: Add support for FAN53526 The FAN53526 differs from the FAN53555 only in that the mode bit in VSEL0/VSEL1 is moved to the CONTROL register, the voltage selector mask is extended by 1 bit and the step is different. So extend the existing fan53555 driver to support FAN53526 as well. Signed-off-by: Bjorn Andersson Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/fan53555.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/fan53555.txt b/Documentation/devicetree/bindings/regulator/fan53555.txt index 54a3f2c80e3a..e7fc045281d1 100644 --- a/Documentation/devicetree/bindings/regulator/fan53555.txt +++ b/Documentation/devicetree/bindings/regulator/fan53555.txt @@ -1,7 +1,8 @@ Binding for Fairchild FAN53555 regulators Required properties: - - compatible: one of "fcs,fan53555", "silergy,syr827", "silergy,syr828" + - compatible: one of "fcs,fan53555", "fcs,fan53526", "silergy,syr827" or + "silergy,syr828" - reg: I2C address Optional properties: -- cgit v1.2.3 From 07b6ce7febbb8185fd6181e9903f98247c4893fd Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Tue, 19 Feb 2019 10:29:57 +0800 Subject: gpio: sprd: Use SoC compatible string instead of wildcard string Use SoC compatible string instead of wildcard string. Reviewed-by: Rob Herring Signed-off-by: Baolin Wang Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt b/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt index 93d98d09d92b..54040a2bfe3a 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt @@ -33,7 +33,7 @@ Required properties: "sprd,sc9860-eic-latch", "sprd,sc9860-eic-async", "sprd,sc9860-eic-sync", - "sprd,sc27xx-eic". + "sprd,sc2731-eic". - reg: Define the base and range of the I/O address space containing the GPIO controller registers. - gpio-controller: Marks the device node as a GPIO controller. @@ -86,7 +86,7 @@ Example: }; pmic_eic: gpio@300 { - compatible = "sprd,sc27xx-eic"; + compatible = "sprd,sc2731-eic"; reg = <0x300>; interrupt-parent = <&sc2731_pmic>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3 From dcab77888da978a1853158ff86b93b5cf7f07d25 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Tue, 29 Jan 2019 17:55:28 +0100 Subject: dt-bindings: pinctrl: Document the i.MX50 IOMUXC binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit AFAICS from the i.MX50 Reference Manual, the i.MX50 IOMUXC works the same as the one in i.MX51, so I copied fsl,imx51-pinctrl.txt and changed the text to imx50. Signed-off-by: Jonathan Neuschäfer Cc: Dong Aisheng Cc: Shawn Guo Reviewed-by: Fabio Estevam Signed-off-by: Linus Walleij --- .../bindings/pinctrl/fsl,imx50-pinctrl.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt new file mode 100644 index 000000000000..6da01d619d33 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt @@ -0,0 +1,32 @@ +* Freescale IMX50 IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx50-iomuxc" +- fsl,pins: two integers array, represents a group of pins mux and config + setting. The format is fsl,pins = , PIN_FUNC_ID is a + pin working on a specific function, CONFIG is the pad setting value like + pull-up for this pin. Please refer to imx50 datasheet for the valid pad + config settings. + +CONFIG bits definition: +PAD_CTL_HVE (1 << 13) +PAD_CTL_HYS (1 << 8) +PAD_CTL_PKE (1 << 7) +PAD_CTL_PUE (1 << 6) +PAD_CTL_PUS_100K_DOWN (0 << 4) +PAD_CTL_PUS_47K_UP (1 << 4) +PAD_CTL_PUS_100K_UP (2 << 4) +PAD_CTL_PUS_22K_UP (3 << 4) +PAD_CTL_ODE (1 << 3) +PAD_CTL_DSE_LOW (0 << 1) +PAD_CTL_DSE_MED (1 << 1) +PAD_CTL_DSE_HIGH (2 << 1) +PAD_CTL_DSE_MAX (3 << 1) +PAD_CTL_SRE_FAST (1 << 0) +PAD_CTL_SRE_SLOW (0 << 0) + +Refer to imx50-pinfunc.h in device tree source folder for all available +imx50 PIN_FUNC_ID. -- cgit v1.2.3 From 037a474f6144544848da72bfda80776686084a13 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Tue, 22 Jan 2019 09:31:46 +0000 Subject: dt-bindings: imx: Add clock binding doc for imx8mm Add the clock binding doc for i.MX8MM. Signed-off-by: Bai Ping Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/imx8mm-clock.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx8mm-clock.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/imx8mm-clock.txt b/Documentation/devicetree/bindings/clock/imx8mm-clock.txt new file mode 100644 index 000000000000..8e4ab9e619a1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8mm-clock.txt @@ -0,0 +1,29 @@ +* Clock bindings for NXP i.MX8M Mini + +Required properties: +- compatible: Should be "fsl,imx8mm-ccm" +- reg: Address and length of the register set +- #clock-cells: Should be <1> +- clocks: list of clock specifiers, must contain an entry for each required + entry in clock-names +- clock-names: should include the following entries: + - "osc_32k" + - "osc_24m" + - "clk_ext1" + - "clk_ext2" + - "clk_ext3" + - "clk_ext4" + +clk: clock-controller@30380000 { + compatible = "fsl,imx8mm-ccm"; + reg = <0x0 0x30380000 0x0 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; +}; + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h +for the full list of i.MX8M Mini clock IDs. -- cgit v1.2.3 From 0c8c53e033d278cad09a81ec1c46a401a6a6b1af Mon Sep 17 00:00:00 2001 From: Edgar Bernardi Righi Date: Tue, 15 Jan 2019 09:03:36 +0530 Subject: dt-bindings: clock: Add DT bindings for Actions Semi S500 CMU Add devicetree bindings for Actions Semi S500 Clock Management Unit. Signed-off-by: Edgar Bernardi Righi [Mani: Documented S500 CMU compatible] Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring [sboyd@kernel.org: Fix SPDX comment style in header file] Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/actions,owl-cmu.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt index 2ef86ae96df8..d19885b7c73f 100644 --- a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt +++ b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt @@ -2,13 +2,14 @@ The Actions Semi Owl Clock Management Unit generates and supplies clock to various controllers within the SoC. The clock binding described here is -applicable to S900 and S700 SoC's. +applicable to S900, S700 and S500 SoC's. Required Properties: - compatible: should be one of the following, "actions,s900-cmu" "actions,s700-cmu" + "actions,s500-cmu" - reg: physical base address of the controller and length of memory mapped region. - clocks: Reference to the parent clocks ("hosc", "losc") @@ -19,8 +20,8 @@ Each clock is assigned an identifier, and client nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in corresponding -dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be -used in device tree sources. +dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or +actions,s500-cmu.h header and can be used in device tree sources. External clocks: -- cgit v1.2.3 From e12ba23254d81b0158a8bcc5f0c43c9fedb38a91 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Wed, 20 Feb 2019 11:40:40 +0000 Subject: dt-binding: irq: imx-irqsteer: Use irq number instead of group number Not all 64 interrupts may be used in one group. e.g. most irqsteer in imx8qxp and imx8qm subsystems supports only 32 interrupts. As the IP integration parameters are Channel number and interrupts number, let's use fsl,irqs-num to represents how many interrupts supported by this irqsteer channel. Note this will break the compatibility of old binding. As the original fsl,irq-groups was born out of a misunderstanding of the HW config options and we are not aware of any users of the current binding. And the old binding was just published in recent months, so it's worth to change now to avoid confusing in the future. Cc: Rob Herring Cc: Shawn Guo Cc: devicetree@vger.kernel.org Reviewed-by: Lucas Stach Signed-off-by: Dong Aisheng Signed-off-by: Marc Zyngier --- .../devicetree/bindings/interrupt-controller/fsl,irqsteer.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt index 45790ce6f5b9..6d0a41b54943 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt @@ -16,8 +16,8 @@ Required properties: - #interrupt-cells: Specifies the number of cells needed to encode an interrupt source. The value must be 1. - fsl,channel: The output channel that all input IRQs should be steered into. -- fsl,irq-groups: Number of IRQ groups managed by this controller instance. - Each group manages 64 input interrupts. +- fsl,num-irqs: Number of input interrupts of this channel. + Should be multiple of 32 input interrupts and up to 512 interrupts. Example: @@ -28,7 +28,7 @@ Example: clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; clock-names = "ipg"; fsl,channel = <0>; - fsl,irq-groups = <1>; + fsl,num-irqs = <64>; interrupt-controller; #interrupt-cells = <1>; }; -- cgit v1.2.3 From e482c01dc73c23b2b8293cb43f633efddc87b36a Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Wed, 20 Feb 2019 11:40:43 +0000 Subject: dt-bindings: irq: imx-irqsteer: Add multi output interrupts support One irqsteer channel can support up to 8 output interrupts. Cc: Rob Herring Cc: Shawn Guo Cc: devicetree@vger.kernel.org Reviewed-by: Lucas Stach Signed-off-by: Dong Aisheng Signed-off-by: Marc Zyngier --- .../devicetree/bindings/interrupt-controller/fsl,irqsteer.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt index 6d0a41b54943..582991c426ee 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt @@ -6,8 +6,9 @@ Required properties: - "fsl,imx8m-irqsteer" - "fsl,imx-irqsteer" - reg: Physical base address and size of registers. -- interrupts: Should contain the parent interrupt line used to multiplex the - input interrupts. +- interrupts: Should contain the up to 8 parent interrupt lines used to + multiplex the input interrupts. They should be specified sequentially + from output 0 to 7. - clocks: Should contain one clock for entry in clock-names see Documentation/devicetree/bindings/clock/clock-bindings.txt - clock-names: -- cgit v1.2.3 From a0d183c329165fdd77becba1f58bbe22a5f72ae9 Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Wed, 20 Feb 2019 20:43:22 +0530 Subject: ALSA: hda/tegra: property for card name An optional property "nvidia,model" is introduced for hda to pass custom name for the sound card. The suffix "-hda" in the name passed is useful to distinguish between multiple cards available for a platform. When the property is not specified, default name("tegra-hda") mentioned in hda driver is used. This property can be added in platform specific file of the board and card name can relate to the board in use. Signed-off-by: Sameer Pujar Reviewed-by: Jonathan Hunter Signed-off-by: Takashi Iwai --- Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.txt index 44d27456e8a4..21cd310963b1 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.txt +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.txt @@ -13,6 +13,10 @@ Required properties: See ../reset/reset.txt for details. - reset-names : Must include the following entries: hda, hda2hdmi, hda2codec_2x +Optional properties: +- nvidia,model : The user-visible name of this sound complex. Since the property + is optional, legacy boards can use default name provided in hda driver. + Example: hda@70030000 { @@ -27,4 +31,5 @@ hda@70030000 { <&tegra_car 128>, /* hda2hdmi */ <&tegra_car 111>; /* hda2codec_2x */ reset-names = "hda", "hda2hdmi", "hda2codec_2x"; + nvidia,model = "jetson-tk1-hda"; }; -- cgit v1.2.3 From 78517428a0d5cc071c9933c4371fbbfc5635be4a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 21 Feb 2019 16:44:41 +0100 Subject: gpio: ixp4xx: Add DT bindings This adds DT bindings for the IXP4xx GPIO controller. Cc: devicetree@vger.kernel.org Reviewed-by: Bartosz Golaszewski Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/intel,ixp4xx-gpio.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt new file mode 100644 index 000000000000..8dc41ed99685 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt @@ -0,0 +1,38 @@ +Intel IXP4xx XScale Networking Processors GPIO + +This GPIO controller is found in the Intel IXP4xx processors. +It supports 16 GPIO lines. + +The interrupt portions of the GPIO controller is hierarchical: +the synchronous edge detector is part of the GPIO block, but the +actual enabling/disabling of the interrupt line is done in the +main IXP4xx interrupt controller which has a 1:1 mapping for +the first 12 GPIO lines to 12 system interrupts. + +The remaining 4 GPIO lines can not be used for receiving +interrupts. + +The interrupt parent of this GPIO controller must be the +IXP4xx interrupt controller. + +Required properties: + +- compatible : Should be + "intel,ixp4xx-gpio" +- reg : Should contain registers location and length +- gpio-controller : marks this as a GPIO controller +- #gpio-cells : Should be 2, see gpio/gpio.txt +- interrupt-controller : marks this as an interrupt controller +- #interrupt-cells : a standard two-cell interrupt, see + interrupt-controller/interrupts.txt + +Example: + +gpio0: gpio@c8004000 { + compatible = "intel,ixp4xx-gpio"; + reg = <0xc8004000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +}; -- cgit v1.2.3 From 8743dcf66981ad6b6457356f723f7048ddff6ac8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 4 Feb 2019 09:20:03 +0000 Subject: dt-bindings: timer: renesas, cmt: Document r8a774c0 CMT support Document SoC specific bindings for RZ/G2E (r8a774c0) SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 862a80f0380a..c0594450e9ef 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -32,6 +32,8 @@ Required Properties: - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470. - "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1. - "renesas,r8a774a1-cmt1" for the 48-bit CMT1 device included in r8a774a1. + - "renesas,r8a774c0-cmt0" for the 32-bit CMT0 device included in r8a774c0. + - "renesas,r8a774c0-cmt1" for the 48-bit CMT1 device included in r8a774c0. - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. -- cgit v1.2.3 From 29f970cf670f12d72580662b2f291cf2dc86aaf5 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 4 Feb 2019 09:20:06 +0000 Subject: dt-bindings: timer: renesas: tmu: Document r8a774c0 bindings Document RZ/G2E (R8A774C0) SoC in the Renesas TMU bindings. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,tmu.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.txt b/Documentation/devicetree/bindings/timer/renesas,tmu.txt index 4ddff85837da..13ad07416bdd 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.txt +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.txt @@ -10,6 +10,7 @@ Required Properties: - compatible: must contain one or more of the following: - "renesas,tmu-r8a7740" for the r8a7740 TMU + - "renesas,tmu-r8a774c0" for the r8a774C0 TMU - "renesas,tmu-r8a7778" for the r8a7778 TMU - "renesas,tmu-r8a7779" for the r8a7779 TMU - "renesas,tmu-r8a77970" for the r8a77970 TMU -- cgit v1.2.3 From 2e876b5d9f8dc6b685bc75f5b03b2a984fed63df Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Sun, 17 Feb 2019 21:50:32 +0800 Subject: dt-bindings: timer: mediatek: update bindings for MT7629 SoC Update the binding for MT7629 SoC, which uses fallback compatible to MT6765 SYST, so add more descriptions to distinguish it from the other SoCs that use GPT. Signed-off-by: Ryder Lee Cc: Daniel Lezcano Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/mediatek,mtk-timer.txt | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index 18d4d0166c76..ff7c567a7972 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -1,7 +1,7 @@ -Mediatek Timers +MediaTek Timers --------------- -Mediatek SoCs have two different timers on different platforms, +MediaTek SoCs have two different timers on different platforms, - GPT (General Purpose Timer) - SYST (System Timer) @@ -9,6 +9,7 @@ The proper timer will be selected automatically by driver. Required properties: - compatible should contain: + For those SoCs that use GPT * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT) * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT) * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT) @@ -17,7 +18,11 @@ Required properties: * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT) * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT) * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT) - * "mediatek,mt6765-timer" for MT6765 compatible timers (SYST) + + For those SoCs that use SYST + * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) + * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST) + - reg: Should contain location and length for timer register. - clocks: Should contain system clock. -- cgit v1.2.3 From 2e710fc3917255bc358c69c41b5af3475c7112b8 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Sat, 29 Dec 2018 09:39:34 +0000 Subject: dt-bindings: timer: gpt: update binding doc The i.MX GPT timer driver binding doc is out of date, update it according to current GPT timer driver. Signed-off-by: Anson Huang Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/fsl,imxgpt.txt | 39 ++++++++++++++++++---- 1 file changed, 33 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt index 9809b11f7180..5d8fd5b52598 100644 --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt @@ -2,17 +2,44 @@ Freescale i.MX General Purpose Timer (GPT) Required properties: -- compatible : should be "fsl,-gpt" -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 4 interrupts; one per timer channel. -- clocks : The clocks provided by the SoC to drive the timer. +- compatible : should be one of following: + for i.MX1: + - "fsl,imx1-gpt"; + for i.MX21: + - "fsl,imx21-gpt"; + for i.MX27: + - "fsl,imx27-gpt", "fsl,imx21-gpt"; + for i.MX31: + - "fsl,imx31-gpt"; + for i.MX25: + - "fsl,imx25-gpt", "fsl,imx31-gpt"; + for i.MX50: + - "fsl,imx50-gpt", "fsl,imx31-gpt"; + for i.MX51: + - "fsl,imx51-gpt", "fsl,imx31-gpt"; + for i.MX53: + - "fsl,imx53-gpt", "fsl,imx31-gpt"; + for i.MX6Q: + - "fsl,imx6q-gpt", "fsl,imx31-gpt"; + for i.MX6DL: + - "fsl,imx6dl-gpt"; + for i.MX6SL: + - "fsl,imx6sl-gpt", "fsl,imx6dl-gpt"; + for i.MX6SX: + - "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; +- reg : specifies base physical address and size of the registers. +- interrupts : should be the gpt interrupt. +- clocks : the clocks provided by the SoC to drive the timer, must contain + an entry for each entry in clock-names. +- clock-names : must include "ipg" entry first, then "per" entry. Example: gpt1: timer@10003000 { - compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; + compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; reg = <0x10003000 0x1000>; interrupts = <26>; - clocks = <&clks 46>, <&clks 61>; + clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; }; -- cgit v1.2.3 From 87e0a455960a383a60d9af49ba74fb1c87b20016 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Thu, 21 Feb 2019 15:21:43 +0800 Subject: dt-bindings: timer: add Tegra210 timer The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock (TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic, or watchdog interrupts. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Reviewed-by: Rob Herring Acked-by: Jon Hunter Signed-off-by: Daniel Lezcano --- .../bindings/timer/nvidia,tegra210-timer.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt new file mode 100644 index 000000000000..032cda96fe0d --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt @@ -0,0 +1,36 @@ +NVIDIA Tegra210 timer + +The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit +timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived +from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock +(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic, +or watchdog interrupts. + +Required properties: +- compatible : "nvidia,tegra210-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 14 interrupts; one per each timer channels 0 through + 13. +- clocks : Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + +timer@60005000 { + compatible = "nvidia,tegra210-timer"; + reg = <0x0 0x60005000 0x0 0x400>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_TIMER>; + clock-names = "timer"; +}; -- cgit v1.2.3 From 29d013ad04010e545f6b51f17b629e3047030105 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 22 Feb 2019 14:45:23 +0100 Subject: dt-bindings: hwmon: Add optional regulator support to pwm-fan This adds an optional regulator support (e.g. switchable supply) to the pwm fan binding. Signed-off-by: Stefan Wahren Reviewed-by: Rob Herring Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/pwm-fan.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/pwm-fan.txt b/Documentation/devicetree/bindings/hwmon/pwm-fan.txt index c6d533202d3e..49ca5d83ed13 100644 --- a/Documentation/devicetree/bindings/hwmon/pwm-fan.txt +++ b/Documentation/devicetree/bindings/hwmon/pwm-fan.txt @@ -6,6 +6,9 @@ Required properties: - cooling-levels : PWM duty cycle values in a range from 0 to 255 which correspond to thermal cooling states +Optional properties: +- fan-supply : phandle to the regulator that provides power to the fan + Example: fan0: pwm-fan { compatible = "pwm-fan"; -- cgit v1.2.3 From b5a4c37324049efe0e0199e975e0df9554fa8873 Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Thu, 21 Feb 2019 13:34:40 +0800 Subject: dt-bindings: dmaengine: sprd: Change channel id to slave id for DMA cell specifier For Spreadtrum DMA engine, all channels are equal, which means slave can request any channels with setting a unique slave id to trigger this channel. Thus we can remove the channel id from device tree to assign the channel dynamically, moreover we should add the slave id in device tree. Signed-off-by: Baolin Wang Reviewed-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/sprd-dma.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/sprd-dma.txt b/Documentation/devicetree/bindings/dma/sprd-dma.txt index 7a10fea2e51b..adccea9941f1 100644 --- a/Documentation/devicetree/bindings/dma/sprd-dma.txt +++ b/Documentation/devicetree/bindings/dma/sprd-dma.txt @@ -31,7 +31,7 @@ DMA clients connected to the Spreadtrum DMA controller must use the format described in the dma.txt file, using a two-cell specifier for each channel. The two cells in order are: 1. A phandle pointing to the DMA controller. -2. The channel id. +2. The slave id. spi0: spi@70a00000{ ... -- cgit v1.2.3 From 772bf73ed4dc2e3f0aa549d91dd3f306399d0c09 Mon Sep 17 00:00:00 2001 From: BOUGH CHEN Date: Fri, 28 Dec 2018 03:26:04 +0000 Subject: dt-bindings: mmc: fsl-imx-esdhc: add imx6ull compatible string Add a imx6ull compatible string to be able to manage erratum ERR010450 on i.MX6ULL. Signed-off-by: Haibo Chen Reviewed-by: Rob Herring Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 9201a7d8d7b0..540c65ed9cba 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -15,6 +15,7 @@ Required properties: "fsl,imx6q-usdhc" "fsl,imx6sl-usdhc" "fsl,imx6sx-usdhc" + "fsl,imx6ull-usdhc" "fsl,imx7d-usdhc" "fsl,imx8qxp-usdhc" -- cgit v1.2.3 From 204d94e63e22d4bd4e8ce8af1aeeda2208822cd0 Mon Sep 17 00:00:00 2001 From: Mike Maslenkin Date: Sat, 29 Dec 2018 01:50:52 +0300 Subject: mmc: dt-bindings: omap: Remove duplicate documentation paragraphs Signed-off-by: Mike Maslenkin Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/ti-omap.txt | 28 ----------------------- 1 file changed, 28 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/ti-omap.txt b/Documentation/devicetree/bindings/mmc/ti-omap.txt index 8de579969763..02fd31cf361d 100644 --- a/Documentation/devicetree/bindings/mmc/ti-omap.txt +++ b/Documentation/devicetree/bindings/mmc/ti-omap.txt @@ -24,31 +24,3 @@ Examples: dmas = <&sdma 61 &sdma 62>; dma-names = "tx", "rx"; }; - -* TI MMC host controller for OMAP1 and 2420 - -The MMC Host Controller on TI OMAP1 and 2420 family provides -an interface for MMC, SD, and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the omap mmc driver. - -Note that this driver will not work with omap2430 or later omaps, -please see the omap hsmmc driver for the current omaps. - -Required properties: -- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers -- ti,hwmods: For 2420, must be "msdi", where n is controller - instance starting 1 - -Examples: - - msdi1: mmc@4809c000 { - compatible = "ti,omap2420-mmc"; - ti,hwmods = "msdi1"; - reg = <0x4809c000 0x80>; - interrupts = <83>; - dmas = <&sdma 61 &sdma 62>; - dma-names = "tx", "rx"; - }; - -- cgit v1.2.3 From 7c3cf5c9322bfde8c8038c1428bf8ecd4c58eff3 Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Thu, 10 Jan 2019 14:46:01 -0800 Subject: dt-bindings: mmc: tegra: Add pinctrl for SDMMC drive strengths Add pinctrls for 3V3 and 1V8 pad drive strength configuration for Tegra210 sdmmc. Tegra210 sdmmc has pad configuration registers in pinmux register domain and handled thru pinctrl to pinmux device node. Tegra186 and Tegra194 has pad configuration register with in the SDMMC register domain itself and are handles thru drive strength properties in sdmmc device node. Signed-off-by: Sowjanya Komatineni Reviewed-by: Rob Herring Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index 32b4b4e41923..2cecdc71d94c 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -39,12 +39,16 @@ sdhci@c8000200 { bus-width = <8>; }; -Optional properties for Tegra210 and Tegra186: +Optional properties for Tegra210, Tegra186 and Tegra194: - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8" for controllers supporting multiple voltage levels. The order of names should correspond to the pin configuration states in pinctrl-0 and pinctrl-1. +- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for + Tegra210 where pad config registers are in the pinmux register domain + for pull-up-strength and pull-down-strength values configuration when + using pads at 3V3 and 1V8 levels. - nvidia,only-1-8-v : The presence of this property indicates that the controller operates at a 1.8 V fixed I/O voltage. - nvidia,pad-autocal-pull-up-offset-3v3, -- cgit v1.2.3 From c7fddbd5db5cffd10ed4d18efa20e36803d1899f Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Wed, 23 Jan 2019 11:30:51 -0800 Subject: dt-bindings: mmc: Add supports-cqe property Add supports-cqe optional property for MMC hosts. This property is used to identify the specific host controller supporting command queue. Signed-off-by: Sowjanya Komatineni Reviewed-by: Thierry Reding Reviewed-by: Rob Herring Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mmc.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt index f5a0923b34ca..cdbcfd3a4ff2 100644 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ b/Documentation/devicetree/bindings/mmc/mmc.txt @@ -62,6 +62,8 @@ Optional properties: be referred to mmc-pwrseq-simple.txt. But now it's reused as a tunable delay waiting for I/O signalling and card power supply to be stable, regardless of whether pwrseq-simple is used. Default to 10ms if no available. +- supports-cqe : The presence of this property indicates that the corresponding + MMC host controller supports HW command queue feature. *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line polarity properties, we have to fix the meaning of the "normal" and "inverted" -- cgit v1.2.3 From badf14ceba5589711f149a48f57c342032e55d03 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 28 Jan 2019 22:06:36 +0100 Subject: hwmon: (ad741x) Add DT bindings for Analog Devices AD741x This adds device tree bindings for Analog Devices AD741x as found in Gateway routers. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Reviewed-by: Rob Herring Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/ad741x.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/ad741x.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/ad741x.txt b/Documentation/devicetree/bindings/hwmon/ad741x.txt new file mode 100644 index 000000000000..9102152c8410 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/ad741x.txt @@ -0,0 +1,15 @@ +* AD7416/AD7417/AD7418 Temperature Sensor Device Tree Bindings + +Required properties: +- compatible: one of + "adi,ad7416" + "adi,ad7417" + "adi,ad7418" +- reg: I2C address + +Example: + +hwmon@28 { + compatible = "adi,ad7418"; + reg = <0x28>; +}; -- cgit v1.2.3 From aeb669d41ffabb91b1542f1f802cb12a989fced0 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Fri, 22 Feb 2019 21:13:47 +0100 Subject: MIPS: lantiq: Remove separate GPHY Firmware loader The separate GPHY Firmware loader driver is not used any more, the GPHY firmware is now loaded by the GSWIP switch driver which also makes use of the GPHY. Remove the old unused GPHY firmware loader driver. The GPHY firmware is useless without an Ethernet and switch driver, it should not harm if loading this does not work for system using an old device tree. I am not aware of any vendor separating the device tree from the kernel binary, it should be ok to remove this. The code and the functionality form this separate GPHY firmware loader was added to the gswip driver in commit 14fceff4771e ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") Signed-off-by: Hauke Mehrtens Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: john@phrozen.org Cc: netdev@vger.kernel.org --- .../devicetree/bindings/mips/lantiq/rcu-gphy.txt | 36 ---------------------- .../devicetree/bindings/mips/lantiq/rcu.txt | 18 ----------- 2 files changed, 54 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt deleted file mode 100644 index a0c19bd1ce66..000000000000 --- a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt +++ /dev/null @@ -1,36 +0,0 @@ -Lantiq XWAY SoC GPHY binding -============================ - -This binding describes a software-defined ethernet PHY, provided by the RCU -module on newer Lantiq XWAY SoCs (xRX200 and newer). - -------------------------------------------------------------------------------- -Required properties: -- compatible : Should be one of - "lantiq,xrx200a1x-gphy" - "lantiq,xrx200a2x-gphy" - "lantiq,xrx300-gphy" - "lantiq,xrx330-gphy" -- reg : Addrress of the GPHY FW load address register -- resets : Must reference the RCU GPHY reset bit -- reset-names : One entry, value must be "gphy" or optional "gphy2" -- clocks : A reference to the (PMU) GPHY clock gate - -Optional properties: -- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in - - - -------------------------------------------------------------------------------- -Example for the GPHys on the xRX200 SoCs: - -#include - gphy0: gphy@20 { - compatible = "lantiq,xrx200a2x-gphy"; - reg = <0x20 0x4>; - - resets = <&reset0 31 30>, <&reset1 7 7>; - reset-names = "gphy", "gphy2"; - clocks = <&pmu0 XRX200_PMU_GATE_GPHY>; - lantiq,gphy-mode = ; - }; diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt index 7f0822b4beae..58d51f480c9e 100644 --- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt @@ -26,24 +26,6 @@ Example of the RCU bindings on a xRX200 SoC: ranges = <0x0 0x203000 0x100>; big-endian; - gphy0: gphy@20 { - compatible = "lantiq,xrx200a2x-gphy"; - reg = <0x20 0x4>; - - resets = <&reset0 31 30>, <&reset1 7 7>; - reset-names = "gphy", "gphy2"; - lantiq,gphy-mode = ; - }; - - gphy1: gphy@68 { - compatible = "lantiq,xrx200a2x-gphy"; - reg = <0x68 0x4>; - - resets = <&reset0 29 28>, <&reset1 6 6>; - reset-names = "gphy", "gphy2"; - lantiq,gphy-mode = ; - }; - reset0: reset-controller@10 { compatible = "lantiq,xrx200-reset"; reg = <0x10 4>, <0x14 4>; -- cgit v1.2.3 From 782eff094922ab6e75e8568355c8487686b239f5 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sat, 29 Dec 2018 13:22:11 +0100 Subject: dt-bindings: net: mt76: update binding for mt7603 driver In addition to MT7603E PCI devices, the driver supports the WLAN core on MT7628/MT7688, which needs to be defined in DT. Reviewed-by: Rob Herring Signed-off-by: Felix Fietkau --- .../bindings/net/wireless/mediatek,mt76.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.txt b/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.txt index 0c17a0ec9b7b..7b9a776230c0 100644 --- a/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.txt +++ b/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.txt @@ -4,6 +4,13 @@ This node provides properties for configuring the MediaTek mt76xx wireless device. The node is expected to be specified as a child node of the PCI controller to which the wireless chip is connected. +Alternatively, it can specify the wireless part of the MT7628/MT7688 SoC. +For SoC, use the compatible string "mediatek,mt7628-wmac" and the following +properties: + +- reg: Address and length of the register set for the device. +- interrupts: Main device interrupt + Optional properties: - mac-address: See ethernet.txt in the parent directory @@ -30,3 +37,15 @@ Optional nodes: }; }; }; + +MT7628 example: + +wmac: wmac@10300000 { + compatible = "mediatek,mt7628-wmac"; + reg = <0x10300000 0x100000>; + + interrupt-parent = <&cpuintc>; + interrupts = <6>; + + mediatek,mtd-eeprom = <&factory 0x0000>; +}; -- cgit v1.2.3 From 0e585aabc500693461a0663013319264ba5927f3 Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Wed, 20 Feb 2019 16:44:37 +0900 Subject: dt-bindings: serial: Add Milbeaut serial driver description Add DT bindings document for Milbeaut serial driver. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/serial/milbeaut-uart.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt new file mode 100644 index 000000000000..3d2fb1a7ba94 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt @@ -0,0 +1,21 @@ +Socionext Milbeaut UART controller + +Required properties: +- compatible: should be "socionext,milbeaut-usio-uart". +- reg: offset and length of the register set for the device. +- interrupts: two interrupts specifier. +- interrupt-names: should be "rx", "tx". +- clocks: phandle to the input clock. + +Optional properties: +- auto-flow-control: flow control enable. + +Example: + usio1: usio_uart@1e700010 { + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + auto-flow-control; + }; -- cgit v1.2.3 From 4f430487e208fedb2ce97a7c22911d9719593a1b Mon Sep 17 00:00:00 2001 From: Christian Hohnstaedt Date: Mon, 25 Feb 2019 07:41:05 +0100 Subject: dt-bindings: regulator: add LS2 load switch documentation Document device-tree settings of the load-switch LS2 in the tps65218 device. Signed-off-by: Christian Hohnstaedt Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/tps65218.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/tps65218.txt b/Documentation/devicetree/bindings/regulator/tps65218.txt index 02f0e9bbfbf8..b28e9bd140c1 100644 --- a/Documentation/devicetree/bindings/regulator/tps65218.txt +++ b/Documentation/devicetree/bindings/regulator/tps65218.txt @@ -71,6 +71,11 @@ tps65218: tps65218@24 { regulator-always-on; }; + ls2: regulator-ls2 { + regulator-min-microamp = <100000>; + regulator-max-microamp = <1000000>; + }; + ls3: regulator-ls3 { regulator-min-microvolt = <100000>; regulator-max-microvolt = <1000000>; -- cgit v1.2.3 From 5ee3d33d107feee21bd52697eeab8c7c726062f4 Mon Sep 17 00:00:00 2001 From: Christian Hohnstaedt Date: Mon, 25 Feb 2019 08:15:03 +0100 Subject: dt-bindings: regulator: tps65218: rectify units of LS3 LS3 has a selectable current limit. Change units to microamp in the example. Signed-off-by: Christian Hohnstaedt Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/tps65218.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/tps65218.txt b/Documentation/devicetree/bindings/regulator/tps65218.txt index b28e9bd140c1..54aded3b78e2 100644 --- a/Documentation/devicetree/bindings/regulator/tps65218.txt +++ b/Documentation/devicetree/bindings/regulator/tps65218.txt @@ -77,7 +77,7 @@ tps65218: tps65218@24 { }; ls3: regulator-ls3 { - regulator-min-microvolt = <100000>; - regulator-max-microvolt = <1000000>; + regulator-min-microamp = <100000>; + regulator-max-microamp = <1000000>; }; }; -- cgit v1.2.3 From 7d19261bc0eb35080231f109687d119b183abab8 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 22 Feb 2019 14:53:44 -0800 Subject: dt-bindings: net: btusb: add QCA6174A IDs There are two USB PID/VID variations I've seen for this chip, and I want to utilize the 'interrupts' property defined here already. Signed-off-by: Brian Norris Reviewed-by: Matthias Kaehlcke Reviewed-by: Rob Herring Signed-off-by: Marcel Holtmann --- Documentation/devicetree/bindings/net/btusb.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/btusb.txt b/Documentation/devicetree/bindings/net/btusb.txt index 37d67926dd6d..b1ad6ee68e90 100644 --- a/Documentation/devicetree/bindings/net/btusb.txt +++ b/Documentation/devicetree/bindings/net/btusb.txt @@ -9,6 +9,9 @@ Required properties: (more may be added later) are: "usb1286,204e" (Marvell 8997) + "usbcf3,e300" (Qualcomm QCA6174A) + "usb4ca,301a" (Qualcomm QCA6174A (Lite-On)) + Also, vendors that use btusb may have device additional properties, e.g: Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt -- cgit v1.2.3 From 30097374e6ff6997f6c7104b62d7e2c6d15578f0 Mon Sep 17 00:00:00 2001 From: Philipp Puschmann Date: Wed, 27 Feb 2019 06:51:31 +0000 Subject: dt-bindings: usb: ci-hdrc-usb2: add property power-active-high The i.MX USB controller may drive the usb power line directly, but the polarity depends on the board. Reset state of the polarity is low-active so add this property to allow it to be high-active. Signed-off-by: Philipp Puschmann Reviewed-by: Rob Herring Signed-off-by: Peter Chen Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index adae82385dd6..a254386a91ad 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -93,6 +93,7 @@ i.mx specific properties - over-current-active-low: over current signal polarity is active low. - over-current-active-high: over current signal polarity is active high. It's recommended to specify the over current polarity. +- power-active-high: power signal polarity is active high - external-vbus-divider: enables off-chip resistor divider for Vbus Example: -- cgit v1.2.3 From 43185c3b82c33df351bf6a605ca884c35099b6c6 Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Mon, 25 Feb 2019 06:16:53 +0000 Subject: dt-bindings: net: Add bindings for mdio mux consumers When we use the bindings defined in Documentation/devicetree/bindings/mux to define mdio mux in producer and consumer terms, it results in two devices. one is mux producer and other is mux consumer. Add the bindings needed for Mdio mux consumer devices. Signed-off-by: Pankaj Bansal Signed-off-by: David S. Miller --- .../bindings/net/mdio-mux-multiplexer.txt | 82 ++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/mdio-mux-multiplexer.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.txt b/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.txt new file mode 100644 index 000000000000..534e38058fe0 --- /dev/null +++ b/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.txt @@ -0,0 +1,82 @@ +Properties for an MDIO bus multiplexer consumer device + +This is a special case of MDIO mux when MDIO mux is defined as a consumer +of a mux producer device. The mux producer can be of any type like mmio mux +producer, gpio mux producer or generic register based mux producer. + +Required properties in addition to the MDIO Bus multiplexer properties: + +- compatible : should be "mmio-mux-multiplexer" +- mux-controls : mux controller node to use for operating the mux +- mdio-parent-bus : phandle to the parent MDIO bus. + +each child node of mdio bus multiplexer consumer device represent a mdio +bus. + +for more information please refer +Documentation/devicetree/bindings/mux/mux-controller.txt +and Documentation/devicetree/bindings/net/mdio-mux.txt + +Example: +In below example the Mux producer and consumer are separate nodes. + +&i2c0 { + fpga@66 { // fpga connected to i2c + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", + "simple-mfd"; + reg = <0x66>; + + mux: mux-controller { // Mux Producer + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ + <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */ + }; + }; +}; + +mdio-mux-1 { // Mux consumer + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 0>; + mdio-parent-bus = <&emdio1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@8 { + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + }; + + .. + .. +}; + +mdio-mux-2 { // Mux consumer + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 1>; + mdio-parent-bus = <&emdio2>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + .. + .. +}; -- cgit v1.2.3 From d3ff9f851b7ad892df8dc168f0d589308fb42ac3 Mon Sep 17 00:00:00 2001 From: Kamil Konieczny Date: Fri, 22 Feb 2019 13:21:43 +0100 Subject: dt-bindings: crypto: document Exynos5433 SlimSSS Document DT bindings for crypto Samsung Exynos5433 SlimSSS (Slim Security SubSystem) IP. Signed-off-by: Kamil Konieczny Signed-off-by: Herbert Xu --- .../devicetree/bindings/crypto/samsung-slimsss.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/samsung-slimsss.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/crypto/samsung-slimsss.txt b/Documentation/devicetree/bindings/crypto/samsung-slimsss.txt new file mode 100644 index 000000000000..7ec9a5a7727a --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/samsung-slimsss.txt @@ -0,0 +1,19 @@ +Samsung SoC SlimSSS (Slim Security SubSystem) module + +The SlimSSS module in Exynos5433 SoC supports the following: +-- Feeder (FeedCtrl) +-- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS +-- SHA-1/SHA-256 and (SHA-1/SHA-256)/HMAC + +Required properties: + +- compatible : Should contain entry for slimSSS version: + - "samsung,exynos5433-slim-sss" for Exynos5433 SoC. +- reg : Offset and length of the register set for the module +- interrupts : interrupt specifiers of SlimSSS module interrupts (one feed + control interrupt). + +- clocks : list of clock phandle and specifier pairs for all clocks listed in + clock-names property. +- clock-names : list of device clock input names; should contain "pclk" and + "aclk" for slim-sss in Exynos5433. -- cgit v1.2.3 From d82ca49f3e8aa300819cd6c917cfd65ab998fccf Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 11 Feb 2019 17:51:07 -0800 Subject: dt-bindings: imx6q-pcie: Add "pcie_aux" clock for imx8mq Add a binding for an extra clock required on i.MX8MQ. Signed-off-by: Andrey Smirnov Signed-off-by: Lorenzo Pieralisi Reviewed-by: Lucas Stach Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: Rob Herring Cc: devicetree@vger.kernel.org --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 954f435dca8c..a7f5f5afa0e6 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -56,6 +56,10 @@ Additional required properties for imx7d-pcie and imx8mq-pcie: - "turnoff" - fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node. +Additional required properties for imx8mq-pcie: +- clock-names: Must include the following additional entries: + - "pcie_aux" + Example: pcie@01000000 { -- cgit v1.2.3 From 985e225142cf0cb826401f5448763f13ee712b3a Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 12 Feb 2019 17:08:08 +0530 Subject: dt-bindings: hwmon: Add missing documentation for lm75 Add missing dt-binding documentation for lm75 hwmon sensor. Signed-off-by: Jagan Teki Acked-by: Rob Herring Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/lm75.txt | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/lm75.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/lm75.txt b/Documentation/devicetree/bindings/hwmon/lm75.txt new file mode 100644 index 000000000000..12d8cf7cf592 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/lm75.txt @@ -0,0 +1,37 @@ +*LM75 hwmon sensor. + +Required properties: +- compatible: manufacturer and chip name, one of + "adi,adt75", + "dallas,ds1775", + "dallas,ds75", + "dallas,ds7505", + "gmt,g751", + "national,lm75", + "national,lm75a", + "national,lm75b", + "maxim,max6625", + "maxim,max6626", + "maxim,max31725", + "maxim,max31726", + "maxim,mcp980x", + "st,stds75", + "st,stlm75", + "microchip,tcn75", + "ti,tmp100", + "ti,tmp101", + "ti,tmp105", + "ti,tmp112", + "ti,tmp175", + "ti,tmp275", + "ti,tmp75", + "ti,tmp75c", + +- reg: I2C bus address of the device + +Example: + +sensor@48 { + compatible = "st,stlm75"; + reg = <0x48>; +}; -- cgit v1.2.3 From dac58275308bad60841925429d472a89923fc852 Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Fri, 8 Feb 2019 16:51:33 +0900 Subject: dt-bindings: display: add missing semicolon in example MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing semicolon in example for Sitronix ST7735R display panels. Cc: Rob Herring Cc: Noralf Trønnes Signed-off-by: Akinobu Mita Reviewed-by: Noralf Trønnes Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/display/sitronix,st7735r.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/sitronix,st7735r.txt b/Documentation/devicetree/bindings/display/sitronix,st7735r.txt index f0a5090a3326..cd5c7186890a 100644 --- a/Documentation/devicetree/bindings/display/sitronix,st7735r.txt +++ b/Documentation/devicetree/bindings/display/sitronix,st7735r.txt @@ -20,7 +20,7 @@ Example: backlight: backlight { compatible = "gpio-backlight"; gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; - } + }; ... -- cgit v1.2.3 From 364e8d6f21fa31a8473582d5697a5c480489858d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 12 Feb 2019 16:57:44 +0530 Subject: dt-bindings: Add vendor prefix for techstar Add vendor prefix for techstar, known as Shenzhen Techstar Electronics Co., Ltd. a known producer for LCD modules. Signed-off-by: Jagan Teki Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..615793226010 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -390,6 +390,7 @@ tcl Toby Churchill Ltd. technexion TechNexion technologic Technologic Systems tempo Tempo Semiconductor +techstar Shenzhen Techstar Electronics Co., Ltd. terasic Terasic Inc. thine THine Electronics, Inc. ti Texas Instruments -- cgit v1.2.3 From da36822dec7436bc270d3e24edc89c4ceb708bb8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 12 Feb 2019 17:22:32 +0530 Subject: dt-bindings: Add vendor prefix for feiyang Add vendor prefix for feiyang, known as Shenzhen Fly Young Technology Co.,LTD. a known producer for LCD modules. Signed-off-by: Jagan Teki Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 615793226010..cfb590f9849c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -136,6 +136,7 @@ fairphone Fairphone B.V. faraday Faraday Technology Corporation fastrax Fastrax Oy fcs Fairchild Semiconductor +feiyang Shenzhen Fly Young Technology Co.,LTD. firefly Firefly focaltech FocalTech Systems Co.,Ltd friendlyarm Guangzhou FriendlyARM Computer Tech Co., Ltd -- cgit v1.2.3 From 1d0bf7b9d308c01113eaead72a5578ca6fc01146 Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Wed, 27 Feb 2019 13:51:49 +0900 Subject: dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram The Milbeaut M10V SoC needs a part of sram for smp, so this adds the M10V sram compatible and binding. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt new file mode 100644 index 000000000000..194f6a3c1c1e --- /dev/null +++ b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt @@ -0,0 +1,24 @@ +Milbeaut SRAM for smp bringup + +Milbeaut SoCs use a part of the sram for the bringup of the secondary cores. +Once they get powered up in the bootloader, they stay at the specific part +of the sram. +Therefore the part needs to be added as the sub-node of mmio-sram. + +Required sub-node properties: +- compatible : should be "socionext,milbeaut-smp-sram" + +Example: + + sram: sram@0 { + compatible = "mmio-sram"; + reg = <0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x10000>; + + smp-sram@f100 { + compatible = "socionext,milbeaut-smp-sram"; + reg = <0xf100 0x20>; + }; + }; -- cgit v1.2.3 From fd73403a4862842e89d7d2063cfe9e25bbe9c991 Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Wed, 27 Feb 2019 13:52:05 +0900 Subject: dt-bindings: arm: Add SMP enable-method for Milbeaut This adds a compatible string "socionext,milbeaut-m10v-smp" for Milbeaut M10V to the 32 bit ARM CPU device tree binding. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 298c17b327c6..365dcf384d73 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -228,6 +228,7 @@ patternProperties: - renesas,r9a06g032-smp - rockchip,rk3036-smp - rockchip,rk3066-smp + - socionext,milbeaut-m10v-smp - ste,dbx500-smp cpu-release-addr: -- cgit v1.2.3 From f2a3aa163cf88103c9148ad63f086c6f677220ec Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Wed, 27 Feb 2019 13:52:25 +0900 Subject: dt-bindings: Add documentation for Milbeaut SoCs This adds a DT binding documentation for the M10V and its evaluation board. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring Signed-off-by: Arnd Bergmann --- .../bindings/arm/socionext/milbeaut.yaml | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml new file mode 100644 index 000000000000..aae53fc3cb1e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/milbeaut.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Milbeaut platforms device tree bindings + +maintainers: + - Taichi Sugaya + - Takao Orito + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - socionext,milbeaut-m10v-evb + - const: socionext,sc2000a +... -- cgit v1.2.3 From 172e90878d6ced1e59f2fa8e4469f9fb8077cbc9 Mon Sep 17 00:00:00 2001 From: Sugaya Taichi Date: Wed, 27 Feb 2019 13:52:41 +0900 Subject: dt-bindings: timer: Add Milbeaut M10V timer description Add DT bindings document for Milbeaut M10V timer. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring Signed-off-by: Arnd Bergmann --- .../bindings/timer/socionext,milbeaut-timer.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt new file mode 100644 index 000000000000..ac44c4b67530 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt @@ -0,0 +1,17 @@ +Milbeaut SoCs Timer Controller + +Required properties: + +- compatible : should be "socionext,milbeaut-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : The interrupt of the first timer. +- clocks: phandle to the input clk. + +Example: + +timer { + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20> + interrupts = <0 91 4>; + clocks = <&clk 4>; +}; -- cgit v1.2.3 From 20cc5ddecc42831cea5b9a3bed3254d04826bd55 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Tue, 26 Feb 2019 15:42:23 +0200 Subject: dt-bindings: net: freescale: enetc: Add connection bindings for ENETC ethernet nodes Define connection bindings (external PHY connections and internal links) for the ENETC on-chip ethernet controllers. Signed-off-by: Claudiu Manoil Reviewed-by: Rob Herring Signed-off-by: David S. Miller --- .../devicetree/bindings/net/fsl-enetc.txt | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/fsl-enetc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/fsl-enetc.txt b/Documentation/devicetree/bindings/net/fsl-enetc.txt new file mode 100644 index 000000000000..c812e25ae90f --- /dev/null +++ b/Documentation/devicetree/bindings/net/fsl-enetc.txt @@ -0,0 +1,69 @@ +* ENETC ethernet device tree bindings + +Depending on board design and ENETC port type (internal or +external) there are two supported link modes specified by +below device tree bindings. + +Required properties: + +- reg : Specifies PCIe Device Number and Function + Number of the ENETC endpoint device, according + to parent node bindings. +- compatible : Should be "fsl,enetc". + +1) The ENETC external port is connected to a MDIO configurable phy: + +In this case, the ENETC node should include a "mdio" sub-node +that in turn should contain the "ethernet-phy" node describing the +external phy. Below properties are required, their bindings +already defined in ethernet.txt or phy.txt, under +Documentation/devicetree/bindings/net/*. + +Required: + +- phy-handle : Phandle to a PHY on the MDIO bus. + Defined in ethernet.txt. + +- phy-connection-type : Defined in ethernet.txt. + +- mdio : "mdio" node, defined in mdio.txt. + +- ethernet-phy : "ethernet-phy" node, defined in phy.txt. + +Example: + + ethernet@0,0 { + compatible = "fsl,enetc"; + reg = <0x000000 0 0 0 0>; + phy-handle = <&sgmii_phy0>; + phy-connection-type = "sgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy0: ethernet-phy@2 { + reg = <0x2>; + }; + }; + }; + +2) The ENETC port is an internal port or has a fixed-link external +connection: + +In this case, the ENETC port node defines a fixed link connection, +as specified by "fixed-link.txt", under +Documentation/devicetree/bindings/net/*. + +Required: + +- fixed-link : "fixed-link" node, defined in "fixed-link.txt". + +Example: + ethernet@0,2 { + compatible = "fsl,enetc"; + reg = <0x000200 0 0 0 0>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; -- cgit v1.2.3 From b805c403c859756175fefc213065125da16b808d Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Fri, 1 Mar 2019 10:14:07 +0800 Subject: dt-bindings: net: bluetooth: add support for MediaTek MT7663U and MT7668U UART devices Update binding document with adding support of MT7663U and MT7668U UART devices to mediatek-bluetooth. Reviewed-by: Rob Herring Signed-off-by: Sean Wang Signed-off-by: Marcel Holtmann --- .../devicetree/bindings/net/mediatek-bluetooth.txt | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt b/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt index 14ceb2a5b4e8..41a7dcc80f5b 100644 --- a/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt +++ b/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt @@ -33,3 +33,67 @@ Example: clock-names = "ref"; }; }; + +MediaTek UART based Bluetooth Devices +================================== + +This device is a serial attached device to UART device and thus it must be a +child node of the serial node with UART. + +Please refer to the following documents for generic properties: + + Documentation/devicetree/bindings/serial/slave-device.txt + +Required properties: + +- compatible: Must be + "mediatek,mt7663u-bluetooth": for MT7663U device + "mediatek,mt7668u-bluetooth": for MT7668U device +- vcc-supply: Main voltage regulator +- pinctrl-names: Should be "default", "runtime" +- pinctrl-0: Should contain UART RXD low when the device is powered up to + enter proper bootstrap mode. +- pinctrl-1: Should contain UART mode pin ctrl + +Optional properties: + +- reset-gpios: GPIO used to reset the device whose initial state keeps low, + if the GPIO is missing, then board-level design should be + guaranteed. +- current-speed: Current baud rate of the device whose defaults to 921600 + +Example: + + uart1_pins_boot: uart1-default { + pins-dat { + pinmux = ; + output-low; + }; + }; + + uart1_pins_runtime: uart1-runtime { + pins-dat { + pinmux = , + ; + }; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt7623-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&pericfg CLK_PERI_UART1_SEL>, + <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; + + bluetooth { + compatible = "mediatek,mt7663u-bluetooth"; + vcc-supply = <®_5v>; + reset-gpios = <&pio 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "runtime"; + pinctrl-0 = <&uart1_pins_boot>; + pinctrl-1 = <&uart1_pins_runtime>; + current-speed = <921600>; + }; + }; -- cgit v1.2.3 From 57e883b576dc056f59a5612713b679432db36bfa Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 21 Feb 2019 09:40:44 +0000 Subject: dt-bindings: rtc: add rx8571 compatible The Epson rx8571 is compatible with the Epson rx8581 RTC. The difference between the rx8571 and rx8581 RTC is that the former has 16 bytes more RAM. This renders them incompatible from a DT point of view. Signed-off-by: Biju Das Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/rtc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc.txt b/Documentation/devicetree/bindings/rtc/rtc.txt index fc79d7133218..f4687c68c08c 100644 --- a/Documentation/devicetree/bindings/rtc/rtc.txt +++ b/Documentation/devicetree/bindings/rtc/rtc.txt @@ -48,6 +48,7 @@ dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and dallas,ds1672 Dallas DS1672 Real-time Clock dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE +epson,rx8571 I2C-BUS INTERFACE REAL TIME CLOCK MODULE with Battery Backed RAM epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE emmicro,em3027 EM Microelectronic EM3027 Real-time Clock isil,isl1208 Intersil ISL1208 Low Power RTC with Battery Backed SRAM -- cgit v1.2.3 From a1c0ed24fe9babc53143a5452a0f85cae6e37ba7 Mon Sep 17 00:00:00 2001 From: Tristram Ha Date: Thu, 28 Feb 2019 19:57:22 -0800 Subject: dt-bindings: net: dsa: document additional Microchip KSZ9477 family switches Document additional Microchip KSZ9477 family switches. Show how KSZ8565 switch should be configured as the host port is port 7 instead of port 5. Signed-off-by: Tristram Ha Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/dsa/ksz.txt | 43 +++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dsa/ksz.txt b/Documentation/devicetree/bindings/net/dsa/ksz.txt index 8d58c2a7de39..e7db7268fd0f 100644 --- a/Documentation/devicetree/bindings/net/dsa/ksz.txt +++ b/Documentation/devicetree/bindings/net/dsa/ksz.txt @@ -7,6 +7,11 @@ Required properties: of the following: - "microchip,ksz9477" - "microchip,ksz9897" + - "microchip,ksz9896" + - "microchip,ksz9567" + - "microchip,ksz8565" + - "microchip,ksz9893" + - "microchip,ksz9563" Optional properties: @@ -73,4 +78,42 @@ Ethernet switch connected via SPI to the host, CPU port wired to eth0: }; }; }; + ksz8565: ksz8565@0 { + compatible = "microchip,ksz8565"; + reg = <0>; + + spi-max-frequency = <44000000>; + spi-cpha; + spi-cpol; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + label = "lan1"; + }; + port@1 { + reg = <1>; + label = "lan2"; + }; + port@2 { + reg = <2>; + label = "lan3"; + }; + port@3 { + reg = <3>; + label = "lan4"; + }; + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <ð0>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; }; -- cgit v1.2.3 From 50e6914387ee22e9b06597512f8d49b5cce167fc Mon Sep 17 00:00:00 2001 From: Mathieu Othacehe Date: Tue, 19 Feb 2019 10:58:07 +0100 Subject: dt-bindings: pwm: hibvt: Add hi3559v100 support Add support for hi3559v100-shub-pwm and hisilicon,hi3559v100-pwm platforms. Reviewed-by: Rob Herring Signed-off-by: Mathieu Othacehe Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/pwm-hibvt.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt b/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt index fa7849d67836..daedfef09bb6 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt @@ -5,6 +5,8 @@ Required properties: The SoC specific strings supported including: "hisilicon,hi3516cv300-pwm" "hisilicon,hi3519v100-pwm" + "hisilicon,hi3559v100-shub-pwm" + "hisilicon,hi3559v100-pwm - reg: physical base address and length of the controller's registers. - clocks: phandle and clock specifier of the PWM reference clock. - resets: phandle and reset specifier for the PWM controller reset. -- cgit v1.2.3 From 14101cafe96666f7b2f22712887a405694594cd8 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Mon, 25 Feb 2019 16:44:48 +0000 Subject: pwm: atmel: Add PWM binding for SAM9X60 Add PWM binding for SAM9X60 SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/atmel-pwm.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-pwm.txt index c8c831d7b0d1..591ecdd39c7b 100644 --- a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/atmel-pwm.txt @@ -5,6 +5,7 @@ Required properties: - "atmel,at91sam9rl-pwm" - "atmel,sama5d3-pwm" - "atmel,sama5d2-pwm" + - "microchip,sam9x60-pwm" - reg: physical base address and length of the controller's registers - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of the cells format. -- cgit v1.2.3 From d13af797154f4e033a446ff759431c03e0f832d9 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Thu, 28 Feb 2019 18:52:52 +0800 Subject: dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 Add support for altr,pcie-root-port-2.0. Signed-off-by: Ley Foon Tan Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/altera-pcie.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt index 6c396f17c91a..816b244a221e 100644 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -1,11 +1,13 @@ * Altera PCIe controller Required properties: -- compatible : should contain "altr,pcie-root-port-1.0" +- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" - reg: a list of physical base address and length for TXS and CRA. + For "altr,pcie-root-port-2.0", additional HIP base address and length. - reg-names: must include the following entries: "Txs": TX slave port region "Cra": Control register access region + "Hip": Hard IP region (if "altr,pcie-root-port-2.0") - interrupts: specifies the interrupt source of the parent interrupt controller. The format of the interrupt specifier depends on the parent interrupt controller. -- cgit v1.2.3 From abdd85b6ba7322299d69ab68e1fc6849f6998492 Mon Sep 17 00:00:00 2001 From: Wendy Liang Date: Thu, 21 Feb 2019 16:36:34 -0800 Subject: dt-bindings: mailbox: Add Xilinx IPI Mailbox Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block in ZynqMP SoC used for the communication between various processor systems. Signed-off-by: Wendy Liang Reviewed-by: Rob Herring Signed-off-by: Jassi Brar --- .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 127 +++++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt new file mode 100644 index 000000000000..4438432bfe9b --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt @@ -0,0 +1,127 @@ +Xilinx IPI Mailbox Controller +======================================== + +The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage +messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI +agent owns registers used for notification and buffers for message. + + +-------------------------------------+ + | Xilinx ZynqMP IPI Controller | + +-------------------------------------+ + +--------------------------------------------------+ +ATF | | + | | + | | + +--------------------------+ | + | | + | | + +--------------------------------------------------+ + +------------------------------------------+ + | +----------------+ +----------------+ | +Hardware | | IPI Agent | | IPI Buffers | | + | | Registers | | | | + | | | | | | + | +----------------+ +----------------+ | + | | + | Xilinx IPI Agent Block | + +------------------------------------------+ + + +Controller Device Node: +=========================== +Required properties: +-------------------- +IPI agent node: +- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox" +- interrupt-parent: Phandle for the interrupt controller +- interrupts: Interrupt information corresponding to the + interrupt-names property. +- xlnx,ipi-id: local Xilinx IPI agent ID +- #address-cells: number of address cells of internal IPI mailbox nodes +- #size-cells: number of size cells of internal IPI mailbox nodes + +Internal IPI mailbox node: +- reg: IPI buffers address ranges +- reg-names: Names of the reg resources. It should have: + * local_request_region + - IPI request msg buffer written by local and read + by remote + * local_response_region + - IPI response msg buffer written by local and read + by remote + * remote_request_region + - IPI request msg buffer written by remote and read + by local + * remote_response_region + - IPI response msg buffer written by remote and read + by local +- #mbox-cells: Shall be 1. It contains: + * tx(0) or rx(1) channel +- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is + connected to. + +Optional properties: +-------------------- +- method: The method of accessing the IPI agent registers. + Permitted values are: "smc" and "hvc". Default is + "smc". + +Client Device Node: +=========================== +Required properties: +-------------------- +- mboxes: Standard property to specify a mailbox + (See ./mailbox.txt) +- mbox-names: List of identifier strings for each mailbox + channel. + +Example: +=========================== + zynqmp_ipi { + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = <0 29 4>; + xlnx,ipi-id = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* APU<->RPU0 IPI mailbox controller */ + ipi_mailbox_rpu0: mailbox@ff90400 { + reg = <0xff990400 0x20>, + <0xff990420 0x20>, + <0xff990080 0x20>, + <0xff9900a0 0x20>; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <1>; + }; + /* APU<->RPU1 IPI mailbox controller */ + ipi_mailbox_rpu1: mailbox@ff990440 { + reg = <0xff990440 0x20>, + <0xff990460 0x20>, + <0xff990280 0x20>, + <0xff9902a0 0x20>; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <2>; + }; + }; + rpu0 { + ... + mboxes = <&ipi_mailbox_rpu0 0>, + <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; + rpu1 { + ... + mboxes = <&ipi_mailbox_rpu1 0>, + <&ipi_mailbox_rpu1 1>; + mbox-names = "tx", "rx"; + }; -- cgit v1.2.3 From 830133daec63d450e702e6196cec9f0413164164 Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Tue, 5 Mar 2019 09:29:25 +0100 Subject: dt-bindings: net: stmmac: add phys config properties Add properties to support all Phy config PHY_MODE (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz), PHY wo crystal (50Mhz), No 125Mhz from PHY config. Signed-off-by: Christophe Roullier Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/stm32-dwmac.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt b/Documentation/devicetree/bindings/net/stm32-dwmac.txt index 1341012722aa..3524e80c5e96 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt @@ -24,9 +24,9 @@ Required properties: encompases the glue register, and the offset of the control register. Optional properties: -- clock-names: For MPU family "mac-clk-ck" for PHY without quartz -- st,int-phyclk (boolean) : valid only where PHY do not have quartz and need to be clock - by RCC +- clock-names: For MPU family "eth-ck" for PHY without quartz +- st,eth-clk-sel (boolean) : set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125. +- st,eth-ref-clk-sel (boolean) : set this property in RMII mode when you have PHY without crystal 50MHz and want to select RCC clock instead of ETH_REF_CLK. Example: -- cgit v1.2.3 From 835667999019b71114bec4534fcd6c895ebdcbdb Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Tue, 5 Mar 2019 09:29:27 +0100 Subject: dt-bindings: net: stmmac: remove syscfg clock property Syscfg clock is no more needed. Signed-off-by: Christophe Roullier Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/stm32-dwmac.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt b/Documentation/devicetree/bindings/net/stm32-dwmac.txt index 3524e80c5e96..a90eef11dc46 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt @@ -14,8 +14,7 @@ Required properties: - clock-names: Should be "stmmaceth" for the host clock. Should be "mac-clk-tx" for the MAC TX clock. Should be "mac-clk-rx" for the MAC RX clock. - For MPU family need to add also "ethstp" for power mode clock and, - "syscfg-clk" for SYSCFG clock. + For MPU family need to add also "ethstp" for power mode clock - interrupt-names: Should contain a list of interrupt names corresponding to the interrupts in the interrupts property, if available. Should be "macirq" for the main MAC IRQ -- cgit v1.2.3 From c6873d18cb4a5be9623d468c626b5650451ba44a Mon Sep 17 00:00:00 2001 From: xiaofeis Date: Mon, 11 Mar 2019 14:11:40 +0800 Subject: Documentation: devicetree: add a new optional property for port mac address Add documentation for a new optional property local-mac-address which is described in ethernet.txt. Signed-off-by: xiaofeis Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/dsa/dsa.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.txt b/Documentation/devicetree/bindings/net/dsa/dsa.txt index 35694c0c376b..d66a5292b9d3 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa.txt +++ b/Documentation/devicetree/bindings/net/dsa/dsa.txt @@ -71,6 +71,10 @@ properties, described in binding documents: Documentation/devicetree/bindings/net/fixed-link.txt for details. +- local-mac-address : See + Documentation/devicetree/bindings/net/ethernet.txt + for details. + Example The following example shows three switches on three MDIO busses, @@ -97,6 +101,7 @@ linked into one DSA cluster. port@1 { reg = <1>; label = "lan1"; + local-mac-address = [00 00 00 00 00 00]; }; port@2 { -- cgit v1.2.3 From 24105bf4d10485143f8e26337cda8bcb7f6e6da5 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Tue, 19 Mar 2019 11:02:01 +0000 Subject: dt-bindings: irqchip: renesas-irqc: Document r8a774c0 support Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Marc Zyngier --- Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt index 8de96a4fb2d5..f977ea7617f6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt @@ -16,6 +16,7 @@ Required properties: - "renesas,irqc-r8a7793" (R-Car M2-N) - "renesas,irqc-r8a7794" (R-Car E2) - "renesas,intc-ex-r8a774a1" (RZ/G2M) + - "renesas,intc-ex-r8a774c0" (RZ/G2E) - "renesas,intc-ex-r8a7795" (R-Car H3) - "renesas,intc-ex-r8a7796" (R-Car M3-W) - "renesas,intc-ex-r8a77965" (R-Car M3-N) -- cgit v1.2.3 From fb1eb41a3dd4cfff274c98f3c3324ab329641298 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Fri, 22 Mar 2019 01:05:00 +0100 Subject: dt-bindings: net: dsa: qca8k: fix example In the example, the phy at phy@0 is clashing with the switch0@0 at the same address. Usually, the switches are accessible through pseudo PHYs which in case of the qca8k are located at 0x10 - 0x18. Reviewed-by: Florian Fainelli Signed-off-by: Christian Lamparter Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index bbcb255c3150..5eda99e6c86e 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -55,12 +55,12 @@ Example: reg = <4>; }; - switch0@0 { + switch@10 { compatible = "qca,qca8337"; #address-cells = <1>; #size-cells = <0>; - reg = <0>; + reg = <0x10>; ports { #address-cells = <1>; -- cgit v1.2.3 From 5e07321f3388e6f2b13c43ae9df3e09efa8418e0 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Fri, 22 Mar 2019 01:05:01 +0100 Subject: dt-bindings: net: dsa: qca8k: support internal mdio-bus This patch updates the qca8k's binding to document to the approach for using the internal mdio-bus of the supported qca8k switches. Reviewed-by: Florian Fainelli Signed-off-by: Christian Lamparter Signed-off-by: David S. Miller --- .../devicetree/bindings/net/dsa/qca8k.txt | 69 ++++++++++++++++++++-- 1 file changed, 64 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index 5eda99e6c86e..93a7469e70d4 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -12,10 +12,15 @@ Required properties: Subnodes: The integrated switch subnode should be specified according to the binding -described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of -port and PHY id, each subnode describing a port needs to have a valid phandle -referencing the internal PHY connected to it. The CPU port of this switch is -always port 0. +described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external +mdio-bus each subnode describing a port needs to have a valid phandle +referencing the internal PHY it is connected to. This is because there's no +N:N mapping of port and PHY id. + +Don't use mixed external and internal mdio-bus configurations, as this is +not supported by the hardware. + +The CPU port of this switch is always port 0. A CPU port node has the following optional node: @@ -31,8 +36,9 @@ For QCA8K the 'fixed-link' sub-node supports only the following properties: - 'full-duplex' (boolean, optional), to indicate that full duplex is used. When absent, half duplex is assumed. -Example: +Examples: +for the external mdio-bus configuration: &mdio0 { phy_port1: phy@0 { @@ -108,3 +114,56 @@ Example: }; }; }; + +for the internal master mdio-bus configuration: + + &mdio0 { + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + fixed-link { + speed = 1000; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + label = "wan"; + }; + }; + }; + }; -- cgit v1.2.3 From c4dcd89d20a8fe4009d25660c69396611328cc5e Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 22 Mar 2019 00:04:19 +0100 Subject: i2c: iop3xx: make bindings file name match the driver If we use the "i2c-" prefix for the binding documentation file name, then it should match the file name of the driver, if possible. It is possible for this driver, so rename it. Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-iop3xx.txt | 20 ++++++++++++++++++++ Documentation/devicetree/bindings/i2c/i2c-xscale.txt | 20 -------------------- 2 files changed, 20 insertions(+), 20 deletions(-) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-iop3xx.txt delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-xscale.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-iop3xx.txt b/Documentation/devicetree/bindings/i2c/i2c-iop3xx.txt new file mode 100644 index 000000000000..dcc8390e0d24 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-iop3xx.txt @@ -0,0 +1,20 @@ +i2c Controller on XScale platforms such as IOP3xx and IXP4xx + +Required properties: +- compatible : Must be one of + "intel,iop3xx-i2c" + "intel,ixp4xx-i2c"; +- reg +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties: +- Child nodes conforming to i2c bus binding + +Example: + +i2c@c8011000 { + compatible = "intel,ixp4xx-i2c"; + reg = <0xc8011000 0x18>; + interrupts = <33 IRQ_TYPE_LEVEL_LOW>; +}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-xscale.txt b/Documentation/devicetree/bindings/i2c/i2c-xscale.txt deleted file mode 100644 index dcc8390e0d24..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-xscale.txt +++ /dev/null @@ -1,20 +0,0 @@ -i2c Controller on XScale platforms such as IOP3xx and IXP4xx - -Required properties: -- compatible : Must be one of - "intel,iop3xx-i2c" - "intel,ixp4xx-i2c"; -- reg -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- Child nodes conforming to i2c bus binding - -Example: - -i2c@c8011000 { - compatible = "intel,ixp4xx-i2c"; - reg = <0xc8011000 0x18>; - interrupts = <33 IRQ_TYPE_LEVEL_LOW>; -}; -- cgit v1.2.3 From 94c87527f4e1ebf85936f707ec84ff458f3bbb00 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 22 Mar 2019 00:04:20 +0100 Subject: i2c: mt65xx: make bindings file name match the driver If we use the "i2c-" prefix for the binding documentation file name, then it should match the file name of the driver, if possible. It is possible for this driver, so rename it. Signed-off-by: Wolfram Sang --- .../devicetree/bindings/i2c/i2c-mt65xx.txt | 44 ++++++++++++++++++++++ Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 44 ---------------------- 2 files changed, 44 insertions(+), 44 deletions(-) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-mtk.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt new file mode 100644 index 000000000000..ee4c32454198 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt @@ -0,0 +1,44 @@ +* MediaTek's I2C controller + +The MediaTek's I2C controller is used to interface with I2C devices. + +Required properties: + - compatible: value should be either of the following. + "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701 + "mediatek,mt2712-i2c": for MediaTek MT2712 + "mediatek,mt6577-i2c": for MediaTek MT6577 + "mediatek,mt6589-i2c": for MediaTek MT6589 + "mediatek,mt7622-i2c": for MediaTek MT7622 + "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623 + "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629 + "mediatek,mt8173-i2c": for MediaTek MT8173 + - reg: physical base address of the controller and dma base, length of memory + mapped region. + - interrupts: interrupt number to the cpu. + - clock-div: the fixed value for frequency divider of clock source in i2c + module. Each IC may be different. + - clocks: clock name from clock manager + - clock-names: Must include "main" and "dma", if enable have-pmic need include + "pmic" extra. + +Optional properties: + - clock-frequency: Frequency in Hz of the bus when transfer, the default value + is 100000. + - mediatek,have-pmic: platform can control i2c form special pmic side. + Only mt6589 and mt8135 support this feature. + - mediatek,use-push-pull: IO config use push-pull mode. + +Example: + + i2c0: i2c@1100d000 { + compatible = "mediatek,mt6577-i2c"; + reg = <0x1100d000 0x70>, + <0x11000300 0x80>; + interrupts = ; + clock-frequency = <400000>; + mediatek,have-pmic; + clock-div = <16>; + clocks = <&i2c0_ck>, <&ap_dma_ck>; + clock-names = "main", "dma"; + }; + diff --git a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt deleted file mode 100644 index ee4c32454198..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt +++ /dev/null @@ -1,44 +0,0 @@ -* MediaTek's I2C controller - -The MediaTek's I2C controller is used to interface with I2C devices. - -Required properties: - - compatible: value should be either of the following. - "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701 - "mediatek,mt2712-i2c": for MediaTek MT2712 - "mediatek,mt6577-i2c": for MediaTek MT6577 - "mediatek,mt6589-i2c": for MediaTek MT6589 - "mediatek,mt7622-i2c": for MediaTek MT7622 - "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623 - "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629 - "mediatek,mt8173-i2c": for MediaTek MT8173 - - reg: physical base address of the controller and dma base, length of memory - mapped region. - - interrupts: interrupt number to the cpu. - - clock-div: the fixed value for frequency divider of clock source in i2c - module. Each IC may be different. - - clocks: clock name from clock manager - - clock-names: Must include "main" and "dma", if enable have-pmic need include - "pmic" extra. - -Optional properties: - - clock-frequency: Frequency in Hz of the bus when transfer, the default value - is 100000. - - mediatek,have-pmic: platform can control i2c form special pmic side. - Only mt6589 and mt8135 support this feature. - - mediatek,use-push-pull: IO config use push-pull mode. - -Example: - - i2c0: i2c@1100d000 { - compatible = "mediatek,mt6577-i2c"; - reg = <0x1100d000 0x70>, - <0x11000300 0x80>; - interrupts = ; - clock-frequency = <400000>; - mediatek,have-pmic; - clock-div = <16>; - clocks = <&i2c0_ck>, <&ap_dma_ck>; - clock-names = "main", "dma"; - }; - -- cgit v1.2.3 From 0a96f9ffbfe9446b5c4c67461085236d578248e5 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 22 Mar 2019 00:04:21 +0100 Subject: i2c: stu300: make bindings file name match the driver If we use the "i2c-" prefix for the binding documentation file name, then it should match the file name of the driver, if possible. It is possible for this driver, so rename it. Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt | 15 --------------- Documentation/devicetree/bindings/i2c/i2c-stu300.txt | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt create mode 100644 Documentation/devicetree/bindings/i2c/i2c-stu300.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt b/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt deleted file mode 100644 index bd81a482634f..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt +++ /dev/null @@ -1,15 +0,0 @@ -ST Microelectronics DDC I2C - -Required properties : -- compatible : Must be "st,ddci2c" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: interrupt number to the cpu. -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- Child nodes conforming to i2c bus binding - -Examples : - diff --git a/Documentation/devicetree/bindings/i2c/i2c-stu300.txt b/Documentation/devicetree/bindings/i2c/i2c-stu300.txt new file mode 100644 index 000000000000..bd81a482634f --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-stu300.txt @@ -0,0 +1,15 @@ +ST Microelectronics DDC I2C + +Required properties : +- compatible : Must be "st,ddci2c" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: interrupt number to the cpu. +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties: +- Child nodes conforming to i2c bus binding + +Examples : + -- cgit v1.2.3 From 45dfceb0d14a06eeffe22581eb2996f4ed5225ca Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 22 Mar 2019 00:04:22 +0100 Subject: i2c: sun6i-p2wi: make bindings file name match the driver If we use the "i2c-" prefix for the binding documentation file name, then it should match the file name of the driver, if possible. It is possible for this driver, so rename it. Signed-off-by: Wolfram Sang Acked-by: Maxime Ripard --- .../devicetree/bindings/i2c/i2c-sun6i-p2wi.txt | 41 ++++++++++++++++++++++ .../devicetree/bindings/i2c/i2c-sunxi-p2wi.txt | 41 ---------------------- 2 files changed, 41 insertions(+), 41 deletions(-) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sun6i-p2wi.txt delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi-p2wi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-sun6i-p2wi.txt b/Documentation/devicetree/bindings/i2c/i2c-sun6i-p2wi.txt new file mode 100644 index 000000000000..49df0053347a --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-sun6i-p2wi.txt @@ -0,0 +1,41 @@ + +* Allwinner P2WI (Push/Pull 2 Wire Interface) controller + +Required properties : + + - reg : Offset and length of the register set for the device. + - compatible : Should one of the following: + - "allwinner,sun6i-a31-p2wi" + - interrupts : The interrupt line connected to the P2WI peripheral. + - clocks : The gate clk connected to the P2WI peripheral. + - resets : The reset line connected to the P2WI peripheral. + +Optional properties : + + - clock-frequency : Desired P2WI bus clock frequency in Hz. If not set the +default frequency is 100kHz + +A P2WI may contain one child node encoding a P2WI slave device. + +Slave device properties: + Required properties: + - reg : the I2C slave address used during the initialization + process to switch from I2C to P2WI mode + +Example: + + p2wi@1f03400 { + compatible = "allwinner,sun6i-a31-p2wi"; + reg = <0x01f03400 0x400>; + interrupts = <0 39 4>; + clocks = <&apb0_gates 3>; + clock-frequency = <6000000>; + resets = <&apb0_rst 3>; + + axp221: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-sunxi-p2wi.txt b/Documentation/devicetree/bindings/i2c/i2c-sunxi-p2wi.txt deleted file mode 100644 index 49df0053347a..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-sunxi-p2wi.txt +++ /dev/null @@ -1,41 +0,0 @@ - -* Allwinner P2WI (Push/Pull 2 Wire Interface) controller - -Required properties : - - - reg : Offset and length of the register set for the device. - - compatible : Should one of the following: - - "allwinner,sun6i-a31-p2wi" - - interrupts : The interrupt line connected to the P2WI peripheral. - - clocks : The gate clk connected to the P2WI peripheral. - - resets : The reset line connected to the P2WI peripheral. - -Optional properties : - - - clock-frequency : Desired P2WI bus clock frequency in Hz. If not set the -default frequency is 100kHz - -A P2WI may contain one child node encoding a P2WI slave device. - -Slave device properties: - Required properties: - - reg : the I2C slave address used during the initialization - process to switch from I2C to P2WI mode - -Example: - - p2wi@1f03400 { - compatible = "allwinner,sun6i-a31-p2wi"; - reg = <0x01f03400 0x400>; - interrupts = <0 39 4>; - clocks = <&apb0_gates 3>; - clock-frequency = <6000000>; - resets = <&apb0_rst 3>; - - axp221: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - - /* ... */ - }; - }; -- cgit v1.2.3 From 080a910414659dfd18ffaf60a1e95b96c3f50eab Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 22 Mar 2019 00:04:23 +0100 Subject: i2c: wmt: make bindings file name match the driver If we use the "i2c-" prefix for the binding documentation file name, then it should match the file name of the driver, if possible. It is possible for this driver, so rename it. Signed-off-by: Wolfram Sang --- .../devicetree/bindings/i2c/i2c-vt8500.txt | 24 ---------------------- Documentation/devicetree/bindings/i2c/i2c-wmt.txt | 24 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-vt8500.txt create mode 100644 Documentation/devicetree/bindings/i2c/i2c-wmt.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt deleted file mode 100644 index 94a425eaa6c7..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Wondermedia I2C Controller - -Required properties : - - - compatible : should be "wm,wm8505-i2c" - - reg : Offset and length of the register set for the device - - interrupts : where IRQ is the interrupt number - - clocks : phandle to the I2C clock source - -Optional properties : - - - clock-frequency : desired I2C bus clock frequency in Hz. - Valid values are 100000 and 400000. - Default to 100000 if not specified, or invalid value. - -Example : - - i2c_0: i2c@d8280000 { - compatible = "wm,wm8505-i2c"; - reg = <0xd8280000 0x1000>; - interrupts = <19>; - clocks = <&clki2c0>; - clock-frequency = <400000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-wmt.txt b/Documentation/devicetree/bindings/i2c/i2c-wmt.txt new file mode 100644 index 000000000000..94a425eaa6c7 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-wmt.txt @@ -0,0 +1,24 @@ +* Wondermedia I2C Controller + +Required properties : + + - compatible : should be "wm,wm8505-i2c" + - reg : Offset and length of the register set for the device + - interrupts : where IRQ is the interrupt number + - clocks : phandle to the I2C clock source + +Optional properties : + + - clock-frequency : desired I2C bus clock frequency in Hz. + Valid values are 100000 and 400000. + Default to 100000 if not specified, or invalid value. + +Example : + + i2c_0: i2c@d8280000 { + compatible = "wm,wm8505-i2c"; + reg = <0xd8280000 0x1000>; + interrupts = <19>; + clocks = <&clki2c0>; + clock-frequency = <400000>; + }; -- cgit v1.2.3 From 898a737c8a436b2fcd6dcb0b57775ada2f846a26 Mon Sep 17 00:00:00 2001 From: Erin Lo Date: Mon, 11 Mar 2019 16:54:31 +0800 Subject: dt-bindings: serial: Add compatible for Mediatek MT8183 This adds dt-binding documentation of uart for Mediatek MT8183 SoC Platform. Signed-off-by: Erin Lo Acked-by: Rob Herring Acked-by: Matthias Brugger Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index 742cb470595b..bcfb13194f16 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -16,6 +16,7 @@ Required properties: * "mediatek,mt8127-uart" for MT8127 compatible UARTS * "mediatek,mt8135-uart" for MT8135 compatible UARTS * "mediatek,mt8173-uart" for MT8173 compatible UARTS + * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS * "mediatek,mt6577-uart" for MT6577 and all of the above - reg: The base address of the UART register bank. -- cgit v1.2.3 From d3b018f757560ab5c2bce0e7f46e0c1510d7afd4 Mon Sep 17 00:00:00 2001 From: Carlos Menin Date: Wed, 13 Mar 2019 11:11:26 -0300 Subject: dt-bindings: hwmon: (adc128d818) Specify ti,mode property size By default, cells in DT are 32-bit in size. The driver reads "ti,mode" using the function of_property_read_u8() which causes the value to be read incorrectly in little-endian architectures if the size is not specified. Make it explicit in the binding documentation that this prorperty must be set as a 8-bit value. Signed-off-by: Carlos Menin Reviewed-by: Rob Herring Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/adc128d818.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/adc128d818.txt b/Documentation/devicetree/bindings/hwmon/adc128d818.txt index 08bab0e94d25..d0ae46d7bac3 100644 --- a/Documentation/devicetree/bindings/hwmon/adc128d818.txt +++ b/Documentation/devicetree/bindings/hwmon/adc128d818.txt @@ -26,7 +26,7 @@ Required node properties: Optional node properties: - - ti,mode: Operation mode (see above). + - ti,mode: Operation mode (u8) (see above). Example (operation mode 2): @@ -34,5 +34,5 @@ Example (operation mode 2): adc128d818@1d { compatible = "ti,adc128d818"; reg = <0x1d>; - ti,mode = <2>; + ti,mode = /bits/ 8 <2>; }; -- cgit v1.2.3 From ac0722f23ff5bc1b15e268564a4d56d35cd4a1b5 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 18 Mar 2019 11:05:21 +0100 Subject: dt-bindings: cpu: Fix JSON schema Commit fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for Milbeaut") added support for a new cpu enable-method, but did so using tabulations to ident. This is however invalid in the syntax, and resulted in a failure when trying to use that schemas for validation. Use spaces instead of tabs to indent to fix this. Fixes: fd73403a4862 ("dt-bindings: arm: Add SMP enable-method for Milbeaut") Signed-off-by: Maxime Ripard Reviewed-by: Rob Herring Acked-by: Sugaya Taichi Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/arm/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 365dcf384d73..82dd7582e945 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -228,7 +228,7 @@ patternProperties: - renesas,r9a06g032-smp - rockchip,rk3036-smp - rockchip,rk3066-smp - - socionext,milbeaut-m10v-smp + - socionext,milbeaut-m10v-smp - ste,dbx500-smp cpu-release-addr: -- cgit v1.2.3 From 36ad7022536e0c65f8baeeaa5efde11dec44808a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Wed, 17 Apr 2019 22:09:12 +0200 Subject: of_net: Fix residues after of_get_nvmem_mac_address removal MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I've discovered following discrepancy in the bindings/net/ethernet.txt documentation, where it states following: - nvmem-cells: phandle, reference to an nvmem node for the MAC address; - nvmem-cell-names: string, should be "mac-address" if nvmem is to be.. which is actually misleading and confusing. There are only two ethernet drivers in the tree, cadence/macb and davinci which supports this properties. This nvmem-cell* properties were introduced in commit 9217e566bdee ("of_net: Implement of_get_nvmem_mac_address helper"), but commit afa64a72b862 ("of: net: kill of_get_nvmem_mac_address()") forget to properly clean up this parts. So this patch fixes the documentation by moving the nvmem-cell* properties at the appropriate places. While at it, I've removed unused include as well. Cc: Bartosz Golaszewski Fixes: afa64a72b862 ("of: net: kill of_get_nvmem_mac_address()") Signed-off-by: Petr Štetiar Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/davinci_emac.txt | 2 ++ Documentation/devicetree/bindings/net/ethernet.txt | 2 -- Documentation/devicetree/bindings/net/macb.txt | 4 ++++ 3 files changed, 6 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/davinci_emac.txt b/Documentation/devicetree/bindings/net/davinci_emac.txt index 24c5cdaba8d2..ca83dcc84fb8 100644 --- a/Documentation/devicetree/bindings/net/davinci_emac.txt +++ b/Documentation/devicetree/bindings/net/davinci_emac.txt @@ -20,6 +20,8 @@ Required properties: Optional properties: - phy-handle: See ethernet.txt file in the same directory. If absent, davinci_emac driver defaults to 100/FULL. +- nvmem-cells: phandle, reference to an nvmem node for the MAC address +- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used - ti,davinci-rmii-en: 1 byte, 1 means use RMII - ti,davinci-no-bd-ram: boolean, does EMAC have BD RAM? diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt index cfc376bc977a..2974e63ba311 100644 --- a/Documentation/devicetree/bindings/net/ethernet.txt +++ b/Documentation/devicetree/bindings/net/ethernet.txt @@ -10,8 +10,6 @@ Documentation/devicetree/bindings/phy/phy-bindings.txt. the boot program; should be used in cases where the MAC address assigned to the device by the boot program is different from the "local-mac-address" property; -- nvmem-cells: phandle, reference to an nvmem node for the MAC address; -- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used; - max-speed: number, specifies maximum speed in Mbit/s supported by the device; - max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than the maximum frame size (there's contradiction in the Devicetree diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 174f292d8a3e..8b80515729d7 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -26,6 +26,10 @@ Required properties: Optional elements: 'tsu_clk' - clocks: Phandles to input clocks. +Optional properties: +- nvmem-cells: phandle, reference to an nvmem node for the MAC address +- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used + Optional properties for PHY child node: - reset-gpios : Should specify the gpio for phy reset - magic-packet : If present, indicates that the hardware supports waking -- cgit v1.2.3 From 39420fe04f093c15e1674ef56dbae0df109738ec Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Sat, 20 Apr 2019 18:14:33 +0000 Subject: dt-bindings: add an explanation for internal phy-mode When working on the Allwinner internal PHY, the first work was to use the "internal" mode, but some answer was made my mail on what are really internal mean for PHY. This patch write that in the doc. Signed-off-by: Corentin Labbe Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/ethernet.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt index 2974e63ba311..a68621580584 100644 --- a/Documentation/devicetree/bindings/net/ethernet.txt +++ b/Documentation/devicetree/bindings/net/ethernet.txt @@ -16,7 +16,8 @@ Documentation/devicetree/bindings/phy/phy-bindings.txt. Specification). - phy-mode: string, operation mode of the PHY interface. This is now a de-facto standard property; supported values are: - * "internal" + * "internal" (Internal means there is not a standard bus between the MAC and + the PHY, something proprietary is being used to embed the PHY in the MAC.) * "mii" * "gmii" * "sgmii" -- cgit v1.2.3