From dd240e95f1bee671f58148dea25e3be7cb39b50d Mon Sep 17 00:00:00 2001 From: Laura Nao Date: Mon, 15 Sep 2025 17:19:29 +0200 Subject: dt-bindings: clock: mediatek: Describe MT8196 clock controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce binding documentation for system clocks, functional clocks, and PEXTP0/1 and UFS reset controllers on MediaTek MT8196. This binding also includes a handle to the hardware voter, a fixed-function MCU designed to aggregate votes from the application processor and other remote processors to manage clocks and power domains. The HWV on MT8196/MT6991 is incomplete and requires software to manually enable power supplies, parent clocks, and FENC, as well as write to both the HWV MMIO and the controller registers. Because of these constraints, the HWV cannot be modeled using generic clock, power domain, or interconnect APIs. Instead, a custom phandle is exceptionally used to provide direct, syscon-like register access to drivers. Reviewed-by: Nícolas F. R. A. Prado Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Signed-off-by: Laura Nao Signed-off-by: Stephen Boyd --- .../bindings/clock/mediatek,mt8196-clock.yaml | 112 +++++++++++++++++++++ .../bindings/clock/mediatek,mt8196-sys-clock.yaml | 107 ++++++++++++++++++++ 2 files changed, 219 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml new file mode 100644 index 000000000000..bfdbd2e4a167 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Functional Clock Controller for MT8196 + +maintainers: + - Guangjie Song + - Laura Nao + +description: | + The clock architecture in MediaTek SoCs is structured like below: + PLLs --> + dividers --> + muxes + --> + clock gate + + The device nodes provide clock gate control in different IP blocks. + +properties: + compatible: + items: + - enum: + - mediatek,mt8196-imp-iic-wrap-c + - mediatek,mt8196-imp-iic-wrap-e + - mediatek,mt8196-imp-iic-wrap-n + - mediatek,mt8196-imp-iic-wrap-w + - mediatek,mt8196-mdpsys0 + - mediatek,mt8196-mdpsys1 + - mediatek,mt8196-pericfg-ao + - mediatek,mt8196-pextp0cfg-ao + - mediatek,mt8196-pextp1cfg-ao + - mediatek,mt8196-ufscfg-ao + - mediatek,mt8196-vencsys + - mediatek,mt8196-vencsys-c1 + - mediatek,mt8196-vencsys-c2 + - mediatek,mt8196-vdecsys + - mediatek,mt8196-vdecsys-soc + - mediatek,mt8196-vdisp-ao + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + description: + Reset lines for PEXTP0/1 and UFS blocks. + + mediatek,hardware-voter: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the "Hardware Voter" (HWV), as named in the vendor + documentation for MT8196/MT6991. + + The HWV is a SoC-internal fixed-function MCU used to collect votes from + both the Application Processor and other remote processors within the SoC. + It is intended to transparently enable or disable hardware resources (such + as power domains or clocks) based on internal vote aggregation handled by + the MCU's internal state machine. + + However, in practice, this design is incomplete. While the HWV performs + some internal vote aggregation,software is still required to + - Manually enable power supplies externally, if present and if required + - Manually enable parent clocks via direct MMIO writes to clock controllers + - Enable the FENC after the clock has been ungated via direct MMIO + writes to clock controllers + + As such, the HWV behaves more like a hardware-managed clock reference + counter than a true voter. Furthermore, it is not a separate + controller. It merely serves as an alternative interface to the same + underlying clock or power controller. Actual control still requires + direct access to the controller's own MMIO register space, in + addition to writing to the HWV's MMIO region. + + For this reason, a custom phandle is used here - drivers need to directly + access the HWV MMIO region in a syscon-like fashion, due to how the + hardware is wired. This differs from true hardware voting systems, which + typically do not require custom phandles and rely instead on generic APIs + (clocks, power domains, interconnects). + + The name "hardware-voter" is retained to match vendor documentation, but + this should not be reused or misunderstood as a proper voting mechanism. + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + pericfg_ao: clock-controller@16640000 { + compatible = "mediatek,mt8196-pericfg-ao", "syscon"; + reg = <0x16640000 0x1000>; + mediatek,hardware-voter = <&scp_hwv>; + #clock-cells = <1>; + }; + - | + pextp0cfg_ao: clock-controller@169b0000 { + compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon"; + reg = <0x169b0000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml new file mode 100644 index 000000000000..660ab64f390d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Clock Controller for MT8196 + +maintainers: + - Guangjie Song + - Laura Nao + +description: | + The clock architecture in MediaTek SoCs is structured like below: + PLLs --> + dividers --> + muxes + --> + clock gate + + The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll + provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator. + The topckgen, topckgen_gp2 and vlpckgen provide dividers and muxes which + provide the clock source to other IP blocks. + +properties: + compatible: + items: + - enum: + - mediatek,mt8196-apmixedsys + - mediatek,mt8196-armpll-b-pll-ctrl + - mediatek,mt8196-armpll-bl-pll-ctrl + - mediatek,mt8196-armpll-ll-pll-ctrl + - mediatek,mt8196-apmixedsys-gp2 + - mediatek,mt8196-ccipll-pll-ctrl + - mediatek,mt8196-mfgpll-pll-ctrl + - mediatek,mt8196-mfgpll-sc0-pll-ctrl + - mediatek,mt8196-mfgpll-sc1-pll-ctrl + - mediatek,mt8196-ptppll-pll-ctrl + - mediatek,mt8196-topckgen + - mediatek,mt8196-topckgen-gp2 + - mediatek,mt8196-vlpckgen + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + mediatek,hardware-voter: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the "Hardware Voter" (HWV), as named in the vendor + documentation for MT8196/MT6991. + + The HWV is a SoC-internal fixed-function MCU used to collect votes from + both the Application Processor and other remote processors within the SoC. + It is intended to transparently enable or disable hardware resources (such + as power domains or clocks) based on internal vote aggregation handled by + the MCU's internal state machine. + + However, in practice, this design is incomplete. While the HWV performs + some internal vote aggregation,software is still required to + - Manually enable power supplies externally, if present and if required + - Manually enable parent clocks via direct MMIO writes to clock controllers + - Enable the FENC after the clock has been ungated via direct MMIO + writes to clock controllers + + As such, the HWV behaves more like a hardware-managed clock reference + counter than a true voter. Furthermore, it is not a separate + controller. It merely serves as an alternative interface to the same + underlying clock or power controller. Actual control still requires + direct access to the controller's own MMIO register space, in + addition to writing to the HWV's MMIO region. + + For this reason, a custom phandle is used here - drivers need to directly + access the HWV MMIO region in a syscon-like fashion, due to how the + hardware is wired. This differs from true hardware voting systems, which + typically do not require custom phandles and rely instead on generic APIs + (clocks, power domains, interconnects). + + The name "hardware-voter" is retained to match vendor documentation, but + this should not be reused or misunderstood as a proper voting mechanism. + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + apmixedsys_clk: syscon@10000800 { + compatible = "mediatek,mt8196-apmixedsys", "syscon"; + reg = <0x10000800 0x1000>; + #clock-cells = <1>; + }; + - | + topckgen: syscon@10000000 { + compatible = "mediatek,mt8196-topckgen", "syscon"; + reg = <0x10000000 0x800>; + mediatek,hardware-voter = <&scp_hwv>; + #clock-cells = <1>; + }; + -- cgit v1.2.3 From 793e6b74806eea39da26f2fb7e4b640608d9598d Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Fri, 19 Sep 2025 14:26:42 +0000 Subject: dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible Document the clock controller shipped in Loongson-2K0300 SoC, which generates various clock signals for SoC peripherals. Differing from previous generations of SoCs, LS2K0300 requires a 120MHz external clock input. Signed-off-by: Yao Zi Reviewed-by: Krzysztof Kozlowski Reviewed-by: Yanteng Si Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/loongson,ls2k-clk.yaml | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml index 4f79cdb417ab..c07ad1f85857 100644 --- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - loongson,ls2k0300-clk - loongson,ls2k0500-clk - loongson,ls2k-clk # This is for Loongson-2K1000 - loongson,ls2k2000-clk @@ -24,8 +25,7 @@ properties: maxItems: 1 clocks: - items: - - description: 100m ref + maxItems: 1 clock-names: items: @@ -38,11 +38,23 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h for the full list of Loongson-2 SoC clock IDs. +allOf: + - if: + properties: + compatible: + contains: + const: loongson,ls2k0300-clk + then: + properties: + clock-names: false + else: + required: + - clock-names + required: - compatible - reg - clocks - - clock-names - '#clock-cells' additionalProperties: false -- cgit v1.2.3