From 6974ae5aa23b7f37182da6b66d7f58313a55a88e Mon Sep 17 00:00:00 2001 From: GyoungBo Min Date: Wed, 29 Oct 2025 18:37:28 +0530 Subject: dt-bindings: clock: Add ARTPEC-9 clock controller Add dt-schema for Axis ARTPEC-9 SoC clock controller. The Clock Management Unit (CMU) has a top-level block CMU_CMU which generates clocks for other blocks. Add device-tree binding definitions for following CMU blocks: - CMU_CMU - CMU_BUS - CMU_CORE - CMU_CPUCL - CMU_FSYS0 - CMU_FSYS1 - CMU_IMEM - CMU_PERI Signed-off-by: GyoungBo Min Reviewed-by: Kyunghwan Kim Signed-off-by: Ravi Patel Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251029130731.51305-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/axis,artpec9-clock.yaml | 232 +++++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml b/Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml new file mode 100644 index 000000000000..63442b91e7ac --- /dev/null +++ b/Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml @@ -0,0 +1,232 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/axis,artpec9-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC-9 SoC clock controller + +maintainers: + - Jesper Nilsson + +description: | + ARTPEC-9 clock controller is comprised of several CMU (Clock Management Unit) + units, generating clocks for different domains. Those CMU units are modeled + as separate device tree nodes, and might depend on each other. + The root clock in that root tree is an external clock: OSCCLK (25 MHz). + This external clock must be defined as a fixed-rate clock in dts. + + CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and + dividers, all other clocks of function blocks (other CMUs) are usually + derived from CMU_CMU. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/axis,artpec9-clk.h' header. + +properties: + compatible: + enum: + - axis,artpec9-cmu-cmu + - axis,artpec9-cmu-bus + - axis,artpec9-cmu-core + - axis,artpec9-cmu-cpucl + - axis,artpec9-cmu-fsys0 + - axis,artpec9-cmu-fsys1 + - axis,artpec9-cmu-imem + - axis,artpec9-cmu-peri + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +allOf: + - if: + properties: + compatible: + const: axis,artpec9-cmu-cmu + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + + clock-names: + items: + - const: fin_pll + + - if: + properties: + compatible: + const: axis,artpec9-cmu-bus + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_BUS bus clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: bus + + - if: + properties: + compatible: + const: axis,artpec9-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_CORE main clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: main + + - if: + properties: + compatible: + const: axis,artpec9-cmu-cpucl + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_CPUCL switch clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: switch + + - if: + properties: + compatible: + const: axis,artpec9-cmu-fsys0 + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_FSYS0 bus clock (from CMU_CMU) + - description: CMU_FSYS0 IP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: bus + - const: ip + + - if: + properties: + compatible: + const: axis,artpec9-cmu-fsys1 + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_FSYS1 scan0 clock (from CMU_CMU) + - description: CMU_FSYS1 scan1 clock (from CMU_CMU) + - description: CMU_FSYS1 bus clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: scan0 + - const: scan1 + - const: bus + + - if: + properties: + compatible: + const: axis,artpec9-cmu-imem + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_IMEM ACLK clock (from CMU_CMU) + - description: CMU_IMEM CA5 clock (from CMU_CMU) + - description: CMU_IMEM JPEG clock (from CMU_CMU) + - description: CMU_IMEM SSS clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: aclk + - const: ca5 + - const: jpeg + - const: sss + + - if: + properties: + compatible: + const: axis,artpec9-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_PERI IP clock (from CMU_CMU) + - description: CMU_PERI DISP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: ip + - const: disp + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS1 + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + cmu_fsys1: clock-controller@14c10000 { + compatible = "axis,artpec9-cmu-fsys1"; + reg = <0x0 0x14c10000 0x0 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>, + <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>, + <&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>; + clock-names = "fin_pll", "scan0", "scan1", "bus"; + }; + }; +... -- cgit v1.2.3 From 7b43a16c48fe761480ddb0312e6727d0f5fb0b4a Mon Sep 17 00:00:00 2001 From: Ravi Patel Date: Wed, 19 Nov 2025 18:43:00 +0530 Subject: dt-bindings: arm: axis: Add ARTPEC-9 alfred board Document the Axis ARTPEC-9 SoC binding and the alfred board which uses ARTPEC-9 SoC. Signed-off-by: Ravi Patel Acked-by: Conor Dooley Link: https://patch.msgid.link/20251119131302.79088-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/axis.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentation/devicetree/bindings/arm/axis.yaml index 63e9aca85db7..3062901196a6 100644 --- a/Documentation/devicetree/bindings/arm/axis.yaml +++ b/Documentation/devicetree/bindings/arm/axis.yaml @@ -31,6 +31,12 @@ properties: - axis,artpec8-grizzly - const: axis,artpec8 + - description: Axis ARTPEC-9 SoC board + items: + - enum: + - axis,artpec9-alfred + - const: axis,artpec9 + additionalProperties: true ... -- cgit v1.2.3 From be961cdb8ed3befa81dce118a6a41f0138732d10 Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Sun, 25 Jan 2026 01:35:26 +0530 Subject: dt-bindings: arm: samsung: add compatible for samsung-j7xelte Document the board compatible for Samsung Galaxy J7 (2016), an Exynos7870 device. Signed-off-by: Kaustabh Chakraborty Link: https://patch.msgid.link/20260125-exynos7870-j7xelte-v1-1-5cacc3042c42@disroot.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index f8e20e602c20..711824c0dd7e 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -217,6 +217,7 @@ properties: - enum: - samsung,a2corelte # Samsung Galaxy A2 Core - samsung,j6lte # Samsung Galaxy J6 + - samsung,j7xelte # Samsung Galaxy J7 (2016) - samsung,on7xelte # Samsung Galaxy J7 Prime - const: samsung,exynos7870 -- cgit v1.2.3 From 135b55014109de2e6c8b9c5d52e5cfd7b765315e Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Wed, 4 Mar 2026 22:56:53 +0530 Subject: dt-bindings: arm: samsung: add compatible for samsung-j5y17lte Document board compatible for samsung-j5y17lte (exynos7870) Signed-off-by: Kaustabh Chakraborty Link: https://patch.msgid.link/20260304-exynos7870-j5y17lte-v1-1-eb25902c84c8@disroot.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index 711824c0dd7e..8b53cdedc9ea 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -216,6 +216,7 @@ properties: items: - enum: - samsung,a2corelte # Samsung Galaxy A2 Core + - samsung,j5y17lte # Samsung Galaxy J5 (2017) - samsung,j6lte # Samsung Galaxy J6 - samsung,j7xelte # Samsung Galaxy J7 (2016) - samsung,on7xelte # Samsung Galaxy J7 Prime -- cgit v1.2.3