From 1daabbd6ff20a8b7e87e5eebe74bc7afeb855613 Mon Sep 17 00:00:00 2001 From: Marc Olberding Date: Wed, 26 Nov 2025 16:43:06 -0800 Subject: dt-bindings: arm: aspeed: Add NVIDIA MSX4 board Adds a compatible string for NVIDIA's MSX4 BMC board. Acked-by: Conor Dooley Signed-off-by: Marc Olberding Link: https://patch.msgid.link/20251126-msx1_devicetree-v5-1-e508d13e2dda@nvidia.com [arj: Consistent capitalisation in subject, grammar] Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 9298c1a75dd1..8a190819e066 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -107,6 +107,7 @@ properties: - inventec,transformer-bmc - jabil,rbp-bmc - nvidia,gb200nvl-bmc + - nvidia,msx4-bmc - qcom,dc-scm-v1-bmc - quanta,s6q-bmc - ufispace,ncplite-bmc -- cgit v1.2.3 From 801c03446205af4c94736b4892805c10697e6f61 Mon Sep 17 00:00:00 2001 From: Harini T Date: Thu, 30 Jan 2025 17:32:33 +0530 Subject: dt-bindings: watchdog: xlnx,versal-wwdt: Add optional power-domains property AMD/Xilinx Versal Window Watchdog Timer has its own power domain, so add an optional property to describe it. Signed-off-by: Harini T Acked-by: Conor Dooley Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20250130120233.742879-1-harini.t@amd.com --- Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml b/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml index 14b069599740..fccfc785a077 100644 --- a/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml @@ -32,6 +32,9 @@ properties: clocks: maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - reg -- cgit v1.2.3 From d9465635e051ddc0d9ebb312174ace55d38d2d40 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 24 Oct 2025 17:57:34 +0000 Subject: dt-bindings: rng: add google,gs101-trng compatible Add support for the TRNG found on GS101. It works well with the current exynos850 TRNG support. The TRNG controller can be part of a power domain, allow the relevant property 'power-domains'. Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20251024-gs101-trng-v3-1-5d3403738f39@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/rng/samsung,exynos5250-trng.yaml | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml b/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml index 1a71935d8a19..699831927932 100644 --- a/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml +++ b/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml @@ -12,9 +12,13 @@ maintainers: properties: compatible: - enum: - - samsung,exynos5250-trng - - samsung,exynos850-trng + oneOf: + - enum: + - samsung,exynos5250-trng + - samsung,exynos850-trng + - items: + - const: google,gs101-trng + - const: samsung,exynos850-trng clocks: minItems: 1 @@ -24,6 +28,9 @@ properties: minItems: 1 maxItems: 2 + power-domains: + maxItems: 1 + reg: maxItems: 1 -- cgit v1.2.3 From 411727d9182d7a067fdd16a125d2069f52e8bb7f Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Fri, 14 Nov 2025 12:00:16 +0000 Subject: dt-bindings: soc: samsung: exynos-pmu: remove syscon for google,gs101-pmu Since commit ba5095ebbc7a ("mfd: syscon: Allow syscon nodes without a "syscon" compatible") it is possible to register a regmap without the syscon compatible in the node. Update the bindings for google,gs101-pmu so that the syscon compatible is no longer required. As it isn't really correct to claim we are compatible with syscon (as a mmio regmap created by syscon will not work on gs101). Additionally (with the benefit of hindsight) PMU register writes were never working with a MMIO syscon on gs101, so the ABI break is justified. Signed-off-by: Peter Griffin Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251114-remove-pmu-syscon-compat-v2-1-9496e8c496c7@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 6de47489ee42..936352a6110f 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -34,9 +34,10 @@ select: properties: compatible: oneOf: + - enum: + - google,gs101-pmu - items: - enum: - - google,gs101-pmu - samsung,exynos3250-pmu - samsung,exynos4210-pmu - samsung,exynos4212-pmu -- cgit v1.2.3 From 9f76530e52b51a93643dfd2aa893caf00047a563 Mon Sep 17 00:00:00 2001 From: Georg Gottleuber Date: Thu, 4 Dec 2025 16:52:03 +0100 Subject: dt-bindings: vendor-prefixes: Add prefix for TUXEDO Computers GmbH TUXEDO Computers GmbH is a German supplier for computers. Signed-off-by: Georg Gottleuber Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251204155212.230058-2-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index c7591b2aec2a..07b024dcff90 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1697,6 +1697,8 @@ patternProperties: description: Theobroma Systems Design und Consulting GmbH "^turing,.*": description: Turing Machines, Inc. + "^tuxedo,.*": + description: TUXEDO Computers GmbH "^tyan,.*": description: Tyan Computer Corporation "^tyhx,.*": -- cgit v1.2.3 From 32d68e51bf492580bc2b84adcad8a20427d4b2a0 Mon Sep 17 00:00:00 2001 From: Georg Gottleuber Date: Thu, 4 Dec 2025 16:52:04 +0100 Subject: dt-bindings: arm: qcom: Add TUXEDO Computers device Introduce new binding for the TUXEDO Elite 14 Gen1 laptop with X1E78100 SoC. Signed-off-by: Georg Gottleuber Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251204155212.230058-3-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index d84bd3bca201..52ec9e6bd14d 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1067,6 +1067,12 @@ properties: - const: qcom,x1e78100 - const: qcom,x1e80100 + - items: + - enum: + - tuxedo,elite14gen1 + - const: qcom,x1e78100 + - const: qcom,x1e80100 + - items: - enum: - asus,vivobook-s15 -- cgit v1.2.3 From a4c5af1a94c401e99d7eb22707dd848d54bff80d Mon Sep 17 00:00:00 2001 From: Georg Gottleuber Date: Thu, 4 Dec 2025 16:52:05 +0100 Subject: dt-bindings: vendor-prefixes: Add Medion AG Add Medion AG, a German electronics company, to the list of vendor prefixes. Link: https://www.medion.com/ Signed-off-by: Georg Gottleuber Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251204155212.230058-4-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 07b024dcff90..b7c6c528e018 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -995,6 +995,8 @@ patternProperties: description: Mustek Limited "^mediatek,.*": description: MediaTek Inc. + "^medion,.*": + description: Medion AG "^megachips,.*": description: MegaChips "^mele,.*": -- cgit v1.2.3 From 5851f2a20c60dd5aa39b99e4872e96ce358598b6 Mon Sep 17 00:00:00 2001 From: Georg Gottleuber Date: Thu, 4 Dec 2025 16:52:06 +0100 Subject: dt-bindings: arm: qcom: Add Medion SPRCHRGD device Introduce new binding for the Medion SPRCHRGD 14 S1 notebook with X1E78100 SoC. Signed-off-by: Georg Gottleuber Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251204155212.230058-5-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 52ec9e6bd14d..13ca0cf5ac7e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1069,6 +1069,7 @@ properties: - items: - enum: + - medion,sprchrgd14s1 - tuxedo,elite14gen1 - const: qcom,x1e78100 - const: qcom,x1e80100 -- cgit v1.2.3 From 725ba2d0e0b9ac1f0bc0c0c166db03201feaa203 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Mon, 15 Dec 2025 01:07:21 -0800 Subject: dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards Document the Kaanapali SoC binding and the boards which use it. Acked-by: Krzysztof Kozlowski Signed-off-by: Jingyi Wang Link: https://lore.kernel.org/r/20251215-knp-dts-v4-1-1541bebeb89f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 13ca0cf5ac7e..4eb0a7a9ee4a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -327,6 +327,12 @@ properties: - qcom,ipq9574-ap-al02-c9 - const: qcom,ipq9574 + - items: + - enum: + - qcom,kaanapali-mtp + - qcom,kaanapali-qrd + - const: qcom,kaanapali + - description: Sierra Wireless MangOH Green with WP8548 Module items: - const: swir,mangoh-green-wp8548 -- cgit v1.2.3 From d2091990c5c1da38e9cc41240f03c420743af1bf Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 12 Dec 2025 13:19:18 -0800 Subject: dt-bindings: riscv: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board Append "starfive,jh7110" compatible to VisionFive 2 Lite and VisionFive 2 Lite eMMC boards in the least-compatible end of the list. Appending "starfive,jh7110" reduces the number of compatible strings to check in the OpenSBI platform driver. JH-7110S SoC on these boards is the same as JH-7110 SoC however rated for thermal, voltage, and frequency characteristics for a maximum of 1.25GHz operation. Link: https://lore.kernel.org/lkml/1f96a267-f5c6-498e-a2c4-7a47a73ea7e7@canonical.com/ Suggested-by: Heinrich Schuchardt Signed-off-by: E Shattow Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/starfive.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 9253aab21518..8ba0e10b529a 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -41,6 +41,7 @@ properties: - starfive,visionfive-2-lite - starfive,visionfive-2-lite-emmc - const: starfive,jh7110s + - const: starfive,jh7110 additionalProperties: true -- cgit v1.2.3 From 7beae528ddadd1c3f7d5670f937d993b0f39e0ea Mon Sep 17 00:00:00 2001 From: Joseph Kogut Date: Fri, 5 Dec 2025 12:07:01 +0000 Subject: dt-bindings: arm: rockchip: Add Radxa CM5 IO board Add device tree binding for the Radxa CM5 IO board. This board is based on the rk3588s. Signed-off-by: Joseph Kogut Reviewed-by: Krzysztof Kozlowski Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20251205120703.14721-2-naoki@radxa.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index d496421dbd87..79e99694577e 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -907,6 +907,13 @@ properties: - const: radxa,cm3 - const: rockchip,rk3566 + - description: Radxa Compute Module 5 (CM5) + items: + - enum: + - radxa,cm5-io + - const: radxa,cm5 + - const: rockchip,rk3588s + - description: Radxa CM3 Industrial items: - enum: -- cgit v1.2.3 From 51d857a0168a0101fb691a9191feed771aa78ecd Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 17 Nov 2025 14:09:12 +0100 Subject: dt-bindings: arm: fsl: add TQ-Systems boards MBLS1028A and MBLS1028A-IND Add two mainboards for the TQ-Systems TQMLS1028A SoM, based on the NXP Layerscape LS1028A. Signed-off-by: Matthias Schiffer Reviewed-by: Frank Li Acked-by: Conor Dooley Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 68a2d5fecc43..dfe9fa5c4dbc 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1672,6 +1672,15 @@ properties: - const: kontron,sl28 - const: fsl,ls1028a + - description: + TQ-Systems TQMLS1028A SoM on MBLS1028A/MBLS1028A-IND board + items: + - enum: + - tq,ls1028a-tqmls1028a-mbls1028a + - tq,ls1028a-tqmls1028a-mbls1028a-ind + - const: tq,ls1028a-tqmls1028a + - const: fsl,ls1028a + - description: LS1043A based Boards items: - enum: -- cgit v1.2.3 From def8f003d4f3fa5eac34e0d1ba3ba43b681e116a Mon Sep 17 00:00:00 2001 From: Rogerio Pimentel Date: Sun, 23 Nov 2025 13:14:43 -0500 Subject: dt-bindings: arm: fsl: Add i.MX8MP FRDM board Add device tree compatible string for the i.MX8MP FRDM board. Acked-by: Conor Dooley Signed-off-by: Rogerio Pimentel Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index dfe9fa5c4dbc..b94ce23aa8f6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1099,6 +1099,7 @@ properties: - emcraft,imx8mp-navqp # i.MX8MP Emcraft Systems NavQ+ Kit - fsl,imx8mp-evk # i.MX8MP EVK Board - fsl,imx8mp-evk-revb4 # i.MX8MP EVK Rev B4 Board + - fsl,imx8mp-frdm # i.MX8MP Freedom Board - gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board -- cgit v1.2.3 From 5d96e8677f75d7811aa1a697978961d320161af6 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 12 Dec 2025 09:58:59 +0100 Subject: dt-bindings: power: fsl,imx-gpc: Document address-cells The GPC power controller is an interrupt controllers and can be referenced in interrupt-map properties, e.g. PCIe controller, thus the node should have address-cells property. Signed-off-by: Alexander Stein Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml index 9de3fe73c1eb..d49a5130b87c 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml @@ -38,6 +38,9 @@ properties: reg: maxItems: 1 + "#address-cells": + const: 0 + interrupts: maxItems: 1 -- cgit v1.2.3 From a95260063fb3e01878a28ed23f10241b9e138ae9 Mon Sep 17 00:00:00 2001 From: Fabian Pflug Date: Thu, 18 Dec 2025 12:39:21 +0100 Subject: dt-bindings: arm: fsl: add i.MX93 11x11 FRDM board Add DT compatible string for NXP i.MX93 11x11 FRDM board. Acked-by: Krzysztof Kozlowski Reviewed-by: Daniel Baluta Signed-off-by: Fabian Pflug Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b94ce23aa8f6..20b3a5d6aec2 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1420,6 +1420,7 @@ properties: - enum: - fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board + - fsl,imx93-11x11-frdm # i.MX93 11x11 FRDM Board - fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board - const: fsl,imx93 -- cgit v1.2.3 From 6b4bcef0549e35b777896e5da0ec8af00fa942c1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 22 Dec 2025 09:42:14 +0800 Subject: dt-bindings: arm: fsl: add i.MX952 EVK board Add DT compatible string for NXP i.MX952 EVK board. Acked-by: Krzysztof Kozlowski Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 20b3a5d6aec2..971846c60490 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1438,6 +1438,12 @@ properties: - toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK) - const: fsl,imx95 + - description: i.MX952 based Boards + items: + - enum: + - fsl,imx952-evk # i.MX952 EVK Board + - const: fsl,imx952 + - description: PHYTEC i.MX 95 FPSC based Boards items: - enum: -- cgit v1.2.3 From 6b9d8ef2908727dd80eacb307d6a409963e4dfe5 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 23 Dec 2025 17:28:27 +0100 Subject: dt-bindings: arm: fsl: Add Apalis iMX8QP Add binding documentation for the Apalis iMX8QP SoM mated with Apalis Ixora and Apalis Evaluation board. Apalis iMX8QP is a variant of the Apalis iMX8QM, using an NXP i.MX8QP SoC instead of the i.MX8QM. The two SoCs are pin to pin compatible, with the i.MX8QP being a lower end variant, with a slower GPU and one Cortex A72 core instead of two. The two Apalis SoMs variants share the same schematics and PCB, and the iMX8QP variant exists only on revision V1.1 of board. Link: https://www.nxp.com/products/i.MX8 Link: https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8 Signed-off-by: Francesco Dolcini Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 971846c60490..65a68acf4377 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1334,7 +1334,7 @@ properties: - const: toradex,apalis-imx8 - const: fsl,imx8qm - - description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules + - description: i.MX8QM/i.MX8QP Boards with Toradex Apalis iMX8 V1.1 Modules items: - enum: - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. V1.0/V1.1 Board @@ -1342,7 +1342,9 @@ properties: - toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board - toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board - const: toradex,apalis-imx8-v1.1 - - const: fsl,imx8qm + - enum: + - fsl,imx8qm + - fsl,imx8qp - description: i.MX8QXP based Boards items: -- cgit v1.2.3 From 1e78a43ec0a0e8e7b291b3320844d6a2b2c8d497 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 30 Dec 2025 02:40:34 +0100 Subject: dt-bindings: tpm: Add st,st33tphf2ei2c Add the ST chip st33tphf2ei2c to the supported compatible strings of the TPM TIS I2C schema. The chip is compliant with the TCG PC Client TPM Profile specification. For reference, a databrief is available at: https://www.st.com/resource/en/data_brief/st33tphf2ei2c.pdf Acked-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml b/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml index af7720dc4a12..fdd7fd874e01 100644 --- a/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml +++ b/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml @@ -33,6 +33,7 @@ properties: - infineon,slb9673 - nuvoton,npct75x - st,st33ktpm2xi2c + - st,st33tphf2ei2c - const: tcg,tpm-tis-i2c - description: TPM 1.2 and 2.0 chips with vendor-specific I²C interface -- cgit v1.2.3 From 77e18c63a38bd149f74a53e9c232254431e4de1c Mon Sep 17 00:00:00 2001 From: Joseph Guo Date: Tue, 30 Dec 2025 16:58:53 +0900 Subject: dt-bindings: arm: fsl: Add FRDM-IMX91 board Add the board FRDM-IMX91 in the binding document. Reviewed-by: Daniel Baluta Acked-by: Krzysztof Kozlowski Reviewed-by: Francesco Valla Tested-by: Francesco Valla Signed-off-by: Joseph Guo Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 65a68acf4377..433f555232e9 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1415,6 +1415,7 @@ properties: items: - enum: - fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board + - fsl,imx91-11x11-frdm # FRDM i.MX91 Development Board - const: fsl,imx91 - description: i.MX93 based Boards -- cgit v1.2.3 From 5fc25d64c43c1e25a1a0184a894ab0721c6a524b Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 3 Jan 2026 11:27:05 +0530 Subject: dt-bindings: clock: qcom,x1e80100-gcc: Add missing UFS mux clocks Add some of the UFS symbol rx/tx muxes were not initially described. Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260103-ufs_symbol_clk-v2-1-51828cc76236@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml index 1b15b5070954..881a5dd8d06f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml @@ -62,6 +62,9 @@ properties: - description: USB4_1 PHY max PIPE clock source - description: USB4_2 PHY PCIE PIPE clock source - description: USB4_2 PHY max PIPE clock source + - description: UFS PHY RX Symbol 0 clock source + - description: UFS PHY RX Symbol 1 clock source + - description: UFS PHY TX Symbol 0 clock source power-domains: description: @@ -121,7 +124,10 @@ examples: <&usb4_1_phy_pcie_pipe_clk>, <&usb4_1_phy_max_pipe_clk>, <&usb4_2_phy_pcie_pipe_clk>, - <&usb4_2_phy_max_pipe_clk>; + <&usb4_2_phy_max_pipe_clk>, + <&ufs_phy_rx_symbol_0>, + <&ufs_phy_rx_symbol_1>, + <&ufs_phy_tx_symbol_0>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; #reset-cells = <1>; -- cgit v1.2.3 From 8325294ca9688398ea55843f03ebd1479b9d2334 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= Date: Sat, 20 Dec 2025 16:26:29 +0100 Subject: dt-bindings: arm: qcom: Document Microsoft Surface Pro 11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the compatibles for the Qualcomm-based Microsoft Surface Pro 11, using its Denali codename. The LCD models are using the Qualcomm Snapdragon X1 Plus (X1P64100), the OLED ones are using the Qualcomm Snapdragon X1 Elite (X1E80100). Due to the difference in how the built-in panel is being handled between the OLED variant and LCD one, it is required to have two separate DTBs, so document the compatible string for both variants. Signed-off-by: Jérôme de Bretagne Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251220-surface-sp11-for-next-v6-1-81f7451edb77@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 4eb0a7a9ee4a..c0648c7b8109 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1080,6 +1080,12 @@ properties: - const: qcom,x1e78100 - const: qcom,x1e80100 + - items: + - const: microsoft,denali-lcd + - const: microsoft,denali + - const: qcom,x1p64100 + - const: qcom,x1e80100 + - items: - enum: - asus,vivobook-s15 @@ -1102,6 +1108,11 @@ properties: - const: qcom,hamoa-iot-som - const: qcom,x1e80100 + - items: + - const: microsoft,denali-oled + - const: microsoft,denali + - const: qcom,x1e80100 + - items: - enum: - asus,zenbook-a14-ux3407qa-lcd -- cgit v1.2.3 From 65ce09d2f164a3d91b5802ecd0783aa2c9a208c0 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Thu, 11 Dec 2025 00:32:23 +0530 Subject: dt-bindings: mailbox: qcom: Document SM8750 CPUCP mailbox controller Document CPU Control Processor (CPUCP) mailbox controller for Qualcomm SM8750 SoCs. It is software compatible with X1E80100 CPUCP mailbox controller hence fallback to it. Signed-off-by: Jagadeesh Kona Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20251211-sm8750-cpufreq-v1-1-394609e8d624@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index 9122c3d2dc30..9d99af46e531 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -19,6 +19,7 @@ properties: - items: - enum: - qcom,glymur-cpucp-mbox + - qcom,sm8750-cpucp-mbox - const: qcom,x1e80100-cpucp-mbox - enum: - qcom,x1e80100-cpucp-mbox -- cgit v1.2.3 From 3845bc888660a238920fdba2f85fe284f01fb95f Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 14 Dec 2025 15:51:17 +0100 Subject: dt-bindings: arm: qcom: Add Pixel 3 and 3 XL Document the bindings for the Pixel 3 and 3 XL. Acked-by: Krzysztof Kozlowski Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20251214-pixel-3-v7-1-b1c0cf6f224d@ixit.cz Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c0648c7b8109..c344d92da520 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -906,6 +906,8 @@ properties: - items: - enum: + - google,blueline + - google,crosshatch - huawei,planck - lenovo,yoga-c630 - lg,judyln -- cgit v1.2.3 From 640565d3f3654b7e8848c5bcf01843f04bfa769a Mon Sep 17 00:00:00 2001 From: Hongyang Zhao Date: Wed, 26 Nov 2025 00:07:02 +0800 Subject: dt-bindings: arm: qcom: Add Thundercomm RUBIK Pi 3 Add compatible for the Thundercomm RUBIK Pi 3 board, which is based on the Qualcomm Dragonwing QCS6490 SoC. Reviewed-by: Roger Shimizu Acked-by: Krzysztof Kozlowski Signed-off-by: Hongyang Zhao Link: https://lore.kernel.org/r/20251126-rubikpi-next-20251125-v7-1-e46095b80529@thundersoft.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c344d92da520..acba980bdf4a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -354,6 +354,7 @@ properties: - qcom,qcs6490-rb3gen2 - radxa,dragon-q6a - shift,otter + - thundercomm,rubikpi3 - const: qcom,qcm6490 - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform -- cgit v1.2.3 From d16ffac771715a8c94611b6f8088a3e800bcf5bf Mon Sep 17 00:00:00 2001 From: Riccardo Mereu Date: Thu, 20 Nov 2025 16:58:20 +0100 Subject: dt-bindings: vendor-prefixes: Add Arduino name Add entry for Arduino SRL (https://arduino.cc) Signed-off-by: Riccardo Mereu Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251120155825.121483-2-r.mereu.kernel@arduino.cc Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b7c6c528e018..2de0af95f5e6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -158,6 +158,8 @@ patternProperties: description: Arctic Sand "^arcx,.*": description: arcx Inc. / Archronix Inc. + "^arduino,.*": + description: Arduino SRL "^argon40,.*": description: Argon 40 Technologies Limited "^ariaboard,.*": -- cgit v1.2.3 From 311d173da672397a58498841299ec613ff9eb96b Mon Sep 17 00:00:00 2001 From: Riccardo Mereu Date: Thu, 20 Nov 2025 16:58:23 +0100 Subject: dt-bindings: arm: qcom: Add arduino imola, UnoQ codename MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document Arduino imola, UnoQ codename. Arduino UnoQ combines Qualcomm Dragonwing™ QRB2210 microprocessor with STMicroelectronics STM32U585 microcontroller. Signed-off-by: Riccardo Mereu Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251120155825.121483-5-r.mereu.kernel@arduino.cc Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index acba980bdf4a..cade15d098bc 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -342,6 +342,7 @@ properties: - description: Qualcomm Technologies, Inc. Robotics RB1 items: - enum: + - arduino,imola - qcom,qrb2210-rb1 - const: qcom,qrb2210 - const: qcom,qcm2290 -- cgit v1.2.3 From d88771fda13f2e97a056d471b7b7c11bd17da148 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:28 +0900 Subject: dt-bindings: arm: qcom: Add Milos and The Fairphone (Gen. 6) Document the Milos-based The Fairphone (Gen. 6) smartphone. Acked-by: Rob Herring (Arm) Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-4-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index cade15d098bc..d48c625d3fc4 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -61,6 +61,11 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 + - items: + - enum: + - fairphone,fp6 + - const: qcom,milos + - items: - enum: - microsoft,dempsey -- cgit v1.2.3 From a1823b88d35f1bf04ec4e4f86b9206f699b362d0 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Mon, 29 Dec 2025 04:58:37 +0000 Subject: dt-bindings: arm: rockchip: fix description for Radxa CM3I "Radxa CM3I" is the correct name[1], so fix the description. [1] https://dl.radxa.com/cm3i/docs/hw/radxa_cm3i_product_brief.pdf Signed-off-by: FUKAUMI Naoki Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251229045838.2917-1-naoki@radxa.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 79e99694577e..410a9715a0fc 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -914,7 +914,7 @@ properties: - const: radxa,cm5 - const: rockchip,rk3588s - - description: Radxa CM3 Industrial + - description: Radxa CM3I items: - enum: - radxa,e25 -- cgit v1.2.3 From fc808f80cf298caaa403755ca808cf650844f2f5 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Mon, 29 Dec 2025 04:58:38 +0000 Subject: dt-bindings: arm: rockchip: fix description for Radxa CM5 "Radxa CM5" is the correct name[1], so fix the description. While at it, move the CM5 entry after the CM3I. [1] https://dl.radxa.com/cm5/radxa_cm5_product_brief.pdf Signed-off-by: FUKAUMI Naoki Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251229045838.2917-2-naoki@radxa.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 410a9715a0fc..59a7aed538b4 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -907,13 +907,6 @@ properties: - const: radxa,cm3 - const: rockchip,rk3566 - - description: Radxa Compute Module 5 (CM5) - items: - - enum: - - radxa,cm5-io - - const: radxa,cm5 - - const: rockchip,rk3588s - - description: Radxa CM3I items: - enum: @@ -921,6 +914,13 @@ properties: - const: radxa,cm3i - const: rockchip,rk3568 + - description: Radxa CM5 + items: + - enum: + - radxa,cm5-io + - const: radxa,cm5 + - const: rockchip,rk3588s + - description: Radxa E20C items: - const: radxa,e20c -- cgit v1.2.3 From 1b3cadbd185a6e8681c3b3b6578d7cf3ea4ca47d Mon Sep 17 00:00:00 2001 From: Peter Shen Date: Fri, 19 Dec 2025 17:16:31 +0800 Subject: dt-bindings: arm: aspeed: Add compatible for Facebook Anacapa BMC This patch adds the compatible string for the Facebook Anacapa BMC which uses an Aspeed AST2600 SoC. This is required before adding the board's device tree source file. Signed-off-by: Peter Shen Acked-by: Krzysztof Kozlowski [arj: Insert provided Acked-by tag from Krzysztof, drop misspelled one] Link: https://lore.kernel.org/linux-aspeed/259e917f-0570-40d6-983f-bfe9d77444a7@kernel.org/ Link: https://patch.msgid.link/20251219091632.1598603-2-sjg168@gmail.com Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 8a190819e066..ba59bfd699da 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -80,6 +80,7 @@ properties: - aspeed,ast2600-evb - aspeed,ast2600-evb-a1 - asus,x4tf-bmc + - facebook,anacapa-bmc - facebook,bletchley-bmc - facebook,catalina-bmc - facebook,clemente-bmc -- cgit v1.2.3 From c4f6b5d254ef060ba92f060e2354fc03cc0b2ba6 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Thu, 18 Dec 2025 09:18:13 -0700 Subject: dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 board Document ASRock Rack ALTRAD8 (ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q) compatibles. Signed-off-by: Rebecca Cran Acked-by: Conor Dooley Reviewed-by: Tan Siewert Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20251218161816.38155-2-rebecca@bsdio.com [arj: Drop erroneous Tested-by tag from Tan] Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index ba59bfd699da..f9925a14680e 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -34,6 +34,7 @@ properties: - amd,ethanolx-bmc - ampere,mtjade-bmc - aspeed,ast2500-evb + - asrock,altrad8-bmc - asrock,e3c246d4i-bmc - asrock,e3c256d4i-bmc - asrock,romed8hm3-bmc -- cgit v1.2.3 From a7a53f7482f96f88d6ab2064828f6f6bdb93c43e Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 3 Dec 2025 22:20:37 +0100 Subject: dt-bindings: vendor-prefixes: Add Ezurio LLC Ezurio is the new name of Laird Connectivity after it acquired Boundary Devices. Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index c7591b2aec2a..26e6935e5115 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -555,6 +555,8 @@ patternProperties: description: Exegin Technologies Limited "^ezchip,.*": description: EZchip Semiconductor + "^ezurio,.*": + description: Ezurio LLC "^facebook,.*": description: Facebook "^fairchild,.*": -- cgit v1.2.3 From 07a4700f95745671e8f257d56db6aaf244350111 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 3 Dec 2025 22:20:38 +0100 Subject: dt-bindings: arm: mediatek: Add Ezurio Tungsten entries Add device tree bindings support for the Ezurio Tungsten 510 (MT8370) SMARC [1] / Ezurio Tungsten 700 (MT8390) SMARC [2] + Universal SMARC carrier board [3]. [1] https://www.ezurio.com/product/tungsten510-smarc [2] https://www.ezurio.com/product/tungsten700-smarc [3] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 718d732174b9..382d0eb4d0af 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -438,12 +438,14 @@ properties: - const: mediatek,mt8365 - items: - enum: + - ezurio,mt8370-tungsten-smarc - grinn,genio-510-sbc - mediatek,mt8370-evk - const: mediatek,mt8370 - const: mediatek,mt8188 - items: - enum: + - ezurio,mt8390-tungsten-smarc - grinn,genio-700-sbc - mediatek,mt8390-evk - const: mediatek,mt8390 -- cgit v1.2.3 From d9802af199ad4e9a498879e4cb73763bddd4ae76 Mon Sep 17 00:00:00 2001 From: Horatiu Vultur Date: Mon, 8 Dec 2025 09:35:44 +0100 Subject: dt-bindings: arm: at91: add lan966 pcb8385 board Add documentation for Microchip LAN9668 PCB8385 Acked-by: Rob Herring (Arm) Reviewed-by: Claudiu Beznea Signed-off-by: Horatiu Vultur Link: https://lore.kernel.org/r/20251208083545.3642168-2-horatiu.vultur@microchip.com Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 3a34b7a2e8d4..68d306d17c2a 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -235,9 +235,11 @@ properties: - const: microchip,lan9662 - const: microchip,lan966 - - description: Microchip LAN9668 PCB8290 Evaluation Board. + - description: Microchip LAN9668 Evaluation Board. items: - - const: microchip,lan9668-pcb8290 + - enum: + - microchip,lan9668-pcb8290 + - microchip,lan9668-pcb8385 - const: microchip,lan9668 - const: microchip,lan966 -- cgit v1.2.3 From 5d719a4703566267492129d13516d87066f288f8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 27 Oct 2025 23:56:35 +0200 Subject: dt-bindings: arm: rockchip: Add Orange Pi CM5 Base The Orange Pi CM5 Base board is a carrier board for the Orange Pi CM5 compute module. It has 3 ethernet ports, 2 USB ports, one HDMI output and 4 CSI-2 inputs. Signed-off-by: Laurent Pinchart Acked-by: Conor Dooley Link: https://patch.msgid.link/20251027215637.20715-2-laurent.pinchart@ideasonboard.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 59a7aed538b4..c9b078be3a90 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1306,6 +1306,12 @@ properties: - xunlong,orangepi-5b - const: rockchip,rk3588s + - description: Xunlong Orange Pi CM5 + items: + - const: xunlong,orangepi-cm5-base + - const: xunlong,orangepi-cm5 + - const: rockchip,rk3588s + - description: Zkmagic A95X Z2 items: - const: zkmagic,a95x-z2 -- cgit v1.2.3 From 01a08fd967301e75b2a9350b28a3f09fa2c3b838 Mon Sep 17 00:00:00 2001 From: Gary Yang Date: Sat, 10 Jan 2026 17:34:05 +0800 Subject: dt-bindings: arm: cix: add OrangePi 6 Plus board OrangePi 6 Plus adopts CIX CD8180/CD8160 SoC, built-in 12-core 64-bit processor + NPU processor,integrated graphics processor, equipped with 16GB/32GB/64GB LPDDR5, and provides two M.2 KEY-M interfaces 2280 for NVMe SSD,as well as SPI FLASH and TF slots to meet the needs of fast read/write and high-capacity storage Reviewed-by: Krzysztof Kozlowski Signed-off-by: Gary Yang Link: https://lore.kernel.org/r/20260110093406.2700505-2-gary.yang@cixtech.com Signed-off-by: Peter Chen --- Documentation/devicetree/bindings/arm/cix.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/cix.yaml b/Documentation/devicetree/bindings/arm/cix.yaml index 114dab4bc4d2..21e66df7f696 100644 --- a/Documentation/devicetree/bindings/arm/cix.yaml +++ b/Documentation/devicetree/bindings/arm/cix.yaml @@ -16,9 +16,11 @@ properties: compatible: oneOf: - - description: Radxa Orion O6 + - description: Sky1 based boards items: - - const: radxa,orion-o6 + - enum: + - radxa,orion-o6 # Radxa Orion O6 board + - xunlong,orangepi-6-plus # Xunlong orangepi 6 plus board - const: cix,sky1 additionalProperties: true -- cgit v1.2.3 From ae2208dfa2ac3872f2a0d4c72f1a29fcce7b56a8 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 4 Jan 2026 20:14:47 +0100 Subject: dt-bindings: arm: rockchip: add TS133 to RK356x-based QNAP NAS devices QNAP builds a number of variants of the RK356x-based NAS design. Add the 1-bay TS133 variant. This one is a tiny bit special as it is based around the RK3566 variant of the mostly similar RK3566/RK3568 SoCs. Acked-by: Rob Herring (Arm) Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260104191448.2693309-5-heiko@sntech.de --- Documentation/devicetree/bindings/arm/rockchip.yaml | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index c9b078be3a90..670d743aa9da 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -894,11 +894,15 @@ properties: - const: rockchip,rk3568 - description: QNAP TS-x33 NAS devices - items: - - enum: - - qnap,ts233 - - qnap,ts433 - - const: rockchip,rk3568 + oneOf: + - items: + - const: qnap,ts133 + - const: rockchip,rk3566 + - items: + - enum: + - qnap,ts233 + - qnap,ts433 + - const: rockchip,rk3568 - description: Radxa Compute Module 3 (CM3) items: -- cgit v1.2.3 From 90d88da849393c8353c98bee443410bb32838828 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Thu, 8 Jan 2026 11:33:39 +0000 Subject: dt-bindings: arm: rockchip: Add Radxa CM3J on RPi CM4 IO Board The Radxa CM3J is a feature rich industrial compute module developed by Radxa, based on the Rockchip RK3568 SoC. [1] Add devicetree binding documentation for the Radxa CM3J on RPi CM4 IO Board. [1] https://dl.radxa.com/cm3j/docs/hw/radxa_cm3j_product_brief_Revision_1.0.pdf Signed-off-by: FUKAUMI Naoki Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260108113341.14037-1-naoki@radxa.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 670d743aa9da..a494494a6202 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -918,6 +918,13 @@ properties: - const: radxa,cm3i - const: rockchip,rk3568 + - description: Radxa CM3J + items: + - enum: + - radxa,cm3j-rpi-cm4 + - const: radxa,cm3j + - const: rockchip,rk3568 + - description: Radxa CM5 items: - enum: -- cgit v1.2.3 From fff010c776f715904ba0823bb347eac00dccffa2 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 25 Dec 2025 14:24:20 +0800 Subject: dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt The descriptions for h, svinval, svnapot, and svpbmt extensions currently reference the "20191213 version of the privileged ISA specification". While an Unprivileged ISA document exists with that date, there is no corresponding ratified Privileged ISA specification. These extensions were ratified in the RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 20211203. Update the descriptions to reference the correct specification version. RISC-V International hosts a website [1] for ratified specifications. Following the "Ratified ISA Specifications", historical versions of Volume II Privileged ISA can be found. Link: https://riscv.org/specifications/ratified/ [1] Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") Acked-by: Conor Dooley Signed-off-by: Guodong Xu Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 565cb2cbb49b..6a4697b36b8d 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -117,8 +117,9 @@ properties: - const: h description: - The standard H extension for hypervisors as ratified in the 20191213 - version of the privileged ISA specification. + The standard H extension for hypervisors as ratified in the RISC-V + Instruction Set Manual, Volume II Privileged Architecture, + Document Version 20211203. # multi-letter extensions, sorted alphanumerically - const: smaia @@ -202,20 +203,22 @@ properties: - const: svinval description: The standard Svinval supervisor-level extension for fine-grained - address-translation cache invalidation as ratified in the 20191213 - version of the privileged ISA specification. + address-translation cache invalidation as ratified in the RISC-V + Instruction Set Manual, Volume II Privileged Architecture, + Document Version 20211203. - const: svnapot description: The standard Svnapot supervisor-level extensions for napot - translation contiguity as ratified in the 20191213 version of the - privileged ISA specification. + translation contiguity as ratified in the RISC-V Instruction Set + Manual, Volume II Privileged Architecture, Document Version + 20211203. - const: svpbmt description: The standard Svpbmt supervisor-level extensions for page-based - memory types as ratified in the 20191213 version of the privileged - ISA specification. + memory types as ratified in the RISC-V Instruction Set Manual, + Volume II Privileged Architecture, Document Version 20211203. - const: svrsw60t59b description: -- cgit v1.2.3 From 0cdb7fc1879b1b858463125630f4dd5af6b111ad Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:18 +0800 Subject: dt-bindings: riscv: Add B ISA extension description Add description of the single-letter B extension for Bit Manipulation. B is mandatory for RVA23U64. The B extension is ratified in the 20240411 version of the unprivileged ISA specification. According to the ratified spec, the B standard extension comprises instructions provided by the Zba, Zbb, and Zbs extensions. Add two-way dependency check to enforce that B implies Zba/Zbb/Zbs; and when Zba/Zbb/Zbs (all of them) are specified, then B must be added too. The reason why B/Zba/Zbb/Zbs must coexist at the same time is that unlike other single-letter extensions, B was ratified (Apr/2024) much later than its component extensions Zba/Zbb/Zbs (Jun/2021). When "b" is specified, zba/zbb/zbs must be present to ensure backward compatibility with existing software and kernels that only look for the explicit component strings. When all three components zba/zbb/zbs are specified, "b" should also be present. Making "b" mandatory when all three components are present. Existing devicetrees with zba/zbb/zbs but without "b" will generate warnings that can be fixed in follow-up patches. Signed-off-by: Guodong Xu Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 6a4697b36b8d..beeb6612db31 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -109,6 +109,13 @@ properties: The standard C extension for compressed instructions, as ratified in the 20191213 version of the unprivileged ISA specification. + - const: b + description: + The standard B extension for bit manipulation instructions, as + ratified in the 20240411 version of the unprivileged ISA + specification. The B standard extension comprises instructions + provided by the Zba, Zbb, and Zbs extensions. + - const: v description: The standard V extension for vector operations, as ratified @@ -738,6 +745,30 @@ properties: then: contains: const: f + # B comprises Zba, Zbb, and Zbs + - if: + contains: + const: b + then: + allOf: + - contains: + const: zba + - contains: + const: zbb + - contains: + const: zbs + # Zba, Zbb, Zbs together require B + - if: + allOf: + - contains: + const: zba + - contains: + const: zbb + - contains: + const: zbs + then: + contains: + const: b # Zcb depends on Zca - if: contains: -- cgit v1.2.3 From b321256a4f36227e0c1ae54e8c6c48524dcba83d Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:19 +0800 Subject: dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm Add descriptions for four extensions: Za64rs, Ziccamoa, Ziccif, and Zicclsm. These extensions are ratified in RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state."). They are introduced as new extension names for existing features and regulate implementation details for RISC-V Profile compliance. According to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, they are mandatory for the following profiles: - za64rs: Mandatory in RVA22U64, RVA23U64 - ziccamoa: Mandatory in RVA20U64, RVA22U64, RVA23U64 - ziccif: Mandatory in RVA20U64, RVA22U64, RVA23U64 - zicclsm: Mandatory in RVA20U64, RVA22U64, RVA23U64 Ziccrse specifies the main memory must support "RsrvEventual", which is one (totally there are four) of the support level for Load-Reserved/ Store-Conditional (LR/SC) atomic instructions. Thus it depends on Zalrsc. Ziccamoa specifies the main memory must support AMOArithmetic, among the four levels of PMA support defined for AMOs in the A extension. Thus it depends on Zaamo. Za64rs defines reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes. Za64rs is consumed by two extensions: Zalrsc and Zawrs. Zawrs itself depends on Zalrsc too. Based on the relationship that "A" = Zaamo + Zalrsc, add the following dependencies checks: Za64rs -> Zalrsc or A Ziccrse -> Zalrsc or A Ziccamoa -> Zaamo or A Signed-off-by: Guodong Xu Acked-by: Conor Dooley Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index beeb6612db31..e0bdd88bd24e 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -240,6 +240,12 @@ properties: as ratified at commit 4a69197e5617 ("Update to ratified state") of riscv-svvptc. + - const: za64rs + description: + The standard Za64rs extension for reservation set size of at most + 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit + b1d806605f87 ("Updated to ratified state.") + - const: zaamo description: | The standard Zaamo extension for atomic memory operations as @@ -381,6 +387,27 @@ properties: in commit 64074bc ("Update version numbers for Zfh/Zfinx") of riscv-isa-manual. + - const: ziccamoa + description: + The standard Ziccamoa extension for main memory (cacheability and + coherence) must support all atomics in A, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + + - const: ziccif + description: + The standard Ziccif extension for main memory (cacheability and + coherence) instruction fetch atomicity, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + + - const: zicclsm + description: + The standard Zicclsm extension for main memory (cacheability and + coherence) must support misaligned loads and stores, as ratified + in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated + to ratified state.") + - const: ziccrse description: The standard Ziccrse extension which provides forward progress @@ -769,6 +796,18 @@ properties: then: contains: const: b + # Za64rs and Ziccrse depend on Zalrsc or A + - if: + contains: + anyOf: + - const: za64rs + - const: ziccrse + then: + oneOf: + - contains: + const: zalrsc + - contains: + const: a # Zcb depends on Zca - if: contains: @@ -810,6 +849,16 @@ properties: then: contains: const: f + # Ziccamoa depends on Zaamo or A + - if: + contains: + const: ziccamoa + then: + oneOf: + - contains: + const: zaamo + - contains: + const: a # Zvfbfmin depends on V or Zve32f - if: contains: -- cgit v1.2.3 From c712413333f8e19cc3de4e9cd1a3ed8a53169cc9 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:20 +0800 Subject: dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl Add descriptions for five new extensions: Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl. These extensions are ratified in RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state."). They are introduced as new extension names for existing features and regulate implementation details for RISC-V Profile compliance. According to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, their requirement status are: - Ssccptr: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Sscounterenw: Mandatory in RVA22S64, RVA23S64 - Sstvala: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Sstvecd: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Ssu64xl: Optional in RVA20S64, RVA22S64; Mandatory in RVA23S64 Signed-off-by: Guodong Xu Acked-by: Conor Dooley Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index e0bdd88bd24e..31f1cc79fbd9 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -161,12 +161,26 @@ properties: behavioural changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: ssccptr + description: | + The standard Ssccptr extension for main memory (cacheability and + coherence) hardware page-table reads, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + - const: sscofpmf description: | The standard Sscofpmf supervisor-level extension for count overflow and mode-based filtering as ratified at commit 01d1df0 ("Add ability to manually trigger workflow. (#2)") of riscv-count-overflow. + - const: sscounterenw + description: | + The standard Sscounterenw extension for support writable enables + in scounteren for any supported counter, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + - const: ssnpm description: | The standard Ssnpm extension for next-mode pointer masking as @@ -179,6 +193,24 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. + - const: sstvala + description: | + The standard Sstvala extension for stval provides all needed values + as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 + ("Updated to ratified state.") + + - const: sstvecd + description: | + The standard Sstvecd extension for stvec supports Direct mode as + ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 + ("Updated to ratified state.") + + - const: ssu64xl + description: | + The standard Ssu64xl extension for UXLEN=64 must be supported, as + ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 + ("Updated to ratified state.") + - const: svade description: | The standard Svade supervisor-level extension for SW-managed PTE A/D -- cgit v1.2.3 From 89febd6a02768200fcfc86ee57f1ece632805bff Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:21 +0800 Subject: dt-bindings: riscv: Add Sha and its comprised extensions Add descriptions for the Sha extension and the seven extensions it comprises: Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, and Ssstateen. Sha is ratified in the RVA23 Profiles Version 1.0 (commit 0273f3c921b6 "rva23/rvb23 ratified") as a new profile-defined extension that captures the full set of features that are mandated to be supported along with the H extension. Extensions Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, and Ssstateen are ratified in the RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state"). The requirement status for Sha and its comprised extension in RISC-V Profiles are: - Sha: Mandatory in RVA23S64 - H: Optional in RVA22S64; Mandatory in RVA23S64 - Shcounterenw: Optional in RVA22S64; Mandatory in RVA23S64 - Shgatpa: Optional in RVA22S64; Mandatory in RVA23S64 - Shtvala: Optional in RVA22S64; Mandatory in RVA23S64 - Shvsatpa: Optional in RVA22S64; Mandatory in RVA23S64 - Shvstvala: Optional in RVA22S64; Mandatory in RVA23S64 - Shvstvecd: Optional in RVA22S64; Mandatory in RVA23S64 - Ssstateen: Optional in RVA22S64; Mandatory in RVA23S64 Signed-off-by: Guodong Xu Acked-by: Conor Dooley Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 31f1cc79fbd9..b43199764395 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -129,6 +129,57 @@ properties: Document Version 20211203. # multi-letter extensions, sorted alphanumerically + - const: sha + description: | + The standard Sha extension for augmented hypervisor extension as + ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6 + ("rva23/rvb23 ratified"). + + Sha captures the full set of features that are mandated to be + supported along with the H extension. Sha comprises the following + extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, + Shvstvecd, and Ssstateen. + + - const: shcounterenw + description: | + The standard Shcounterenw extension for support writable enables + in hcounteren for any supported counter, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + + - const: shgatpa + description: | + The standard Shgatpa extension indicates that for each supported + virtual memory scheme SvNN supported in satp, the corresponding + hgatp SvNNx4 mode must be supported. The hgatp mode Bare must + also be supported. It is ratified in RISC-V Profiles Version 1.0, + with commit b1d806605f87 ("Updated to ratified state.") + + - const: shtvala + description: | + The standard Shtvala extension for htval be written with the + faulting guest physical address in all circumstances permitted by + the ISA. It is ratified in RISC-V Profiles Version 1.0, with + commit b1d806605f87 ("Updated to ratified state.") + + - const: shvsatpa + description: | + The standard Shvsatpa extension for vsatp supporting all translation + modes supported in satp, as ratified in RISC-V Profiles Version 1.0, + with commit b1d806605f87 ("Updated to ratified state.") + + - const: shvstvala + description: | + The standard Shvstvala extension for vstval provides all needed + values as ratified in RISC-V Profiles Version 1.0, with commit + b1d806605f87 ("Updated to ratified state.") + + - const: shvstvecd + description: | + The standard Shvstvecd extension for vstvec supporting Direct mode, + as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 + ("Updated to ratified state.") + - const: smaia description: | The standard Smaia supervisor-level extension for the advanced @@ -187,6 +238,12 @@ properties: ratified at commit d70011dde6c2 ("Update to ratified state") of riscv-j-extension. + - const: ssstateen + description: | + The standard Ssstateen extension for supervisor-mode view of the + state-enable extension, as ratified in RISC-V Profiles Version 1.0, + with commit b1d806605f87 ("Updated to ratified state.") + - const: sstc description: | The standard Sstc supervisor-level extension for time compare as -- cgit v1.2.3 From a36b2aaae742dd2253063ee0cc447aa86f94b4fb Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 15:29:09 -0600 Subject: dt-bindings: riscv: extensions: Drop unnecessary select schema The "select" schema is not necessary because this schema is referenced by riscv/cpus.yaml schema. Signed-off-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ------ 1 file changed, 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index b43199764395..89f520495c2a 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -24,12 +24,6 @@ description: | ratified states, with the exception of the I, Zicntr & Zihpm extensions. See the "i" property for more information. -select: - properties: - compatible: - contains: - const: riscv - properties: riscv,isa: description: -- cgit v1.2.3 From f3b795d298a280687ed70211d51043ed5fc7a96a Mon Sep 17 00:00:00 2001 From: "Herve Codina (Schneider Electric)" Date: Wed, 14 Jan 2026 10:39:35 +0100 Subject: dt-bindings: soc: renesas: Document RZ/N1 GPIO Interrupt Multiplexer On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines. The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines. Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Wolfram Sang Reviewed-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260114093938.1089936-7-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven --- .../soc/renesas/renesas,rzn1-gpioirqmux.yaml | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml new file mode 100644 index 000000000000..1a31c11bc3b4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,rzn1-gpioirqmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 SoCs GPIO Interrupt Multiplexer + +description: | + The Renesas RZ/N1 GPIO Interrupt Multiplexer multiplexes GPIO interrupt + lines to the interrupt controller available in the SoC. + + It selects up to 8 of the 96 GPIO interrupt lines available and connect them + to 8 output interrupt lines. + +maintainers: + - Herve Codina + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-gpioirqmux + - const: renesas,rzn1-gpioirqmux + + reg: + maxItems: 1 + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: + items: + - const: 0x7f + + interrupt-map: + description: | + Specifies the mapping from external GPIO interrupt lines to the output + interrupts. The array has up to 8 items defining the mapping related to + the output line 0 (GIC 103) up to the output line 7 (GIC 110). + + The child interrupt number set in arrays items is computed using the + following formula: + gpio_bank * 32 + gpio_number + with: + - gpio_bank: The GPIO bank number + - 0 for GPIO0A, + - 1 for GPIO1A, + - 2 for GPIO2A + - gpio_number: Number of the gpio in the bank (0..31) + minItems: 1 + maxItems: 8 + +required: + - compatible + - reg + - "#address-cells" + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +additionalProperties: false + +examples: + - | + #include + + gic: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <3>; + }; + + interrupt-controller@51000480 { + compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux"; + reg = <0x51000480 0x20>; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x7f>; + interrupt-map = + <32 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* line 0, GPIO1A.0 */ + <89 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* line 1, GPIO2A.25 */ + <9 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; /* line 3, GPIO0A.9 */ + }; -- cgit v1.2.3 From 10a46a7f6ecc243fb9f745c4ec5e1955b49d77b4 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Thu, 15 Jan 2026 11:00:13 +0800 Subject: dt-bindings: arm: amlogic: introduce specific compatibles for S4 family The Amlogic S4 SoC family includes multiple variants, such as the S805X2 and S905Y4. Currently, the bindings only define the generic "amlogic,s4" compatible. This patch introduces specific compatibles "amlogic,s805x2" and "amlogic,s905y4" to properly differentiate these SoCs while keeping "amlogic,s4" as the family fallback. This allows for more precise hardware description and future-proofing if SoC-specific quirks arise. Signed-off-by: Nick Xie Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260115030015.1334517-2-nick@khadas.com Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/amlogic.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 08d9963fe925..a885278bc4e2 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -245,6 +245,14 @@ properties: items: - enum: - amlogic,aq222 + - const: amlogic,s805x2 + - const: amlogic,s4 + + - description: Boards with the Amlogic Meson S4 S905Y4 SoC + items: + - enum: + - khadas,vim1s + - const: amlogic,s905y4 - const: amlogic,s4 - description: Boards with the Amlogic S6 S905X5 SoC -- cgit v1.2.3 From a3ceeadb287ce35eedc4cf0f55e1295d69617354 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 19 Nov 2025 09:37:28 +0000 Subject: dt-bindings: tegra: pmc: Update aotag as an optional aperture Not all Tegra SoCs or all versions of a particular Tegra SoC may include the AOTAG aperture. This change makes "aotag" as an optional aperture for Tegra234 and Tegra264. Co-developed-by: Prathamesh Shete Signed-off-by: Prathamesh Shete Signed-off-by: Jon Hunter Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- .../devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml index be70819020c5..dcd1c5376507 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -19,15 +19,15 @@ properties: - nvidia,tegra264-pmc reg: - minItems: 4 + minItems: 3 maxItems: 5 reg-names: - minItems: 4 + minItems: 3 items: - const: pmc - const: wake - - const: aotag + - enum: [ aotag, scratch, misc ] - enum: [ scratch, misc ] - const: misc @@ -51,6 +51,7 @@ allOf: then: properties: reg: + minItems: 4 maxItems: 4 reg-names: maxItems: 4 @@ -73,7 +74,9 @@ allOf: properties: compatible: contains: - const: nvidia,tegra234-pmc + enum: + - nvidia,tegra234-pmc + - nvidia,tegra264-pmc then: properties: reg-names: -- cgit v1.2.3 From d3b9e6d5b4da3961d8cc4fce1d867f89621420cb Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 5 Nov 2025 20:53:40 +0100 Subject: dt-bindings: memory: tegra: Document DBB clock for Tegra264 Accesses to external memory are routed through the data backbone (DBB) on Tegra264. A separate clock feeds this path and needs to be enabled whenever an IP block makes an access to external memory. The external memory controller driver is the best place to control this clock since it knows how many devices are actively accessing memory. Document the presence of this clock on Tegra264 only. Acked-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- .../bindings/memory-controllers/nvidia,tegra186-mc.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index b901f1b3e0fc..7b03b589168b 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -92,10 +92,14 @@ patternProperties: clocks: items: - description: external memory clock + - description: data backbone clock + minItems: 1 clock-names: items: - const: emc + - const: dbb + minItems: 1 "#interconnect-cells": const: 0 @@ -115,6 +119,9 @@ patternProperties: reg: maxItems: 1 + clocks: + maxItems: 1 + - if: properties: compatible: @@ -124,6 +131,9 @@ patternProperties: reg: minItems: 2 + clocks: + maxItems: 1 + - if: properties: compatible: @@ -133,6 +143,9 @@ patternProperties: reg: minItems: 2 + clocks: + maxItems: 1 + - if: properties: compatible: -- cgit v1.2.3 From 8a59954192eba2d9dd2248dcc7b1f458c082eff2 Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Tue, 13 Jan 2026 05:49:34 +0000 Subject: dt-bindings: iommu: Add NVIDIA Tegra CMDQV support The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Add a new device tree binding document for nvidia,tegra264-cmdqv. Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv property. This property is a phandle to the CMDQV device node, allowing the SMMU driver to associate with its corresponding CMDQV instance. Restrict this property usage to Nvidia Tegra264 only. Reviewed-by: Rob Herring (Arm) Acked-by: Nicolin Chen Signed-off-by: Ashish Mhetre Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- .../devicetree/bindings/iommu/arm,smmu-v3.yaml | 27 +++++++++++++- .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 42 ++++++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 75fcf4cb52d9..82957334bea2 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -20,7 +20,12 @@ properties: $nodename: pattern: "^iommu@[0-9a-f]*" compatible: - const: arm,smmu-v3 + oneOf: + - const: arm,smmu-v3 + - items: + - enum: + - nvidia,tegra264-smmu + - const: arm,smmu-v3 reg: maxItems: 1 @@ -58,6 +63,15 @@ properties: msi-parent: true + nvidia,cmdqv: + description: | + A phandle to its pairing CMDQV extension for an implementation on NVIDIA + Tegra SoC. + + If this property is absent, CMDQ-Virtualization won't be used and SMMU + will only use its own CMDQ. + $ref: /schemas/types.yaml#/definitions/phandle + hisilicon,broken-prefetch-cmd: type: boolean description: Avoid sending CMD_PREFETCH_* commands to the SMMU. @@ -69,6 +83,17 @@ properties: register access with page 0 offsets. Set for Cavium ThunderX2 silicon that doesn't support SMMU page1 register space. +allOf: + - if: + not: + properties: + compatible: + contains: + const: nvidia,tegra264-smmu + then: + properties: + nvidia,cmdqv: false + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml new file mode 100644 index 000000000000..3f5006a59805 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 CMDQV + +description: + The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation + on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU. + +maintainers: + - Nicolin Chen + +properties: + compatible: + const: nvidia,tegra264-cmdqv + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + cmdqv@5200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x5200000 0x830000>; + interrupts = ; + }; -- cgit v1.2.3 From 919f6cd469c605f1de2269d46d04ebf80a1af568 Mon Sep 17 00:00:00 2001 From: sheetal Date: Mon, 29 Sep 2025 16:29:27 +0530 Subject: dt-bindings: dma: Update ADMA bindings for tegra264 - Update ADMA device tree bindings for tegra264 to support up to 64 interrupt channels by setting 'interrupts' property maxItems to 64. - Also, update the 'allOf' conditional schema to ensure correct maxItems for 'interrupts' based on compatible string, including tegra210 (22) and tegra186 (32) ADMA controllers. Signed-off-by: sheetal Reviewed-by: Rob Herring (Arm) Acked-by: Thierry Reding Signed-off-by: Thierry Reding --- .../devicetree/bindings/dma/nvidia,tegra210-adma.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index da0235e451d6..269a1f7ebdbb 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -46,7 +46,7 @@ properties: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. minItems: 1 - maxItems: 32 + maxItems: 64 clocks: description: Must contain one entry for the ADMA module clock @@ -86,6 +86,19 @@ allOf: reg: items: - description: Full address space range of DMA registers. + interrupts: + maxItems: 22 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-adma + then: + properties: + interrupts: + maxItems: 32 - if: properties: -- cgit v1.2.3 From dff8af7c5220c691661ca4b3e2348b58d050092c Mon Sep 17 00:00:00 2001 From: Charan Pedumuru Date: Sun, 4 Jan 2026 11:23:04 +0000 Subject: dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schema Convert NVIDIA Tegra NAND Flash Controller binding to YAML format. Changes during Conversion: - Define new properties `power-domains` and `operating-points-v2` because the existing in tree DTS uses them. - Modify MAINTAINERS references to point the created YAML file. Signed-off-by: Charan Pedumuru Reviewed-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- .../bindings/mtd/nvidia,tegra20-nand.yaml | 102 +++++++++++++++++++++ .../bindings/mtd/nvidia-tegra20-nand.txt | 64 ------------- 2 files changed, 102 insertions(+), 64 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml delete mode 100644 Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml new file mode 100644 index 000000000000..b417d72fa0de --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/nvidia,tegra20-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra NAND Flash Controller + +maintainers: + - Jonathan Hunter + +allOf: + - $ref: nand-controller.yaml + +description: + The NVIDIA NAND controller provides an interface between NVIDIA SoCs + and raw NAND flash devices. It supports standard NAND operations, + hardware-assisted ECC, OOB data access, and DMA transfers, and + integrates with the Linux MTD NAND subsystem for reliable flash management. + +properties: + compatible: + const: nvidia,tegra20-nand + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nand + + resets: + maxItems: 1 + + reset-names: + items: + - const: nand + + power-domains: + maxItems: 1 + + operating-points-v2: + maxItems: 1 + +patternProperties: + '^nand@': + type: object + description: Individual NAND chip connected to the NAND controller + $ref: raw-nand-chip.yaml# + + properties: + reg: + maximum: 5 + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + nand-controller@70008000 { + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + clock-names = "nand"; + resets = <&tegra_car 13>; + reset-names = "nand"; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <8>; + nand-on-flash-bbt; + nand-ecc-algo = "bch"; + nand-ecc-strength = <8>; + wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt deleted file mode 100644 index 4a00ec2b2540..000000000000 --- a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt +++ /dev/null @@ -1,64 +0,0 @@ -NVIDIA Tegra NAND Flash controller - -Required properties: -- compatible: Must be one of: - - "nvidia,tegra20-nand" -- reg: MMIO address range -- interrupts: interrupt output of the NFC controller -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - nand -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - nand - -Optional children nodes: -Individual NAND chips are children of the NAND controller node. Currently -only one NAND chip supported. - -Required children node properties: -- reg: An integer ranging from 1 to 6 representing the CS line to use. - -Optional children node properties: -- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only - "hw" is supported. -- nand-ecc-algo: string, algorithm of NAND ECC. - Supported values with "hw" ECC mode are: "rs", "bch". -- nand-bus-width : See nand-controller.yaml -- nand-on-flash-bbt: See nand-controller.yaml -- nand-ecc-strength: integer representing the number of bits to correct - per ECC step (always 512). Supported strength using HW ECC - modes are: - - RS: 4, 6, 8 - - BCH: 4, 8, 14, 16 -- nand-ecc-maximize: See nand-controller.yaml -- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM - are chosen. -- wp-gpios: GPIO specifier for the write protect pin. - -Optional child node of NAND chip nodes: -Partitions: see mtd.yaml - - Example: - nand-controller@70008000 { - compatible = "nvidia,tegra20-nand"; - reg = <0x70008000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; - clock-names = "nand"; - resets = <&tegra_car 13>; - reset-names = "nand"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <8>; - nand-on-flash-bbt; - nand-ecc-algo = "bch"; - nand-ecc-strength = <8>; - wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; - }; - }; -- cgit v1.2.3 From 58e69e8f9c9a4df948dfc554c26b8f4adf505636 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Tue, 21 Oct 2025 23:32:30 -0700 Subject: dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings for Kaanapali Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm Kaanapali, which is compatible with X1E80100, use fallback to indicate this. Signed-off-by: Jingyi Wang Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20251021-knp-cpufreq-v2-1-95391d66c84e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index 9d99af46e531..90bfde66cc4a 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -19,6 +19,7 @@ properties: - items: - enum: - qcom,glymur-cpucp-mbox + - qcom,kaanapali-cpucp-mbox - qcom,sm8750-cpucp-mbox - const: qcom,x1e80100-cpucp-mbox - enum: -- cgit v1.2.3 From d6e8b796d0d67699c74ee3cbc46601cf9ec925bb Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 22 Oct 2025 17:20:38 +0300 Subject: dt-bindings: display: tegra: document Tegra132 MIPI calibration device Document MIPI calibration device found in Tegra132. This compatible already exists in the Linux kernel, I have just documented it to satisfy warnings. Each Tegra SoC generation has unique set of registers which should be configured. They all differ, hence fallback is not suitable here. Signed-off-by: Svyatoslav Ryhel Acked-by: Conor Dooley Tested-by: Luca Ceresoli # tegra20, parallel camera Signed-off-by: Thierry Reding --- .../devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml index 193ddb105283..9a500f52f01d 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml @@ -18,6 +18,7 @@ properties: enum: - nvidia,tegra114-mipi - nvidia,tegra124-mipi + - nvidia,tegra132-mipi - nvidia,tegra210-mipi - nvidia,tegra186-mipi -- cgit v1.2.3 From d262d030baef287da33344a932639aab5f913c3a Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 22 Oct 2025 17:20:32 +0300 Subject: dt-bindings: display: tegra: document Tegra30 VI and VIP Existing Parallel VI interface schema for Tegra20 is fully compatible with Tegra30; hence, lets reuse it by setting fallback for Tegra30. Adjust existing VI schema to reflect that Tegra20 VI is compatible with Tegra30 by setting a fallback for Tegra30. Additionally, switch to using an enum instead of list of const. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Tested-by: Luca Ceresoli # tegra20, parallel camera Signed-off-by: Thierry Reding --- .../bindings/display/tegra/nvidia,tegra20-vi.yaml | 19 ++++++++++++------- .../bindings/display/tegra/nvidia,tegra20-vip.yaml | 9 +++++++-- 2 files changed, 19 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml index 644f42b942ad..bb138277d5e8 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml @@ -16,16 +16,21 @@ properties: compatible: oneOf: - - const: nvidia,tegra20-vi - - const: nvidia,tegra30-vi - - const: nvidia,tegra114-vi - - const: nvidia,tegra124-vi + - enum: + - nvidia,tegra20-vi + - nvidia,tegra114-vi + - nvidia,tegra124-vi + - nvidia,tegra210-vi + - nvidia,tegra186-vi + - nvidia,tegra194-vi + + - items: + - const: nvidia,tegra30-vi + - const: nvidia,tegra20-vi + - items: - const: nvidia,tegra132-vi - const: nvidia,tegra124-vi - - const: nvidia,tegra210-vi - - const: nvidia,tegra186-vi - - const: nvidia,tegra194-vi reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml index 14294edb8d8c..9104a36e16d9 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml @@ -11,8 +11,13 @@ maintainers: properties: compatible: - enum: - - nvidia,tegra20-vip + oneOf: + - enum: + - nvidia,tegra20-vip + + - items: + - const: nvidia,tegra30-vip + - const: nvidia,tegra20-vip ports: $ref: /schemas/graph.yaml#/properties/ports -- cgit v1.2.3 From 6f55fc60dc2c465b536cd69b71b82266d0da52c9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Jan 2026 20:00:37 +0100 Subject: dt-bindings: vendor-prefixes: Document ifm electronic gmbh ifm is a manufacturer of industrial sensors, control technology and automation solutions. Document their vendor prefix, which is already used for ifm,ac14xx and other powerpc devices. Acked-by: Rob Herring (Arm) Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index c7591b2aec2a..c06d640bfcb0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -755,6 +755,8 @@ patternProperties: description: IEI Integration Corp. "^ifi,.*": description: Ingenieurburo Fur Ic-Technologie (I/F/I) + "^ifm,.*": + description: ifm electronic gmbh "^ilitek,.*": description: ILI Technology Corporation (ILITEK) "^imagis,.*": -- cgit v1.2.3 From a642165719daa8a1b5aef86dcf6d6454082ac1d1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Jan 2026 20:00:38 +0100 Subject: dt-bindings: arm: fsl: Document ifm VHIP4 EvalBoard v1 and v2 Document ifm i.MX8MN VHIP4 EvalBoard v1 and v2 reference design binding. This system exists in two generations, v1 and v2, which share a lot of commonality. The boards come with either single gigabit ethernet or an KSZ8794 fast-ethernet switch, boot from eMMC, and offer CAN interfaces via Microchip MCP25xx SPI CAN controllers, UART, and USB host. The GPU is not available in the SoC populated on these devices. Acked-by: Rob Herring (Arm) Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 433f555232e9..b45047c15ef1 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1071,6 +1071,15 @@ properties: - gw,imx8mn-gw7902 # i.MX8MM Gateworks Board - const: fsl,imx8mn + - description: ifm i.MX8MN VHIP4 based boards + items: + - enum: + - ifm,imx8mn-vhip4-evalboard-v1 + - ifm,imx8mn-vhip4-evalboard-v2 + - const: ifm,imx8mn-vhip4-evalboard + - const: ifm,imx8mn-vhip4 + - const: fsl,imx8mn + - description: Variscite VAR-SOM-MX8MN based boards items: - enum: -- cgit v1.2.3 From 3a2741fa31385348c5b501bdcbab6f6d7b4628ac Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 13 Jan 2026 10:58:58 +0000 Subject: dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Ensure children of cmu_top have alphanumeric ordering. Top is special as it feeds all the other children CMUs. This ordering then matches the clk-gs101.c file. Reviewed-by: André Draszik Signed-off-by: Peter Griffin Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260113-dpu-clocks-v3-1-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/google,gs101-clock.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 31e106ef913d..82639863b1a4 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -29,9 +29,9 @@ properties: enum: - google,gs101-cmu-top - google,gs101-cmu-apm - - google,gs101-cmu-misc - google,gs101-cmu-hsi0 - google,gs101-cmu-hsi2 + - google,gs101-cmu-misc - google,gs101-cmu-peric0 - google,gs101-cmu-peric1 -- cgit v1.2.3 From 52300cd894b3167d6206e266e341a089e87124b9 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 13 Jan 2026 10:58:59 +0000 Subject: dt-bindings: clock: google,gs101-clock: Add DPU clock management unit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add dt schema documentation and clock IDs for the Display Process Unit (DPU) clock management unit (CMU). This CMU feeds IPs such as image scaler, enhancer and compressor. Signed-off-by: Peter Griffin Reviewed-by: Rob Herring (Arm) Reviewed-by: André Draszik Link: https://patch.msgid.link/20260113-dpu-clocks-v3-2-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/google,gs101-clock.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 82639863b1a4..6193c87511fa 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -29,6 +29,7 @@ properties: enum: - google,gs101-cmu-top - google,gs101-cmu-apm + - google,gs101-cmu-dpu - google,gs101-cmu-hsi0 - google,gs101-cmu-hsi2 - google,gs101-cmu-misc @@ -77,6 +78,24 @@ allOf: items: - const: oscclk + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-dpu + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: DPU bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - if: properties: compatible: -- cgit v1.2.3 From fc12767c19d49663b13ba2def6e4674df041c8a2 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Fri, 31 Oct 2025 00:41:44 -0700 Subject: dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms Document the Inter-Processor Communication Controller on the Qualcomm Kaanapali and Glymur Platforms, which will be used to route interrupts across various subsystems found on the SoC. Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Signed-off-by: Jingyi Wang Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251031-knp-ipcc-v3-1-62ffb4168dff@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index e5c423130db6..7c4d6170491d 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -24,6 +24,8 @@ properties: compatible: items: - enum: + - qcom,glymur-ipcc + - qcom,kaanapali-ipcc - qcom,milos-ipcc - qcom,qcs8300-ipcc - qcom,qdu1000-ipcc -- cgit v1.2.3 From b17171492e9897f2c283d7b62d7a283cbbeee6d0 Mon Sep 17 00:00:00 2001 From: Lei Xu Date: Fri, 16 Jan 2026 00:56:13 -0800 Subject: dt-bindings: arm: fsl: Add compatible for i.MX95 15x15 FRDM board Introduce a new DT compatible string for the NXP i.MX95 15x15 FRDM development board, a compact and cost-effective platform based on the i.MX95 applications processor. Acked-by: Krzysztof Kozlowski Reviewed-by: Daniel Baluta Reviewed-by: Laurentiu Mihalcea Signed-off-by: Lei Xu Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b45047c15ef1..36e885f7d13c 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1446,6 +1446,7 @@ properties: items: - enum: - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board + - fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board - toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK) - const: fsl,imx95 -- cgit v1.2.3 From a8e3d66ff5c0c37e7c10b3e486d2c5047bf9cf2b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 15 Jan 2026 13:56:23 +0100 Subject: dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant Add support for the mediatek,mt8192-audsys compatible, which uses a different audio controller (mt8192-afe-pcm) compared to mt8183 and mt2701. This resolves a dtbs_check warning on all MT8192 devicetrees. Reviewed-by: Rob Herring (Arm) Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/arm/mediatek/mediatek,audsys.yaml | 46 ++++++++++++++++------ 1 file changed, 33 insertions(+), 13 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml index f3a761cbd0fd..09a6c16e7e82 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml @@ -48,19 +48,39 @@ required: - compatible - '#clock-cells' -if: - properties: - compatible: - contains: - const: mediatek,mt8183-audiosys -then: - properties: - audio-controller: - $ref: /schemas/sound/mediatek,mt8183-audio.yaml# -else: - properties: - audio-controller: - $ref: /schemas/sound/mediatek,mt2701-audio.yaml# +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-audsys + - mediatek,mt7622-audsys + then: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt2701-audio.yaml# + + - if: + properties: + compatible: + contains: + const: mediatek,mt8183-audiosys + then: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt8183-audio.yaml# + + - if: + properties: + compatible: + contains: + const: mediatek,mt8192-audsys + then: + properties: + audio-controller: + $ref: /schemas/sound/mt8192-afe-pcm.yaml# + additionalProperties: false -- cgit v1.2.3 From 6609c1976e64b6ce31fc2de11136dd7703372f20 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 24 Dec 2025 12:45:20 +0200 Subject: dt-bindings: watchdog: Document X1E80100 compatible Document the compatible for the X1E80100 platform to the Qualcomm watchdog binding. The HW implementation is compatible with the KPSS WDT. Acked-by: Rob Herring (Arm) Reviewed-by: Guenter Roeck Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20251224-arm64-dts-qcom-x1e80100-el2-add-apss-wdt-v3-1-1801c55d2883@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index 54f5311ed016..f2c4bc900e5f 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -43,6 +43,7 @@ properties: - qcom,apss-wdt-sm6350 - qcom,apss-wdt-sm8150 - qcom,apss-wdt-sm8250 + - qcom,apss-wdt-x1e80100 - const: qcom,kpss-wdt - const: qcom,kpss-wdt deprecated: true -- cgit v1.2.3 From 974e24ed49e03586c101c414ba9cf9764de5863b Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 15 Dec 2025 13:19:40 +0100 Subject: dt-bindings: i2c: st,stm32-i2c: add 'power-domains' property STM32 I2C may be in a power domain which is the case for the STM32MP2x based boards. Allow a single 'power-domains' entry for STM32 I2C. Signed-off-by: Alain Volmat Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251215-stm32-i2c-mp2x-dt-updates-v1-1-2738a05a7af8@foss.st.com Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index 457bb0702ed9..64aaa0dfa8fa 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -127,6 +127,9 @@ properties: wakeup-source: true + power-domains: + maxItems: 1 + access-controllers: minItems: 1 maxItems: 2 -- cgit v1.2.3 From 9cdfabe2f2d1eed6e57d5b4fb18fb4719b6c565a Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 19 Dec 2025 16:58:03 +0100 Subject: dt-bindings: media: st: csi: add 'power-domains' property STM32 CSI may be in a power domain which is the case for the STM32MP2x based boards. Allow a single 'power-domains' entry for STM32 CSI. Signed-off-by: Alain Volmat Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251219-stm32-mp2x-dcmipp-csi-power-domain-v1-1-a6edb2aa8154@foss.st.com Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml b/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml index e9fa3cfea5d2..2ac7c9670c62 100644 --- a/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml @@ -46,6 +46,9 @@ properties: minItems: 1 maxItems: 2 + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports -- cgit v1.2.3 From 196369e3823ed10ff42364f580164640255f5a4c Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 19 Dec 2025 16:58:06 +0100 Subject: dt-bindings: media: st: dcmipp: add 'power-domains' property STM32 DCMIPP may be in a power domain which is the case for the STM32MP2x based boards. Allow a single 'power-domains' entry for STM32 DCMIPP. Signed-off-by: Alain Volmat Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251219-stm32-mp2x-dcmipp-csi-power-domain-v1-4-a6edb2aa8154@foss.st.com Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml index 7b03a77adbce..162a0c526d5d 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml @@ -37,6 +37,9 @@ properties: resets: maxItems: 1 + power-domains: + maxItems: 1 + access-controllers: minItems: 1 maxItems: 2 -- cgit v1.2.3 From 81a52103b90f5cddc41c34f633c014a956236abc Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:40 +0800 Subject: dt-bindings: riscv: add SpacemiT X100 CPU compatible Add compatible string for the SpacemiT X100 core. [1] The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100 supports the RISC-V vector and hypervisor extensions and all mandatory extersions as required by the RVA23U64 and RVA23S64 profiles, per the definition in 'RVA23 Profile, Version 1.0'. [2] From a microarchieture viewpoint, the X100 features a 4-issue out-of-order pipeline. X100 is used in SpacemiT K3 SoC. Acked-by: Paul Walmsley Acked-by: Krzysztof Kozlowski Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2] Reviewed-by: Yixun Lan Reviewed-by: Heinrich Schuchardt Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-1-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d733c0bd534f..5feeb2203050 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -61,6 +61,7 @@ properties: - sifive,u7 - sifive,u74 - sifive,u74-mc + - spacemit,x100 - spacemit,x60 - thead,c906 - thead,c908 -- cgit v1.2.3 From 6cdeb30db4d8faf9f1fa7ab863d91d36a584716d Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:41 +0800 Subject: dt-bindings: timer: add SpacemiT K3 CLINT Add compatible string for SpacemiT K3 CLINT. Acked-by: Conor Dooley Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-2-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 0d3b8dc362ba..3bab40500df9 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -33,6 +33,7 @@ properties: - eswin,eic7700-clint # ESWIN EIC7700 - sifive,fu540-c000-clint # SiFive FU540 - spacemit,k1-clint # SpacemiT K1 + - spacemit,k3-clint # SpacemiT K3 - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 -- cgit v1.2.3 From 60490ca6d54b6f0a00223a4fe59bb180bb1538bf Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:42 +0800 Subject: dt-bindings: interrupt-controller: add SpacemiT K3 APLIC Add compatible string for SpacemiT K3 APLIC. Acked-by: Conor Dooley Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-3-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml index bef00521d5da..0718071444d2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml @@ -28,6 +28,7 @@ properties: items: - enum: - qemu,aplic + - spacemit,k3-aplic - const: riscv,aplic reg: -- cgit v1.2.3 From a716729a3ce1055efab477030235777d2be0852b Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:43 +0800 Subject: dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC Add compatible string for SpacemiT K3 IMSIC. Acked-by: Krzysztof Kozlowski Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-4-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml index c23b5c09fdb9..feec122bddde 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml @@ -48,6 +48,7 @@ properties: items: - enum: - qemu,imsics + - spacemit,k3-imsics - const: riscv,imsics reg: -- cgit v1.2.3 From 7cb5fafc180f6e188af7943d6b162051f22490fc Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:44 +0800 Subject: dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX which is a 2.5-inch single-board computer. Acked-by: Conor Dooley Reviewed-by: Yixun Lan Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-5-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index 9c49482002f7..b958b94a924d 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SpacemiT SoC-based boards maintainers: + - Guodong Xu - Yangyu Chen - Yixun Lan @@ -26,6 +27,10 @@ properties: - xunlong,orangepi-r2s - xunlong,orangepi-rv2 - const: spacemit,k1 + - items: + - enum: + - spacemit,k3-pico-itx + - const: spacemit,k3 additionalProperties: true -- cgit v1.2.3 From 84f42966b80eaec59349c7b474ebd6b0943731e4 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Tue, 13 Jan 2026 13:57:19 -0600 Subject: dt-bindings: arm: rockchip: Add Anbernic RG-DS Add compatible string for the Anbernic RG-DS. Signed-off-by: Chris Morgan Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260113195721.151205-5-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index a494494a6202..ae77ded9fe47 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -60,6 +60,12 @@ properties: - anbernic,rg-arc-s - const: rockchip,rk3566 + - description: Anbernic RK3568 Handheld Gaming Console + items: + - enum: + - anbernic,rg-ds + - const: rockchip,rk3568 + - description: Ariaboard Photonicat items: - const: ariaboard,photonicat -- cgit v1.2.3 From 3c8399d31c8eb10aa34bccec1f49b51694e67b00 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Tue, 13 Jan 2026 13:57:20 -0600 Subject: dt-bindings: input: touchscreen: goodix: Add "panel" property Add a "panel" property to define a relationship between a touchscreen and an associated panel when more than one of each exist in a device. Signed-off-by: Chris Morgan Acked-by: Dmitry Torokhov Acked-by: Rob Herring (Arm) [picked with the rest with Dmitry's Ack] Link: https://patch.msgid.link/20260113195721.151205-6-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/input/touchscreen/goodix.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml index a96137c6f063..a26a54d63a1c 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml @@ -42,6 +42,8 @@ properties: address, thus it can be driven by the host during the reset sequence. maxItems: 1 + panel: true + reset-gpios: maxItems: 1 -- cgit v1.2.3 From d83bcab6842f01bad024056c3801c39f55e61f30 Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Tue, 27 Jan 2026 15:14:00 +0800 Subject: dt-bindings: arm: realtek: Add Kent Soc family compatibles Define compatible strings for Realtek RTD1501s, RTD1861b and RTD1920s. Additionally, convert legacy DTS-style comments to YAML description properties, following the pattern from the ARM bindings conversion series [1]. [1] https://lore.kernel.org/lkml/20200622125527.24207-2-afaerber@suse.de/ Acked-by: Conor Dooley Signed-off-by: Yu-Chun Lin Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260127071530.25426-2-eleanor15x@gmail.com Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/realtek.yaml | 42 +++++++++++++++------- 1 file changed, 30 insertions(+), 12 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documentation/devicetree/bindings/arm/realtek.yaml index ddd9a85099e9..be529490640c 100644 --- a/Documentation/devicetree/bindings/arm/realtek.yaml +++ b/Documentation/devicetree/bindings/arm/realtek.yaml @@ -14,21 +14,21 @@ properties: const: '/' compatible: oneOf: - # RTD1195 SoC based boards - - items: + - description: RTD1195 SoC based boards + items: - enum: - mele,x1000 # MeLE X1000 - realtek,horseradish # Realtek Horseradish EVB - const: realtek,rtd1195 - # RTD1293 SoC based boards - - items: + - description: RTD1293 SoC based boards + items: - enum: - synology,ds418j # Synology DiskStation DS418j - const: realtek,rtd1293 - # RTD1295 SoC based boards - - items: + - description: RTD1295 SoC based boards + items: - enum: - mele,v9 # MeLE V9 - probox2,ava # ProBox2 AVA @@ -36,25 +36,43 @@ properties: - zidoo,x9s # Zidoo X9S - const: realtek,rtd1295 - # RTD1296 SoC based boards - - items: + - description: RTD1296 SoC based boards + items: - enum: - synology,ds418 # Synology DiskStation DS418 - const: realtek,rtd1296 - # RTD1395 SoC based boards - - items: + - description: RTD1395 SoC based boards + items: - enum: - bananapi,bpi-m4 # Banana Pi BPI-M4 - realtek,lion-skin # Realtek Lion Skin EVB - const: realtek,rtd1395 - # RTD1619 SoC based boards - - items: + - description: RTD1501s SoC based boards + items: + - enum: + - realtek,phantom # Realtek Phantom EVB (8GB) + - const: realtek,rtd1501s + + - description: RTD1619 SoC based boards + items: - enum: - realtek,mjolnir # Realtek Mjolnir EVB - const: realtek,rtd1619 + - description: RTD1861b SoC based boards + items: + - enum: + - realtek,krypton # Realtek Krypton EVB (8GB) + - const: realtek,rtd1861b + + - description: RTD1920s SoC based boards + items: + - enum: + - realtek,smallville # Realtek Smallville EVB (4GB) + - const: realtek,rtd1920s + additionalProperties: true ... -- cgit v1.2.3 From 2bd42d859b093e3a4c71258767c3cac298265993 Mon Sep 17 00:00:00 2001 From: Niravkumar L Rabara Date: Tue, 2 Dec 2025 18:16:51 +0800 Subject: dt-bindings: intel: Add Agilex5 SoCFPGA modular board Add compatible for Agilex5 SoCFPGA modular board. Signed-off-by: Niravkumar L Rabara Acked-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml index c918837bd41c..6b2d88947352 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -32,6 +32,7 @@ properties: - enum: - intel,socfpga-agilex5-socdk - intel,socfpga-agilex5-socdk-013b + - intel,socfpga-agilex5-socdk-modular - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 -- cgit v1.2.3 From 1cb8486ac5f3adc0a4f38e8b59962c2314fc2ca5 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 10 Dec 2025 21:59:39 -0600 Subject: dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml For all SoCFPGA platforms, whether it has the "intel" or "altr" vendor prefix are referring to the same business unit that is responsible for the platform. And now that Altera has spun off to be a separate corporate entity from Intel, it would make sense to have the device bindings documentation in the same file. Move the Intel AgileX board binding documentations into the same file that contains the Altera ones. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 26 ++++++++++++++ .../devicetree/bindings/arm/intel,socfpga.yaml | 41 ---------------------- 2 files changed, 26 insertions(+), 41 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/intel,socfpga.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index db61537b7115..26ab75bc6ed3 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -9,6 +9,9 @@ title: Altera's SoCFPGA platform maintainers: - Dinh Nguyen +description: + Altera/Intel boards with ARM 32/64 bits cores + properties: $nodename: const: "/" @@ -81,6 +84,29 @@ properties: - altr,socfpga-stratix10-swvp - const: altr,socfpga-stratix10 + - description: AgileX boards + items: + - enum: + - intel,n5x-socdk + - intel,socfpga-agilex-n6000 + - intel,socfpga-agilex-socdk + - const: intel,socfpga-agilex + + - description: Agilex3 boards + items: + - enum: + - intel,socfpga-agilex3-socdk + - const: intel,socfpga-agilex3 + - const: intel,socfpga-agilex5 + + - description: Agilex5 boards + items: + - enum: + - intel,socfpga-agilex5-socdk + - intel,socfpga-agilex5-socdk-013b + - intel,socfpga-agilex5-socdk-nand + - const: intel,socfpga-agilex5 + - description: SoCFPGA VT items: - const: altr,socfpga-vt diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml deleted file mode 100644 index 6b2d88947352..000000000000 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ /dev/null @@ -1,41 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Intel SoCFPGA platform - -maintainers: - - Dinh Nguyen - -properties: - $nodename: - const: "/" - compatible: - oneOf: - - description: AgileX boards - items: - - enum: - - intel,n5x-socdk - - intel,socfpga-agilex-n6000 - - intel,socfpga-agilex-socdk - - const: intel,socfpga-agilex - - description: Agilex3 boards - items: - - enum: - - intel,socfpga-agilex3-socdk - - const: intel,socfpga-agilex3 - - const: intel,socfpga-agilex5 - - description: Agilex5 boards - items: - - enum: - - intel,socfpga-agilex5-socdk - - intel,socfpga-agilex5-socdk-013b - - intel,socfpga-agilex5-socdk-modular - - intel,socfpga-agilex5-socdk-nand - - const: intel,socfpga-agilex5 - -additionalProperties: true - -... -- cgit v1.2.3 From 42918d28cb47f1907daa843a68c2abb801f57761 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 26 Dec 2025 07:05:40 -0600 Subject: dt-bindings: altera: document syscon as fallback for sys-mgr For 32-bit Altera SoCFPGA parts, the sys-mgr uses the syscon as a fallback. This change addresses this warning from dtbs_check: sysmgr@ffd08000 (altr,sys-mgr): compatible: 'oneOf' conditional failed, one must be fixed: ['altr,sys-mgr', 'syscon'] is too long 'altr,sys-mgr-s10' was expected 'altr,sys-mgr' was expected from schema $id: http://devicetree.org/schemas/soc/altera/altr,sys-mgr.yaml Acked-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml b/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml index d56ff4c05ae5..2dd3395f3f63 100644 --- a/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml +++ b/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml @@ -13,7 +13,9 @@ properties: compatible: oneOf: - description: Cyclone5/Arria5/Arria10 - const: altr,sys-mgr + items: + - const: altr,sys-mgr + - const: syscon - description: Stratix10 SoC items: - const: altr,sys-mgr-s10 @@ -45,7 +47,7 @@ additionalProperties: false examples: - | sysmgr@ffd08000 { - compatible = "altr,sys-mgr"; + compatible = "altr,sys-mgr", "syscon"; reg = <0xffd08000 0x1000>; cpu1-start-addr = <0xffd080c4>; }; -- cgit v1.2.3 From 4d904af4d6ce29b9240ebecd35e31458d08cd577 Mon Sep 17 00:00:00 2001 From: Ng Tze Yee Date: Fri, 30 Jan 2026 09:46:57 -0600 Subject: dt-bindings: intel: Add Agilex eMMC support Agilex devkit support a separate eMMC daughter card. Document Agilex eMMC daughter board compatible. [dinguyen] becauce of patch 1cb8486ac5f3 ("dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml"), I moved the change to altera.yaml file. Acked-by: Krzysztof Kozlowski Signed-off-by: Ng Tze Yee Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 26ab75bc6ed3..13a3a9696821 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -90,6 +90,7 @@ properties: - intel,n5x-socdk - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk + - intel,socfpga-agilex-socdk-emmc - const: intel,socfpga-agilex - description: Agilex3 boards -- cgit v1.2.3