From 3f285c301cd788164fa776e1f95458c56e68a6ee Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 15 Mar 2022 14:26:38 +0000 Subject: dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's. SYSC controller found on the RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55 core0 reset vector address configuration register. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220315142644.17660-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml index bb433e75a0ee..c31eeb66319f 100644 --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml @@ -10,8 +10,8 @@ maintainers: - Geert Uytterhoeven description: - The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI - and supports following functions, + The RZ/{G2L,V2L}-alike System Controller (SYSC) performs system control of + the LSI and supports following functions, - External terminal state capture function - 34-bit address space access function - Low power consumption control @@ -20,6 +20,7 @@ description: properties: compatible: enum: + - renesas,r9a07g043-sysc # RZ/G2UL - renesas,r9a07g044-sysc # RZ/G2{L,LC} - renesas,r9a07g054-sysc # RZ/V2L -- cgit v1.2.3 From 7663f7a26b335a53102a0893824689182ac64e42 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Wed, 16 Feb 2022 19:31:29 +0800 Subject: dt-bindings: arm: mediatek: Add mt8195 pericfg compatible Add mt8195 pericfg compatible to binding document. Signed-off-by: Tinghan Shen Acked-by: Rob Herring Acked-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220216113131.13145-2-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml index 8723dfe34bab..611f666f359d 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8135-pericfg - mediatek,mt8173-pericfg - mediatek,mt8183-pericfg + - mediatek,mt8195-pericfg - mediatek,mt8516-pericfg - const: syscon - items: -- cgit v1.2.3 From e403fff3b848107e2da92b9a567a926aa5943f7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 2 Apr 2022 23:46:19 +0300 Subject: dt-bindings: arm: bcm: fix BCM53012 and BCM53016 SoC strings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix inaccurate SoC strings brcm,brcm53012 and brcm,brcm53016 to respectively brcm,bcm53012 and brcm,bcm53016. Fixes: 4cb5201fcb5d ("dt-bindings: arm: bcm: Convert BCM4708 to YAML") Fixes: a2e385f5374d ("dt-bindings: ARM: add bindings for the Meraki MR32") Signed-off-by: Arınç ÜNAL Reviewed-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 434d3c6db61e..f0e2a20d22d5 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -84,8 +84,8 @@ properties: - brcm,bcm953012hr - brcm,bcm953012k - meraki,mr32 - - const: brcm,brcm53012 - - const: brcm,brcm53016 + - const: brcm,bcm53012 + - const: brcm,bcm53016 - const: brcm,bcm4708 additionalProperties: true -- cgit v1.2.3 From ca41a8b302601b2547ea8aac4306efd8356d85a6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 2 Apr 2022 23:46:20 +0300 Subject: dt-bindings: arm: bcm: create new description for BCM53016 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Create a new description for BCM53016 and move Meraki MR32 under it. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index f0e2a20d22d5..8a97ee048053 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -83,8 +83,13 @@ properties: - brcm,bcm953012er - brcm,bcm953012hr - brcm,bcm953012k - - meraki,mr32 - const: brcm,bcm53012 + - const: brcm,bcm4708 + + - description: BCM53016 based boards + items: + - enum: + - meraki,mr32 - const: brcm,bcm53016 - const: brcm,bcm4708 -- cgit v1.2.3 From 0346e33d558c3372a5f8138ad8086f9414177a06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 2 Apr 2022 23:46:22 +0300 Subject: dt-bindings: arm: bcm: add bindings for Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Asus RT-AC88U under BCM47094 based boards. Signed-off-by: Arınç ÜNAL Reviewed-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 8a97ee048053..8b7e87fb6c34 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -64,6 +64,7 @@ properties: - description: BCM47094 based boards items: - enum: + - asus,rt-ac88u - dlink,dir-885l - linksys,panamera - luxul,abr-4500-v1 -- cgit v1.2.3 From 1034eb1a6ab812b5c20063a0002de0b3b7f1d9ce Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 23 Feb 2022 00:33:12 +0100 Subject: dt-bindings: arm: ux500: Document Codina-TMO This is a U8500-based phone named Samsung Galaxy Exhibit or Samsung SGH-T599, codenamed "Codina TMO" as it was made for T-Mobile. Cc: phone-devel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220222233313.1774416-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/ux500.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/ux500.yaml b/Documentation/devicetree/bindings/arm/ux500.yaml index a46193ad94e0..17accb31bca0 100644 --- a/Documentation/devicetree/bindings/arm/ux500.yaml +++ b/Documentation/devicetree/bindings/arm/ux500.yaml @@ -40,6 +40,11 @@ properties: - const: samsung,codina - const: st-ericsson,u8500 + - description: Samsung Galaxy Exhibit (SGH-T599) + items: + - const: samsung,codina-tmo + - const: st-ericsson,u8500 + - description: Samsung Galaxy Beam (GT-I8530) items: - const: samsung,gavini -- cgit v1.2.3 From 6d41e13041a306f85ad6cbeb3d532f35cc5cc90a Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:38 +0000 Subject: dt-bindings: watchdog: sunxi: fix F1C100s compatible The F1C100 series actually features a newer generation watchdog IP, so the compatible string was wrong. Signed-off-by: Andre Przywara Reviewed-by: Samuel Holland Acked-by: Rob Herring Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-2-andre.przywara@arm.com --- .../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 43afa24513b9..7a26cde0afdd 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -26,10 +26,8 @@ properties: - allwinner,sun50i-h616-wdt - allwinner,sun50i-r329-wdt - allwinner,sun50i-r329-wdt-reset + - allwinner,suniv-f1c100s-wdt - const: allwinner,sun6i-a31-wdt - - items: - - const: allwinner,suniv-f1c100s-wdt - - const: allwinner,sun4i-a10-wdt - const: allwinner,sun20i-d1-wdt - items: - const: allwinner,sun20i-d1-wdt-reset -- cgit v1.2.3 From 42b91bb160815d82d36cc1cfe28f1edd9079d912 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:39 +0000 Subject: dt-bindings: watchdog: sunxi: clarify clock support Most Allwinner SoCs have just one input clock to drive the watchdog peripheral. So far this is the 24 MHz "HOSC" oscillator, divided down internally to 32 KHz. The F1C100 series watchdog however uses the unchanged 32 KHz "LOSC" as its only clock input, which has the same effect, but let's the binding description mismatch. Change the binding description to name the clocks more loosely, so both the LOSC and divided HOSC match the description. As the fixed clock names now make less sense, drop them from SoCs supporting just one clock input, they were not used by any DT anyway. For the newer SoCs, supporting a choice of two input clocks, we keep both the description and clock-names requirement. Signed-off-by: Andre Przywara Reviewed-by: Guenter Roeck Reviewed-by: Samuel Holland Reviewed-by: Rob Herring Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-3-andre.przywara@arm.com --- .../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 7a26cde0afdd..cbcf19f51411 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -39,14 +39,8 @@ properties: clocks: minItems: 1 items: - - description: High-frequency oscillator input, divided internally - - description: Low-frequency oscillator input, only found on some variants - - clock-names: - minItems: 1 - items: - - const: hosc - - const: losc + - description: 32 KHz input clock + - description: secondary clock source interrupts: maxItems: 1 @@ -71,9 +65,14 @@ then: properties: clocks: minItems: 2 + items: + - description: High-frequency oscillator input, divided internally + - description: Low-frequency oscillator input clock-names: - minItems: 2 + items: + - const: hosc + - const: losc required: - clock-names @@ -83,9 +82,6 @@ else: clocks: maxItems: 1 - clock-names: - maxItems: 1 - unevaluatedProperties: false examples: -- cgit v1.2.3 From fb2dcdd7c44652add88ac518c67b208e5133a7a9 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:41 +0000 Subject: dt-bindings: arm: sunxi: document LicheePi Nano name The top level LicheePi Nano compatible name was never documented in the bindings, so add the currently used string. As for the manufacturer name, Samuel reports: ========== From what I can tell, "Lichee Pi Nano" [1][2] is the original board, and the "Sipeed Lichee Nano" [3] is a newer batch by some of the same people [4]. Other than the silkscreen and the addition of the resistive touchscreen IC, the boards look identical. And in fact I was able to find an intermediate version of the schematic [5] that uses the old styling but includes the touchscreen IC. ========== [1]: https://licheepizero.us/ [2]: http://nano.lichee.pro/ [3]: https://wiki.sipeed.com/hardware/en/lichee/Nano/Nano.html [4]: see e.g. http://bbs.lichee.pro/ [5]: https://github.com/hongxuyao/F1C100s_with_Keil_RTX4_emWin5/blob/spl-separated/doc/lichee-nano/lichee_nano-Schematic.pdf Signed-off-by: Andre Przywara Reviewed-by: Samuel Holland Acked-by: Rob Herring Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-5-andre.przywara@arm.com --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 086c68771d2b..95278a6a9a8e 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -391,6 +391,11 @@ properties: - const: libretech,all-h5-cc-h5 - const: allwinner,sun50i-h5 + - description: Lichee Pi Nano + items: + - const: licheepi,licheepi-nano + - const: allwinner,suniv-f1c100s + - description: Lichee Pi One items: - const: licheepi,licheepi-one -- cgit v1.2.3 From 382e0d4f9ece6d1b282ac70c246bdc7be5edc053 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:47 +0000 Subject: dt-bindings: spi: sunxi: document F1C100 controllers The Allwinner F1C100 series contains two SPI controllers, which are compatible to the IP block used in the Allwinner H3 as well. The only difference in the integration is the missing mod clock in the F1C100, but that does not affect the SPI controller binding, as we can still supply the correct clock (AHB parent) easily. Signed-off-by: Andre Przywara Acked-by: Samuel Holland Acked-by: Rob Herring Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-11-andre.przywara@arm.com --- Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 908248260afa..ca4c95345a49 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -26,6 +26,7 @@ properties: - allwinner,sun8i-r40-spi - allwinner,sun50i-h6-spi - allwinner,sun50i-h616-spi + - allwinner,suniv-f1c100s-spi - const: allwinner,sun8i-h3-spi reg: -- cgit v1.2.3 From 1ceaccf2b267165fcff39e374f8596dfccd2321b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 22:41:15 +0200 Subject: arm64: dts: synaptics: remove unused DTSI for AS370 The as370.dtsi for Synaptics AS370 SoC does not have a user (DTS board file), is uncompilable and untestable. It was added back in 2018. No user appeared since that time, so assume it won't be added. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/syna.txt | 4 ---- 1 file changed, 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/syna.txt b/Documentation/devicetree/bindings/arm/syna.txt index d8b48f2edf1b..851f48ead927 100644 --- a/Documentation/devicetree/bindings/arm/syna.txt +++ b/Documentation/devicetree/bindings/arm/syna.txt @@ -18,10 +18,6 @@ stable binding/ABI. --------------------------------------------------------------- -Boards with the Synaptics AS370 SoC shall have the following properties: - Required root node property: - compatible: "syna,as370" - Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 shall have the following properties: -- cgit v1.2.3 From 6648d167fbd16eaa4ef4972b4904adde2717f722 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Thu, 10 Mar 2022 22:03:50 +0100 Subject: dt-bindings: arm: rockchip: add radxa rock3 model a Add entry for the Radxa ROCK3 Model A board (with the Rockchip RK3568 SoC). Signed-off-by: Michael Riesch Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220310210352.451136-2-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index eece92f83a2d..efb0a9c4347b 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -545,6 +545,11 @@ properties: - const: radxa,rock2-square - const: rockchip,rk3288 + - description: Radxa ROCK3 Model A + items: + - const: radxa,rock3a + - const: rockchip,rk3568 + - description: Rikomagic MK808 v1 items: - const: rikomagic,mk808 -- cgit v1.2.3 From 26ad4834da921ffcadad3ba177dbb137d36c9248 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Feb 2022 13:23:35 +0200 Subject: dt-bindings: omap: Add clock-output-names and #clock-cells This allows us to use clock-output-names for the clock manager instance name instead of relying on non-standard node names. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Acked-by: Rob Herring Message-Id: <20220203112337.19821-1-tony@atomide.com> --- Documentation/devicetree/bindings/arm/omap/prcm.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt index 3eb6d7afff14..431ef8c56a13 100644 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -31,12 +31,17 @@ Required properties: (base address and length) - clocks: clocks for this module - clockdomains: clockdomains for this module +- #clock-cells: From common clock binding +- clock-output-names: From common clock binding + Example: -cm: cm@48004000 { +cm: clock@48004000 { compatible = "ti,omap3-cm"; reg = <0x48004000 0x4000>; + #clock-cells = <0>; + clock-output-names = "cm"; cm_clocks: clocks { #address-cells = <1>; -- cgit v1.2.3 From 8ab423081a263cc84f4377d518d98330d4f78072 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Feb 2022 13:23:36 +0200 Subject: dt-bindings: clock: ti: Add clock-output-names for clockctrl This allows us to use clock-output-names for the clockctrl instance name instead of relying on a custom compatible or non-standard node names. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Acked-by: Rob Herring Message-Id: <20220203112337.19821-2-tony@atomide.com> --- Documentation/devicetree/bindings/clock/ti-clkctrl.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt index 18af6b9409e3..d20db7974a38 100644 --- a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt +++ b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt @@ -21,6 +21,7 @@ Required properties : "ti,clkctrl-l4-per" "ti,clkctrl-l4-secure" "ti,clkctrl-l4-wkup" +- clock-output-names : from common clock binding - #clock-cells : shall contain 2 with the first entry being the instance offset from the clock domain base and the second being the clock index @@ -32,7 +33,8 @@ Example: Clock controller node on omap 4430: l4per: cm@1400 { cm_l4per@0 { cm_l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4_per"; reg = <0x20 0x1b0>; #clock-cells = <2>; }; -- cgit v1.2.3 From fc3d39d5758dc001662df5aac825b2b6bcb6476f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Feb 2022 13:23:37 +0200 Subject: dt-bindings: clock: ti: Add clock-output-names for TI composite clocks For the TI composite clocks, we currently have only the divider clock list clock-output-names as an optional devicetree property. Let's add clock-output-names for all the TI composite clock bindings. This allows us to use clock-output-names for the clockctrl instance name instead of relying on a custom compatible or non-standard node names. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Acked-by: Rob Herring Message-Id: <20220203112337.19821-3-tony@atomide.com> --- Documentation/devicetree/bindings/clock/ti/clockdomain.txt | 3 +++ Documentation/devicetree/bindings/clock/ti/composite.txt | 3 +++ Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt | 1 + Documentation/devicetree/bindings/clock/ti/gate.txt | 1 + Documentation/devicetree/bindings/clock/ti/interface.txt | 1 + Documentation/devicetree/bindings/clock/ti/mux.txt | 1 + 6 files changed, 10 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt index cb76b3f2b341..9c6199249ce5 100644 --- a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt +++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt @@ -17,6 +17,9 @@ Required properties: - #clock-cells : from common clock binding; shall be set to 0. - clocks : link phandles of clocks within this domain +Optional properties: +- clock-output-names : from common clock binding. + Examples: dss_clkdm: dss_clkdm { compatible = "ti,clockdomain"; diff --git a/Documentation/devicetree/bindings/clock/ti/composite.txt b/Documentation/devicetree/bindings/clock/ti/composite.txt index 5f43c4706b09..33ac7c9ad053 100644 --- a/Documentation/devicetree/bindings/clock/ti/composite.txt +++ b/Documentation/devicetree/bindings/clock/ti/composite.txt @@ -27,6 +27,9 @@ Required properties: - clocks : link phandles of component clocks - #clock-cells : from common clock binding; shall be set to 0. +Optional properties: +- clock-output-names : from common clock binding. + Examples: usb_l4_gate_ick: usb_l4_gate_ick { diff --git a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt index 662b36d53bf0..518e3c142276 100644 --- a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt +++ b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt @@ -16,6 +16,7 @@ Required properties: - clocks: parent clock. Optional properties: +- clock-output-names : from common clock binding. - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock, see [2] - reg: offset for the autoidle register of this clock, see [2] diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt index 56d603c1f716..b4820b1de4f0 100644 --- a/Documentation/devicetree/bindings/clock/ti/gate.txt +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt @@ -36,6 +36,7 @@ Required properties: ti,clkdm-gate-clock type Optional properties: +- clock-output-names : from common clock binding. - ti,bit-shift : bit shift for programming the clock gate, invalid for ti,clkdm-gate-clock type - ti,set-bit-to-disable : inverts default gate programming. Setting the bit diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt index 3f4704040140..94ec77dc3c59 100644 --- a/Documentation/devicetree/bindings/clock/ti/interface.txt +++ b/Documentation/devicetree/bindings/clock/ti/interface.txt @@ -28,6 +28,7 @@ Required properties: - reg : base address for the control register Optional properties: +- clock-output-names : from common clock binding. - ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0) Examples: diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt index eec8994b9be8..e17425a58621 100644 --- a/Documentation/devicetree/bindings/clock/ti/mux.txt +++ b/Documentation/devicetree/bindings/clock/ti/mux.txt @@ -42,6 +42,7 @@ Required properties: - reg : register offset for register controlling adjustable mux Optional properties: +- clock-output-names : from common clock binding. - ti,bit-shift : number of bits to shift the bit-mask, defaults to 0 if not present - ti,index-starts-at-one : valid input select programming starts at 1, not -- cgit v1.2.3 From 4185b27b3bef9ce724a3dafd8193c935e845fcdc Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 23 Feb 2022 22:52:47 +0530 Subject: dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for LPASS core clocks and audio clock IDs for LPASS client to request for the clocks. Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Taniya Das Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220223172248.18877-1-tdas@codeaurora.org --- .../bindings/clock/qcom,sc7280-lpasscorecc.yaml | 172 +++++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml new file mode 100644 index 000000000000..bad9135489de --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280 + +maintainers: + - Taniya Das + +description: | + Qualcomm LPASS core and audio clock control module which supports the + clocks and power domains on SC7280. + + See also: + - dt-bindings/clock/qcom,lpasscorecc-sc7280.h + - dt-bindings/clock/qcom,lpassaudiocc-sc7280.h + +properties: + clocks: true + + clock-names: true + + compatible: + enum: + - qcom,sc7280-lpassaoncc + - qcom,sc7280-lpassaudiocc + - qcom,sc7280-lpasscorecc + - qcom,sc7280-lpasshm + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,sc7280-lpassaudiocc + + then: + properties: + clocks: + items: + - description: Board XO source + - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC + + clock-names: + items: + - const: bi_tcxo + - const: lpass_aon_cc_main_rcg_clk_src + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-lpassaoncc + + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board XO active only source + - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: iface + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-lpasshm + - qcom,sc7280-lpasscorecc + + then: + properties: + clocks: + items: + - description: Board XO source + + clock-names: + items: + - const: bi_tcxo + +examples: + - | + #include + #include + #include + #include + lpass_audiocc: clock-controller@3300000 { + compatible = "qcom,sc7280-lpassaudiocc"; + reg = <0x3300000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; + clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; + power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + #include + #include + #include + #include + lpass_hm: clock-controller@3c00000 { + compatible = "qcom,sc7280-lpasshm"; + reg = <0x3c00000 0x28>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + #include + #include + #include + #include + lpasscore: clock-controller@3900000 { + compatible = "qcom,sc7280-lpasscorecc"; + reg = <0x3900000 0x50000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + #include + #include + #include + #include + lpass_aon: clock-controller@3380000 { + compatible = "qcom,sc7280-lpassaoncc"; + reg = <0x3380000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, + <&lpasscore LPASS_CORE_CC_CORE_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao","iface"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + +... -- cgit v1.2.3 From b736cedce53390705887d5188678b0f25a9b9c23 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sat, 26 Feb 2022 11:19:38 +0100 Subject: dt-bindings: arm: qcom: Document asus,sparrow device Document the ASUS ZenWatch 2 ("sparrow") which is a smartwatch based on Snapdragon 400 SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226101939.1011551-1-luca@z3ntu.xyz --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 129cdd246223..7f89ab344d3f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -99,6 +99,7 @@ properties: - items: - enum: + - asus,sparrow - lg,lenok - const: qcom,apq8026 -- cgit v1.2.3 From 05d39fc06cee5b11b195d0d5fec55d01da2781cb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 08:32:34 +0100 Subject: dt-bindings: arm: renesas: Document Renesas RZ/G2UL SMARC EVK Document the Renesas SMARC EVK board which is based on the Renesas RZ/G2UL Type-1 (R9A07G043U11) SoC. The SMARC EVK consists of an RZ/G2UL Type-1 SoM module and a SMARC carrier board. The SoM module sits on top of the carrier board. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220402073234.24625-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index fa435d6fda77..f61807103867 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -405,6 +405,8 @@ properties: - description: RZ/G2UL (R9A07G043) items: + - enum: + - renesas,smarc-evk # SMARC EVK - enum: - renesas,r9a07g043u11 # RZ/G2UL Type-1 - renesas,r9a07g043u12 # RZ/G2UL Type-2 -- cgit v1.2.3 From ad984c428c311a7df4b33c038be40d795a9299bf Mon Sep 17 00:00:00 2001 From: William Zhang Date: Wed, 13 Apr 2022 12:26:41 -0700 Subject: dt-bindings: arm: add bcmbca device tree binding document Add arch bcmbca device tree binding document for Broadcom ARM based broadband SoC chipsets. In this change, only BCM47622 is added. Other chipsets will be added in the future. Signed-off-by: William Zhang Acked-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- .../devicetree/bindings/arm/bcm/brcm,bcmbca.yaml | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml new file mode 100644 index 000000000000..5fb455840417 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcmbca.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Broadband SoC device tree bindings + +description: + Broadcom Broadband SoCs include family of high performance DSL/PON/Wireless + chips that can be used as home gateway, router and WLAN AP for residential, + enterprise and carrier applications. + +maintainers: + - William Zhang + - Anand Gore + - Kursad Oney + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BCM47622 based boards + items: + - enum: + - brcm,bcm947622 + - const: brcm,bcm47622 + - const: brcm,bcmbca + +additionalProperties: true + +... -- cgit v1.2.3 From 6cd3233242eebfd81c8eb83fa965959471a2cd97 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 20 Apr 2022 17:42:41 +0900 Subject: dt-bindings: arm: renesas: Document R-Car V4H White Hawk DT bindings Add device tree binding documentation for the Renesas R-Car V4H (r8a779g0) SoC and the Renesas White Hawk CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220420084255.375700-2-yoshihiro.shimoda.uh@renesas.com Link: https://lore.kernel.org/r/20220420084255.375700-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index f61807103867..5408b154d05e 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -327,6 +327,18 @@ properties: - const: renesas,spider-cpu - const: renesas,r8a779f0 + - description: R-Car V4H (R8A779G0) + items: + - enum: + - renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000) + - const: renesas,r8a779g0 + + - items: + - enum: + - renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000) + - const: renesas,white-hawk-cpu + - const: renesas,r8a779g0 + - description: R-Car H3e (R8A779M0) items: - enum: -- cgit v1.2.3 From 8ff93be3259fda0f7b7667ee1717b1dc9c4c8d07 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 20 Apr 2022 17:42:43 +0900 Subject: dt-bindings: reset: renesas,rst: Document r8a779g0 reset module Document bindings for the R-Car V4H (R8A779G0) reset module. Signed-off-by: Yoshihiro Shimoda Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220420084255.375700-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/reset/renesas,rst.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml index bbe313bf1796..0d1b89e2fe9c 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml @@ -49,6 +49,7 @@ properties: - renesas,r8a77995-rst # R-Car D3 - renesas,r8a779a0-rst # R-Car V3U - renesas,r8a779f0-rst # R-Car S4-8 + - renesas,r8a779g0-rst # R-Car V4H reg: maxItems: 1 -- cgit v1.2.3 From 41e3958475ed3f9ad09facbe04cb8eafcee14546 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Fri, 8 Apr 2022 14:19:21 +0100 Subject: dt-bindings: Add Arm corstone1000 platform Add bindings to describe the FPGA in a prototyping board (MPS3) implementation and the Fixed Virtual Platform implementation of the ARM Corstone1000 platform. Link: https://lore.kernel.org/r/20220408131922.3864348-2-rui.silva@linaro.org Reviewed-by: Rob Herring Signed-off-by: Rui Miguel Silva Signed-off-by: Sudeep Holla --- .../devicetree/bindings/arm/arm,corstone1000.yaml | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml new file mode 100644 index 000000000000..a77f88223801 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Corstone1000 Device Tree Bindings + +maintainers: + - Vishnu Banavath + - Rui Miguel Silva + +description: |+ + ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that + provides a flexible compute architecture that combines Cortex‑A and Cortex‑M + processors. + + Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion + systems for M-Class (or other) processors for adding sensors, connectivity, + video, audio and machine learning at the edge System and security IPs to build + a secure SoC for a range of rich IoT applications, for example gateways, smart + cameras and embedded systems. + + Integrated Secure Enclave providing hardware Root of Trust and supporting + seamless integration of the optional CryptoCell™-312 cryptographic + accelerator. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA + implementation of the Corstone1000 in the MPS3 prototyping board. See + ARM document DAI0550. + items: + - const: arm,corstone1000-mps3 + - description: Corstone1000 FVP is the Fixed Virtual Platform + implementation of this system. See ARM ecosystems FVP's. + items: + - const: arm,corstone1000-fvp + +additionalProperties: true + +... -- cgit v1.2.3 From b59add5e6e5a66ae3f6a42a573b6e56b6dbaee41 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 19 Apr 2022 17:20:30 +0800 Subject: dt-bindings: arm: Add compatible for Mediatek MT8192 This commit adds dt-binding documentation for the Mediatek MT8192 reference board. Signed-off-by: Allen-KH Cheng Link: https://lore.kernel.org/r/20220419092030.30519-1-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index ab0593c77321..3a9b92ee915b 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -131,6 +131,10 @@ properties: - enum: - mediatek,mt8183-evb - const: mediatek,mt8183 + - items: + - enum: + - mediatek,mt8192-evb + - const: mediatek,mt8192 - items: - enum: - mediatek,mt8195-evb -- cgit v1.2.3 From cc9d1e59f47562a3b9c812c29d84996e36234308 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Fri, 15 Apr 2022 17:00:00 +0200 Subject: dt-bindings: arm64: dts: mediatek: Add mt8195-demo board Add bindings for the MediaTek mt8195-demo board. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220415150003.1793063-2-fparent@baylibre.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 3a9b92ee915b..4a2bd9759c47 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -137,6 +137,7 @@ properties: - const: mediatek,mt8192 - items: - enum: + - mediatek,mt8195-demo - mediatek,mt8195-evb - const: mediatek,mt8195 - description: Google Burnet (HP Chromebook x360 11MK G3 EE) -- cgit v1.2.3 From 7a5ae564198d536a53bb11ed0eb6679ee0fced10 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 20 Apr 2022 17:42:44 +0900 Subject: dt-bindings: power: renesas,rcar-sysc: Document r8a779g0 SYSC bindings Document bindings for the R-Car V4H (aka R8A779G0) SYSC block. Signed-off-by: Yoshihiro Shimoda Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220420084255.375700-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml index 62a49ca319ec..72039401af3d 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml @@ -42,6 +42,7 @@ properties: - renesas,r8a77995-sysc # R-Car D3 - renesas,r8a779a0-sysc # R-Car V3U - renesas,r8a779f0-sysc # R-Car S4-8 + - renesas,r8a779g0-sysc # R-Car V4H reg: maxItems: 1 -- cgit v1.2.3 From 358d1cef2a88f590a183a0357b944674097ec0ab Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 30 Mar 2022 16:40:12 +0100 Subject: dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK board Details of the SoC can be found here: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output The RZ/V2M Evaluation Kit (V2MEVK) consists of the RZ/V2M Main Board, RZ/V2M Base Board, and CIS IMX415 Board (CIS). Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220330154024.112270-2-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 5408b154d05e..ff80152f092f 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -444,6 +444,12 @@ properties: - renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L - const: renesas,r9a07g054 + - description: RZ/V2M (R9A09G011) + items: + - enum: + - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0 + - const: renesas,r9a09g011 + additionalProperties: true ... -- cgit v1.2.3 From e2ab93e59bc3c029b61a7091825f193f1a66a1a1 Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Tue, 26 Apr 2022 13:08:26 +0530 Subject: dt-bindings: memory: tegra: Update validation for reg and reg-names From Tegra186 onwards, memory controller support multiple channels. "reg" items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and Tegra234 have overall 17 memory controller channels each. There is one "reg" entry for memory controller stream-ID registers. So update the "reg" property's "minItems" and "maxItems" accordingly in the Tegra186 devicetree documentation. Also update validation for "reg-names" added for these corresponding "reg" items. ABI change due to new bindings is intended but backward compatibility is preserved in driver. Reviewed-by: Rob Herring Signed-off-by: Ashish Mhetre Signed-off-by: Thierry Reding --- .../memory-controllers/nvidia,tegra186-mc.yaml | 80 ++++++++++++++++++++-- 1 file changed, 74 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 13c4c82fd0d3..c7cfa6c2cd81 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -34,8 +34,12 @@ properties: - nvidia,tegra234-mc reg: - minItems: 1 - maxItems: 3 + minItems: 6 + maxItems: 18 + + reg-names: + minItems: 6 + maxItems: 18 interrupts: items: @@ -142,7 +146,18 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 for stream-id registers + + reg-names: + maxItems: 6 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 - if: properties: @@ -151,7 +166,30 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 - if: properties: @@ -160,13 +198,37 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 additionalProperties: false required: - compatible - reg + - reg-names - interrupts - "#address-cells" - "#size-cells" @@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = ; #address-cells = <2>; -- cgit v1.2.3 From c37415f55bdadffe5b4c0e7981e9fc7e8b96beea Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 07:52:46 -0400 Subject: dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B The Quartz64 Model B is a compact single board computer from Pine64 based on the rk3566 SoC. It outputs on uart2 for the debug console. Signed-off-by: Peter Geis Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220429115252.2360496-2-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index efb0a9c4347b..6fa95ff92a98 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -502,9 +502,11 @@ properties: - const: pine64,rockpro64 - const: rockchip,rk3399 - - description: Pine64 Quartz64 Model A + - description: Pine64 Quartz64 Model A/B items: - - const: pine64,quartz64-a + - enum: + - pine64,quartz64-a + - pine64,quartz64-b - const: rockchip,rk3566 - description: Radxa Rock -- cgit v1.2.3 From c466828fb3ba8cb7f5c3bf28766da9b70bf9745e Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 07:52:47 -0400 Subject: dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM The SoQuartz system on module is designed to be pin compatible with the RPi CM4 SoM. It is based on the rk3566 SoC and outputs on uart2 for debug and console. The first carrier board supported is the CM4IO board from RPi. Signed-off-by: Peter Geis Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220429115252.2360496-3-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 6fa95ff92a98..ea8dcbc5106f 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -509,6 +509,13 @@ properties: - pine64,quartz64-b - const: rockchip,rk3566 + - description: Pine64 SoQuartz SoM + items: + - enum: + - pine64,soquartz-cm4io + - const: pine64,soquartz + - const: rockchip,rk3566 + - description: Radxa Rock items: - const: radxa,rock -- cgit v1.2.3 From e52ded5543708e0382f236ce35372a63f4568341 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 07:52:48 -0400 Subject: dt-bindings: arm: rockchip: Add Firefly Station M2 The Station M2 is a compact single board computer based on the rk3566 SoC. It outputs on uart2 for debug and console purposes. Signed-off-by: Peter Geis Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220429115252.2360496-4-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index ea8dcbc5106f..cf9eb1e8326a 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -133,6 +133,11 @@ properties: - firefly,roc-rk3399-pc-plus - const: rockchip,rk3399 + - description: Firefly Station M2 + items: + - const: firefly,rk3566-roc-pc + - const: rockchip,rk3566 + - description: FriendlyElec NanoPi R2S items: - const: friendlyarm,nanopi-r2s -- cgit v1.2.3 From bb419dc67bb51d15740df5a775da1de057e4b2fb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 25 Apr 2022 16:04:35 +0200 Subject: dt-bindings: arm: stm32: narrow DH STM32MP1 SoM boards The bindings for DH STM32MP1 SoM boards allows invalid combinations, e.g. st,stm32mp153 SoC on a dh,stm32mp157c-dhcom-som SoM. Split the enums to properly match valid setups. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- .../devicetree/bindings/arm/stm32/stm32.yaml | 37 +++++++++++++--------- 1 file changed, 22 insertions(+), 15 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index fa0a1b84122e..2f83f2760e6a 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -14,21 +14,6 @@ properties: const: "/" compatible: oneOf: - - description: DH STM32MP1 SoM based Boards - items: - - enum: - - arrow,stm32mp157a-avenger96 # Avenger96 - - dh,stm32mp153c-dhcom-drc02 - - dh,stm32mp157c-dhcom-pdk2 - - dh,stm32mp157c-dhcom-picoitx - - enum: - - dh,stm32mp153c-dhcom-som - - dh,stm32mp157a-dhcor-som - - dh,stm32mp157c-dhcom-som - - enum: - - st,stm32mp153 - - st,stm32mp157 - - description: emtrion STM32MP1 Argon based Boards items: - const: emtrion,stm32mp157c-emsbc-argon @@ -65,6 +50,13 @@ properties: - enum: - st,stm32mp135f-dk - const: st,stm32mp135 + + - description: DH STM32MP153 SoM based Boards + items: + - const: dh,stm32mp153c-dhcom-drc02 + - const: dh,stm32mp153c-dhcom-som + - const: st,stm32mp153 + - items: - enum: - shiratech,stm32mp157a-iot-box # IoT Box @@ -79,6 +71,21 @@ properties: - const: st,stm32mp157c-ed1 - const: st,stm32mp157 + - description: DH STM32MP1 SoM based Boards + items: + - enum: + - arrow,stm32mp157a-avenger96 # Avenger96 + - const: dh,stm32mp157a-dhcor-som + - const: st,stm32mp157 + + - description: DH STM32MP1 SoM based Boards + items: + - enum: + - dh,stm32mp157c-dhcom-pdk2 + - dh,stm32mp157c-dhcom-picoitx + - const: dh,stm32mp157c-dhcom-som + - const: st,stm32mp157 + - description: Engicam i.Core STM32MP1 SoM based Boards items: - enum: -- cgit v1.2.3 From 5d68f9798d7da8a1004d3d09e56dc7b379700016 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 25 Apr 2022 16:04:36 +0200 Subject: dt-bindings: arm: stm32: correct blank lines Correct blank lines to precesily separate entries. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 2f83f2760e6a..80b29f6903f0 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -64,8 +64,8 @@ properties: - st,stm32mp157c-ed1 - st,stm32mp157a-dk1 - st,stm32mp157c-dk2 - - const: st,stm32mp157 + - items: - const: st,stm32mp157c-ev1 - const: st,stm32mp157c-ed1 @@ -110,6 +110,7 @@ properties: - const: oct,stm32mp15xx-osd32 - enum: - st,stm32mp157 + - description: Odyssey STM32MP1 SoM based Boards items: - enum: -- cgit v1.2.3 From c70bb467fb211fadd2c1360892a498330d8a94a6 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 26 Apr 2022 09:35:08 +0200 Subject: dt-bindings: arm: stm32: Add compatible strings for Protonic T1L boards This boards are based on STM32MP151AAD3 and use 10BaseT1L for communication. - PRTT1C - 10BaseT1L switch - PRTT1S - 10BaseT1L CO2 sensor board - PRTT1A - 10BaseT1L multi functional controller Signed-off-by: Oleksij Rempel Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 80b29f6903f0..a93c60241f28 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -51,6 +51,14 @@ properties: - st,stm32mp135f-dk - const: st,stm32mp135 + - description: ST STM32MP151 based Boards + items: + - enum: + - prt,prtt1a # Protonic PRTT1A + - prt,prtt1c # Protonic PRTT1C + - prt,prtt1s # Protonic PRTT1S + - const: st,stm32mp151 + - description: DH STM32MP153 SoM based Boards items: - const: dh,stm32mp153c-dhcom-drc02 -- cgit v1.2.3 From 94de07e5565be51d91dd91dcae6ede54c0f9be27 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 26 Apr 2022 09:35:09 +0200 Subject: dt-bindings: net: silabs,wfx: add prt,prtt1c-wfm200 antenna variant Add compatible for wfm200 antenna configuration variant for Protonic PRTT1C board. Signed-off-by: Oleksij Rempel Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml b/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml index 105725a127ab..ce107fe45d7c 100644 --- a/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml +++ b/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml @@ -39,6 +39,7 @@ properties: compatible: items: - enum: + - prt,prtt1c-wfm200 # Protonic PRTT1C Board - silabs,brd4001a # WGM160P Evaluation Board - silabs,brd8022a # WF200 Evaluation Board - silabs,brd8023a # WFM200 Evaluation Board -- cgit v1.2.3 From 6e5b6ce2053c3a7ba94d93962e66b5240e286279 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 11 Apr 2022 00:05:14 +0200 Subject: dt-bindings: rcc: Add optional external ethernet RX clock properties Describe optional external ethernet RX clock in the DT binding to fix dtbs_check warnings like: arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dt.yaml: rcc@50000000: 'assigned-clock-parents', 'assigned-clock-rates', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Gabriel Fernandez Cc: Rob Herring To: devicetree@vger.kernel.org Acked-by: Gabriel Fernandez Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220410220514.21779-1-marex@denx.de Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index a0ae4867ed27..7a251264582d 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -59,6 +59,14 @@ properties: - st,stm32mp1-rcc - const: syscon + clocks: + description: + Specifies the external RX clock for ethernet MAC. + maxItems: 1 + + clock-names: + const: ETH_RX_CLK/ETH_REF_CLK + reg: maxItems: 1 -- cgit v1.2.3 From 35de4b4b82bcfaa5a33fd02e74a453fc67b3b1ec Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:46 +0200 Subject: dt-bindings: clock: stm32mp1: describes clocks if "st,stm32mp1-rcc-secure" In case of "st,stm32mp1-rcc-secure" (stm32mp1 clock driver with RCC security support hardened), "clocks" and "clock-names" describe oscillators and are required. Signed-off-by: Alexandre Torgue Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/st,stm32mp1-rcc.yaml | 42 +++++++++++++++++----- 1 file changed, 34 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index 7a251264582d..bb0e0b92e907 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -58,14 +58,8 @@ properties: - st,stm32mp1-rcc-secure - st,stm32mp1-rcc - const: syscon - - clocks: - description: - Specifies the external RX clock for ethernet MAC. - maxItems: 1 - - clock-names: - const: ETH_RX_CLK/ETH_REF_CLK + clocks: true + clock-names: true reg: maxItems: 1 @@ -76,6 +70,38 @@ required: - compatible - reg +if: + properties: + compatible: + contains: + enum: + - st,stm32mp1-rcc-secure +then: + properties: + clocks: + description: Specifies oscillators. + maxItems: 5 + + clock-names: + items: + - const: hse + - const: hsi + - const: csi + - const: lse + - const: lsi + required: + - clocks + - clock-names +else: + properties: + clocks: + description: + Specifies the external RX clock for ethernet MAC. + maxItems: 1 + + clock-names: + const: ETH_RX_CLK/ETH_REF_CLK + additionalProperties: false examples: -- cgit v1.2.3 From 8e14ebb1f08f036539c8cd362a9fd173c4befa2a Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:51 +0200 Subject: dt-bindings: arm: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1) Add a "secure" version based on SCMI of STM32 boards. Only boards provided by STMicroelectronics are concerned: -STM32MP157A-DK1 -STM32MP157C-DK2 -STM32MP157C-ED1 -STM32MP157C-EV1 Signed-off-by: Alexandre Torgue Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index a93c60241f28..8b31565fee59 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -75,6 +75,23 @@ properties: - const: st,stm32mp157 - items: + - const: st,stm32mp157a-dk1-scmi + - const: st,stm32mp157a-dk1 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-dk2-scmi + - const: st,stm32mp157c-dk2 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ed1-scmi + - const: st,stm32mp157c-ed1 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ev1 + - const: st,stm32mp157c-ed1 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ev1-scmi - const: st,stm32mp157c-ev1 - const: st,stm32mp157c-ed1 - const: st,stm32mp157 -- cgit v1.2.3 From 8b3dd27bfe47abe30450d01077983497aa1a159f Mon Sep 17 00:00:00 2001 From: Paul Elder Date: Wed, 6 Apr 2022 17:33:54 +0200 Subject: dt-bindings: soc: Add i.MX8MP media block control DT bindings The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral providing access to the NoC and ensuring proper power sequencing of the peripherals within the MEDIAMIX domain. Add DT bindings for it. There is already a driver for block controls of other SoCs in the i.MX8M family, so these bindings will expand upon that. Signed-off-by: Paul Elder Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart Reviewed-by: Marek Vasut Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml | 104 +++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml new file mode 100644 index 000000000000..21d3ee486295 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MP Media Block Control + +maintainers: + - Paul Elder + +description: + The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral + providing access to the NoC and ensuring proper power sequencing of the + peripherals within the MEDIAMIX domain. + +properties: + compatible: + items: + - const: fsl,imx8mp-media-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + maxItems: 10 + + power-domain-names: + items: + - const: bus + - const: mipi-dsi1 + - const: mipi-csi1 + - const: lcdif1 + - const: isi + - const: mipi-csi2 + - const: lcdif2 + - const: isp + - const: dwe + - const: mipi-dsi2 + + clocks: + items: + - description: The APB clock + - description: The AXI clock + - description: The pixel clock for the first CSI2 receiver (aclk) + - description: The pixel clock for the second CSI2 receiver (aclk) + - description: The pixel clock for the first LCDIF (pix_clk) + - description: The pixel clock for the second LCDIF (pix_clk) + - description: The core clock for the ISP (clk) + - description: The MIPI-PHY reference clock used by DSI + + clock-names: + items: + - const: apb + - const: axi + - const: cam1 + - const: cam2 + - const: disp1 + - const: disp2 + - const: isp + - const: phy + +required: + - compatible + - reg + - '#power-domain-cells' + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + media_blk_ctl: blk-ctl@32ec0000 { + compatible = "fsl,imx8mp-media-blk-ctrl", "syscon"; + reg = <0x32ec0000 0x138>; + power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>, + <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>, + <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>, + <&mipi_phy2_pd>; + power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi", + "mipi-csi2", "lcdif2", "isp1", "dwe", "mipi-dsi2"; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; + clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2", + "isp", "phy"; + #power-domain-cells = <1>; + }; +... -- cgit v1.2.3 From e95a7329f83781916ff5c1a52c1f7641757ff1e2 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Apr 2022 17:33:57 +0200 Subject: dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl Add the DT binding for the HDMI blk-ctrl found on the i.MX8MP SoC. Signed-off-by: Lucas Stach Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml new file mode 100644 index 000000000000..563e1d0e327f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MP HDMI blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the display pipeline + peripherals located in the HDMI domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mp-hdmi-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 8 + maxItems: 8 + + power-domain-names: + items: + - const: bus + - const: irqsteer + - const: lcdif + - const: pai + - const: pvi + - const: trng + - const: hdmi-tx + - const: hdmi-tx-phy + + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: apb + - const: axi + - const: ref_266m + - const: ref_24m + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + blk-ctrl@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; + reg = <0x32fc0000 0x23c>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names = "apb", "axi", "ref_266m", "ref_24m"; + power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmi_phy>; + power-domain-names = "bus", "irqsteer", "lcdif", "pai", "pvi", "trng", + "hdmi-tx", "hdmi-tx-phy"; + #power-domain-cells = <1>; + }; -- cgit v1.2.3 From eca2eee48d78af51bddacbd40844fb2ce3767616 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 21 Feb 2022 01:17:37 +0100 Subject: dt-bindings: arm: Add Data Modul i.MX8M Mini eDM SBC Add DT compatible string for Data Modul i.MX8M Mini eDM SBC board into YAML DT binding document. This system is an evaluation board for various custom display units. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Rob Herring Cc: Shawn Guo Cc: NXP Linux Team Cc: devicetree@vger.kernel.org To: linux-arm-kernel@lists.infradead.org Reviewed-by: Peng Fan Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 08bdd30e511c..55d6e866acb9 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -762,6 +762,7 @@ properties: - enum: - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit - boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board + - dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC - emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board -- cgit v1.2.3 From 5c35e2284103ea2674d95a7532d6d4e2bb759553 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Tue, 22 Feb 2022 08:09:41 +0100 Subject: dt-bindings: arm: fsl: add TQ Systems boards based on i.MX6UL(L) TQMa6ULx is a SOM family using NXP i.MX6UL CPU family. TQMa6ULLx is a SOM family using NXP i.MX6ULL CPU family. Both are available as a socket type as well as an LGA type. For both variants there are the mainboards MBa6ULx and MBa6ULxL, trailing 'L' is LGA version. Finally there is the possibility to use the socket module with an LGA adapter on the MBa6ULxL. The SOM needs a mainboard, therefore we provide compatibles using this naming schema: "tq,imx6ul-" for the module and "tq,imx6ul--" for when mounted on the mainboard. The i.MX6ULL version is done similar. Signed-off-by: Matthias Schiffer Acked-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 55d6e866acb9..09bb76bf24b6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -613,6 +613,28 @@ properties: - const: kontron,imx6ul-n6310-som - const: fsl,imx6ul + - description: TQ-Systems TQMa6UL1 SoM on MBa6ULx board + items: + - enum: + - tq,imx6ul-tqma6ul1-mba6ulx + - const: tq,imx6ul-tqma6ul1 # MCIMX6G1 + - const: fsl,imx6ul + + - description: TQ-Systems TQMa6UL2 SoM on MBa6ULx board + items: + - enum: + - tq,imx6ul-tqma6ul2-mba6ulx + - const: tq,imx6ul-tqma6ul2 # MCIMX6G2 + - const: fsl,imx6ul + + - description: TQ-Systems TQMa6ULxL SoM on MBa6ULx[L] board + items: + - enum: + - tq,imx6ul-tqma6ul2l-mba6ulx # using LGA adapter + - tq,imx6ul-tqma6ul2l-mba6ulxl + - const: tq,imx6ul-tqma6ul2l # MCIMX6G2, LGA SoM variant + - const: fsl,imx6ul + - description: i.MX6ULL based Boards items: - enum: @@ -667,6 +689,21 @@ properties: - const: kontron,imx6ull-n6411-som - const: fsl,imx6ull + - description: TQ Systems TQMa6ULLx SoM on MBa6ULx board + items: + - enum: + - tq,imx6ull-tqma6ull2-mba6ulx + - const: tq,imx6ull-tqma6ull2 # MCIMX6Y2 + - const: fsl,imx6ull + + - description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board + items: + - enum: + - tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter + - tq,imx6ull-tqma6ull2l-mba6ulxl + - const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant + - const: fsl,imx6ull + - description: i.MX6ULZ based Boards items: - enum: -- cgit v1.2.3 From 5a10857a8e35c71f526965211759dffbc54b5827 Mon Sep 17 00:00:00 2001 From: Andrej Picej Date: Tue, 22 Feb 2022 10:16:04 +0100 Subject: dt-bindings: arm: fsl: add PHYTEC phyGATE Tauri i.MX6 ULL Add devicetree bindings for phyGATE Tauri board with phyCORE-i.MX6 ULL. Signed-off-by: Andrej Picej Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 09bb76bf24b6..03b8d8cf2c6b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -662,6 +662,15 @@ properties: - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyGATE-Tauri + items: + - enum: + - phytec,imx6ull-phygate-tauri-emmc + - phytec,imx6ull-phygate-tauri-nand + - const: phytec,imx6ull-phygate-tauri # PHYTEC phyGATE-Tauri with i.MX6 ULL + - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL + - const: fsl,imx6ull + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: -- cgit v1.2.3 From afd406d7328e93bf99467e9ad866c34beb9f306f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 7 Apr 2022 21:21:41 +0200 Subject: dt-bindings: arm: Add i.MX53 based Menlo board comment Add comment regarding the i.MX53 based Menlo board. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Rob Herring Cc: Shawn Guo Cc: NXP Linux Team Cc: devicetree@vger.kernel.org To: linux-arm-kernel@lists.infradead.org Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 03b8d8cf2c6b..8a7ed7782e99 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -172,7 +172,7 @@ properties: - karo,tx53 # Ka-Ro electronics TX53 module - kiebackpeter,imx53-ddc # K+P imx53 DDC - kiebackpeter,imx53-hsc # K+P imx53 HSC - - menlo,m53menlo + - menlo,m53menlo # i.MX53 Menlo board - voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668 - const: fsl,imx53 -- cgit v1.2.3 From a84091746e50111b0dd6722eca7230d5719ffd18 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 8 Apr 2022 16:57:24 +0200 Subject: dt-bindings: arm: fsl: add toradex,verdin-imx8mp et al. Add toradex,verdin-imx8mp for the Verdin iMX8M Plus modules, its nonwifi and wifi variants and the carrier boards (both Dahlia and the Verdin Development Board) they may be mated in. Signed-off-by: Marcel Ziswiler Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 8a7ed7782e99..b6cc34115362 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -907,6 +907,9 @@ properties: items: - enum: - fsl,imx8mp-evk # i.MX8MP EVK Board + - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules + - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT + - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules - const: fsl,imx8mp - description: PHYTEC phyCORE-i.MX8MP SoM based boards @@ -915,6 +918,24 @@ properties: - const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM - const: fsl,imx8mp + - description: Toradex Boards with Verdin iMX8M Plus Modules + items: + - enum: + - toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia + - toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board + - const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT + - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module + - const: fsl,imx8mp + + - description: Toradex Boards with Verdin iMX8M Plus Wi-Fi / BT Modules + items: + - enum: + - toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia + - toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B. + - const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module + - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module + - const: fsl,imx8mp + - description: i.MX8MQ based Boards items: - enum: -- cgit v1.2.3 From 31963ac56eb5ff6af62787128d635975d8d103e5 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:21 +0200 Subject: dt-bindings: arm: fsl: imx6dl-colibri: Drop dedicated v1.1 bindings The dedicated device tree for V1.1 modules has been dropped. Remove its bindings too. Acked-by: Rob Herring Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 8 -------- 1 file changed, 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b6cc34115362..5b434e21844f 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -411,7 +411,6 @@ properties: - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 - toradex,colibri_imx6dl # Colibri iMX6 Modules - - toradex,colibri_imx6dl-v1_1 # Colibri iMX6 V1.1 Modules - udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board - vdl,lanmcu # Van der Laan LANMCU board - wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board @@ -492,13 +491,6 @@ properties: - const: toradex,colibri_imx6dl # Colibri iMX6DL/S Module - const: fsl,imx6dl - - description: i.MX6DL Boards with Toradex Colibri iMX6DL/S V1.1 Modules - items: - - enum: - - toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6DL/S V1.1 M. on Colibri Evaluation Board V3 - - const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6DL/S V1.1 Module - - const: fsl,imx6dl - - description: i.MX6S DHCOM DRC02 Board items: - const: dh,imx6s-dhcom-drc02 -- cgit v1.2.3 From 9eef821d3b84c866acbe58a0964e2756990523e9 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:22 +0200 Subject: dt-bindings: arm: fsl: Add carriers for toradex,colibri-imx6dl Add bindings for Aster, Iris and Iris V2 carrier boards our Colibri iMX6S/DL may be mated with. Acked-by: Rob Herring Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 5b434e21844f..b71fb76d95ee 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -487,7 +487,10 @@ properties: - description: i.MX6DL Boards with Toradex Colibri iMX6DL/S Modules items: - enum: + - toradex,colibri_imx6dl-aster # Colibri iMX6DL/S Module on Aster Board - toradex,colibri_imx6dl-eval-v3 # Colibri iMX6DL/S Module on Colibri Evaluation Board V3 + - toradex,colibri_imx6dl-iris # Colibri iMX6DL/S Module on Iris Board + - toradex,colibri_imx6dl-iris-v2 # Colibri iMX6DL/S Module on Iris Board V2 - const: toradex,colibri_imx6dl # Colibri iMX6DL/S Module - const: fsl,imx6dl -- cgit v1.2.3 From 84cb08ca541437b061f9d901f3c637d93ebebb2e Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 12 Apr 2022 16:32:37 +0200 Subject: dt-bindings: arm: fsl: add IMX8MN DDR3L eval board This eval board features an IMX8MN UltraLite and has DDR3L RAM. The product part number is 8MNANOD3L-EVK. Signed-off-by: Michael Walle Reviewed-by: Heiko Thiery Acked-by: Krzysztof Kozlowski Acked-by: Peng Fan Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b71fb76d95ee..065336080c46 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -876,6 +876,7 @@ properties: - beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit - bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2 - bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO + - fsl,imx8mn-ddr3l-evk # i.MX8MN DDR3L EVK Board - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board - gw,imx8mn-gw7902 # i.MX8MM Gateworks Board -- cgit v1.2.3 From bed5522940e08ee9b2dc802e4ef53a09e27975e8 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 14 Apr 2022 09:15:04 -0700 Subject: dt-bindings: arm: Add i.MX8M Plus Gateworks GW74xx board Add DT compatible string for i.MX8M Plus based Gateworks GW74xx board. Signed-off-by: Tim Harvey Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 065336080c46..13aee9fe115e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -903,6 +903,7 @@ properties: items: - enum: - fsl,imx8mp-evk # i.MX8MP EVK Board + - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules -- cgit v1.2.3 From 1299bb1d2e9adbd4e64c7bbd572d67cff09851fd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 18 Apr 2022 15:24:56 +0200 Subject: dt-bindings: arm: Add i.MX8M Mini Toradex Verdin based Menlo board Add DT compatible string for board based on the Toradex Verdin iMX8M Mini SoM, the MX8Menlo. The board is a compatible replacement for i.MX53 M53Menlo and features USB, multiple UARTs, ethernet, LEDs, SD and eMMC. Acked-by: Peng Fan Acked-by: Rob Herring Reviewed-by: Fabio Estevam Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Francesco Dolcini Cc: Marcel Ziswiler Cc: Peng Fan Cc: Rob Herring Cc: Shawn Guo Cc: NXP Linux Team Cc: devicetree@vger.kernel.org To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 13aee9fe115e..754351643cff 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -814,6 +814,7 @@ properties: - gw,imx8mm-gw7902 # i.MX8MM Gateworks Board - gw,imx8mm-gw7903 # i.MX8MM Gateworks Board - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM + - menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT - toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules -- cgit v1.2.3 From cff15d3ee66d0412f36fc927a19b27fcc3f9dc20 Mon Sep 17 00:00:00 2001 From: Changming Huang Date: Wed, 20 Apr 2022 10:35:55 +0800 Subject: dt-bindings: arm: fsl: add ls1021a-iot board Add the board ls1021a-iot in the binding docuemnt. Signed-off-by: Changming Huang Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 754351643cff..b8b0efa55339 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1065,6 +1065,7 @@ properties: - description: LS1021A based Boards items: - enum: + - fsl,ls1021a-iot - fsl,ls1021a-moxa-uc-8410a - fsl,ls1021a-qds - fsl,ls1021a-tsn -- cgit v1.2.3 From 7a0a377425210eb2cdee394db73136631d5dd204 Mon Sep 17 00:00:00 2001 From: Manoj Sai Date: Mon, 25 Apr 2022 19:12:22 +0530 Subject: dt-bindings: arm: fsl: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam. i.Core MX8M Plus needs to mount on top of this Evaluation board for creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit. Add bindings for it. Signed-off-by: Manoj Sai Reviewed-by: Jagan Teki Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b8b0efa55339..d1d79889227e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -910,6 +910,13 @@ properties: - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules - const: fsl,imx8mp + - description: Engicam i.Core MX8M Plus SoM based boards + items: + - enum: + - engicam,icore-mx8mp-edimm2.2 # i.MX8MP Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit + - const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM + - const: fsl,imx8mp + - description: PHYTEC phyCORE-i.MX8MP SoM based boards items: - const: phytec,imx8mp-phyboard-pollux-rdk # phyBOARD-Pollux RDK -- cgit v1.2.3 From b1f7836d93baff7c8c1e8550e089190d118a95f7 Mon Sep 17 00:00:00 2001 From: Denys Drozdov Date: Mon, 25 Apr 2022 18:23:50 +0200 Subject: dt-bindings: arm: fsl: add toradex,colibri-imx6ull Add toradex,colibri-imx6ull for carrier board dts, including aster, iris and iris-v2 device tree, wifi and nonwifi variants for NAND and eMMC modules. Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d1d79889227e..091db1bdf90b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -669,23 +669,32 @@ properties: - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: - - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board + - toradex,colibri-imx6ull-aster # Colibri iMX6ULL Module on Aster Carrier Board + - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board V3 + - toradex,colibri-imx6ull-iris # Colibri iMX6ULL Module on Iris Carrier Board + - toradex,colibri-imx6ull-iris-v2 # Colibri iMX6ULL Module on Iris V2 Carrier Board - const: toradex,colibri-imx6ull # Colibri iMX6ULL Module - - const: fsl,imx6dl + - const: fsl,imx6ull - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module items: - enum: - - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1GB (eMMC) M. on Colibri Evaluation Board - - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module - - const: fsl,imx6dl + - toradex,colibri-imx6ull-emmc-aster # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board + - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3 + - toradex,colibri-imx6ull-emmc-iris # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board + - toradex,colibri-imx6ull-emmc-iris-v2 # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board + - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module + - const: fsl,imx6ull - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules items: - enum: - - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Evaluation Board - - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module - - const: fsl,imx6dl + - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3 + - toradex,colibri-imx6ull-wifi-aster # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board + - toradex,colibri-imx6ull-wifi-iris # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board + - toradex,colibri-imx6ull-wifi-iris-v2 # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board + - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module + - const: fsl,imx6ull - description: Kontron N6411 S Board items: -- cgit v1.2.3 From 5bb0276031b2c768667f6902c8eda8ddefab74d0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 27 Apr 2022 18:15:32 +0200 Subject: dt-bindings: dmaengine: fsl-imx: deprecate '#dma-channels' and '#dma-requests' The generic properties, used in most of the drivers and defined in generic dma-common DT bindings, are 'dma-channels' and 'dma-requests'. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/dma/fsl-imx-dma.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt index 7bd8847d6394..1c9929d53727 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt @@ -13,8 +13,10 @@ Required properties: - #dma-cells : Has to be 1. imx-dma does not support anything else. Optional properties: -- #dma-channels : Number of DMA channels supported. Should be 16. -- #dma-requests : Number of DMA requests supported. +- dma-channels : Number of DMA channels supported. Should be 16. +- #dma-channels : deprecated +- dma-requests : Number of DMA requests supported. +- #dma-requests : deprecated Example: @@ -23,7 +25,7 @@ Example: reg = <0x10001000 0x1000>; interrupts = <32 33>; #dma-cells = <1>; - #dma-channels = <16>; + dma-channels = <16>; }; -- cgit v1.2.3 From e61492e47838f4d99a3ffcc591ba57d1d5d0896f Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 4 May 2022 16:51:44 +0900 Subject: dt-bindings: clock: add Exynos Auto v9 SoC CMU bindings Add dt-schema for Exynos Auto v9 SoC clock controller. Signed-off-by: Chanho Park Reviewed-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220504075154.58819-3-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/samsung,exynosautov9-clock.yaml | 219 +++++++++++++++++++++ 1 file changed, 219 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml new file mode 100644 index 000000000000..eafc715d2d02 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Auto v9 SoC clock controller + +maintainers: + - Chanho Park + - Chanwoo Choi + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + Exynos Auto v9 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. Root clocks in that clock tree are + two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz). + The external OSCCLK must be defined as fixed-rate clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/samsung,exynosautov9.h' header. + +properties: + compatible: + enum: + - samsung,exynosautov9-cmu-top + - samsung,exynosautov9-cmu-busmc + - samsung,exynosautov9-cmu-core + - samsung,exynosautov9-cmu-fsys2 + - samsung,exynosautov9-cmu-peric0 + - samsung,exynosautov9-cmu-peric1 + - samsung,exynosautov9-cmu-peris + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-busmc + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_BUSMC bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_busmc_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CORE bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_core_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-fsys2 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS2 bus clock (from CMU_TOP) + - description: UFS clock (from CMU_TOP) + - description: Ethernet clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_fsys2_bus + - const: dout_fsys2_clkcmu_ufs_embd + - const: dout_fsys2_clkcmu_ethernet + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIC0 bus clock (from CMU_TOP) + - description: PERIC0 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_peric0_bus + - const: dout_clkcmu_peric0_ip + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-peric1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIC1 bus clock (from CMU_TOP) + - description: PERIC1 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_peric1_bus + - const: dout_clkcmu_peric1_ip + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIS bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_peris_bus + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS2 + - | + #include + + cmu_fsys2: clock-controller@17c00000 { + compatible = "samsung,exynosautov9-cmu-fsys2"; + reg = <0x17c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_FSYS2_BUS>, + <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>, + <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>; + clock-names = "oscclk", + "dout_clkcmu_fsys2_bus", + "dout_fsys2_clkcmu_ufs_embd", + "dout_fsys2_clkcmu_ethernet"; + }; + +... -- cgit v1.2.3 From 5652dc5cd96765d236ada1006db1d467c523c3b4 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 09:25:08 +0100 Subject: dt-bindings: memory: renesas,rpc-if: Document RZ/G2UL SoC Document RZ/G2UL RPC-IF bindings. RZ/G2UL RPC-IF is identical to one found on the RZ/G2L SoC. No driver changes are required as generic compatible string "renesas,rzg2l-rpc-if" will be used as a fallback. Signed-off-by: Biju Das Acked-by: Rob Herring Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220501082508.25511-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml index 9a6dbf54b540..6744d17f1efd 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml @@ -39,6 +39,7 @@ properties: - items: - enum: + - renesas,r9a07g043-rpc-if # RZ/G2UL - renesas,r9a07g044-rpc-if # RZ/G2{L,LC} - renesas,r9a07g054-rpc-if # RZ/V2L - const: renesas,rzg2l-rpc-if -- cgit v1.2.3 From 033a26dcbe10476c5203f590dce0537fac802d03 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 May 2022 14:40:58 +0200 Subject: dt-bindings: soc: renesas: Move renesas,rzg2l-sysc from arm to soc The Renesas RZ/{G2L,V2L} System Controller (SYSC) DT binding is not really a power-related DT binding, hence it does not belong under Documentation/devicetree/bindings/power/. Move it to Documentation/devicetree/bindings/soc/renesas/. Signed-off-by: Geert Uytterhoeven Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/a47015888f99476a5206a556dce93503494d9a73.1651495078.git.geert+renesas@glider.be --- .../bindings/power/renesas,rzg2l-sysc.yaml | 65 ---------------------- .../bindings/soc/renesas/renesas,rzg2l-sysc.yaml | 65 ++++++++++++++++++++++ 2 files changed, 65 insertions(+), 65 deletions(-) delete mode 100644 Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml deleted file mode 100644 index c31eeb66319f..000000000000 --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml +++ /dev/null @@ -1,65 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" - -title: Renesas RZ/{G2L,V2L} System Controller (SYSC) - -maintainers: - - Geert Uytterhoeven - -description: - The RZ/{G2L,V2L}-alike System Controller (SYSC) performs system control of - the LSI and supports following functions, - - External terminal state capture function - - 34-bit address space access function - - Low power consumption control - - WDT stop control - -properties: - compatible: - enum: - - renesas,r9a07g043-sysc # RZ/G2UL - - renesas,r9a07g044-sysc # RZ/G2{L,LC} - - renesas,r9a07g054-sysc # RZ/V2L - - reg: - maxItems: 1 - - interrupts: - items: - - description: CA55/CM33 Sleep/Software Standby Mode request interrupt - - description: CA55 Software Standby Mode release request interrupt - - description: CM33 Software Standby Mode release request interrupt - - description: CA55 ACE Asynchronous Bridge Master/Slave interface deny request interrupt - - interrupt-names: - items: - - const: lpm_int - - const: ca55stbydone_int - - const: cm33stbyr_int - - const: ca55_deny - -required: - - compatible - - reg - - interrupts - - interrupt-names - -additionalProperties: false - -examples: - - | - #include - - sysc: system-controller@11020000 { - compatible = "renesas,r9a07g044-sysc"; - reg = <0x11020000 0x10000>; - interrupts = , - , - , - ; - interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", - "ca55_deny"; - }; diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml new file mode 100644 index 000000000000..ce2875c89329 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/renesas/renesas,rzg2l-sysc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas RZ/{G2L,V2L} System Controller (SYSC) + +maintainers: + - Geert Uytterhoeven + +description: + The RZ/{G2L,V2L}-alike System Controller (SYSC) performs system control of + the LSI and supports following functions, + - External terminal state capture function + - 34-bit address space access function + - Low power consumption control + - WDT stop control + +properties: + compatible: + enum: + - renesas,r9a07g043-sysc # RZ/G2UL + - renesas,r9a07g044-sysc # RZ/G2{L,LC} + - renesas,r9a07g054-sysc # RZ/V2L + + reg: + maxItems: 1 + + interrupts: + items: + - description: CA55/CM33 Sleep/Software Standby Mode request interrupt + - description: CA55 Software Standby Mode release request interrupt + - description: CM33 Software Standby Mode release request interrupt + - description: CA55 ACE Asynchronous Bridge Master/Slave interface deny request interrupt + + interrupt-names: + items: + - const: lpm_int + - const: ca55stbydone_int + - const: cm33stbyr_int + - const: ca55_deny + +required: + - compatible + - reg + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g044-sysc"; + reg = <0x11020000 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", + "ca55_deny"; + }; -- cgit v1.2.3 From 5c39d087c98db6bc453e6f7911e7a9713f219a77 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 5 May 2022 08:19:03 -0300 Subject: dt-bindings: vendor-prefixes: Add prefix for Storopack Add a vendor prefix entry for Storopack (https://www.storopack.com). Signed-off-by: Fabio Estevam Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 01430973ecec..0206bb14c1df 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1193,6 +1193,8 @@ patternProperties: description: StorLink Semiconductors, Inc. "^storm,.*": description: Storm Semiconductor, Inc. + "^storopack,.*": + description: Storopack "^summit,.*": description: Summit microelectronics "^sunchip,.*": -- cgit v1.2.3 From 0efdbec205bfd16a537c29eecd535afce195b4d2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 5 May 2022 08:19:04 -0300 Subject: dt-bindings: arm: fsl: Add Storopack i.MX7D SMEGW01 board Add DT compatible string for Storopack i.MX7D SMEGW01 board. Signed-off-by: Fabio Estevam Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 091db1bdf90b..0bf43346d232 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -757,6 +757,7 @@ properties: - kam,imx7d-flex-concentrator-mfg # Kamstrup OMNIA Flex Concentrator in manufacturing mode - novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board - remarkable,imx7d-remarkable2 # i.MX7D ReMarkable 2 E-Ink Tablet + - storopack,imx7d-smegw01 # Storopack i.MX7D SMEGW01 - technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf - technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit - technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph -- cgit v1.2.3 From 75f9d540862a392395f41a5aa437a7fc2d059c23 Mon Sep 17 00:00:00 2001 From: Philip Oberfichtner Date: Fri, 6 May 2022 07:59:47 +0200 Subject: dt-bindings: arm: Add bosch acc board Add device tree binding for the Bosch ACC board, based on i.MX6 Dual. Signed-off-by: Philip Oberfichtner Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0bf43346d232..ef524378d449 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -192,6 +192,7 @@ properties: items: - enum: - auvidea,h100 # Auvidea H100 + - bosch,imx6q-acc # Bosch ACC i.MX6 Dual - boundary,imx6q-nitrogen6_max - boundary,imx6q-nitrogen6_som2 - boundary,imx6q-nitrogen6x -- cgit v1.2.3 From 045d0c3db9119ebb36d50e0190bed4ea6374f6cf Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Wed, 11 May 2022 11:25:59 +0200 Subject: dt-bindings: clock: stm32mp1: adapt example for "st,stm32mp1-rcc-secure" For "st,stm32mp1-rcc-secure" schema, clocks and clock-names entries are now required properties. Signed-off-by: Alexandre Torgue Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220511092559.4952-1-alexandre.torgue@foss.st.com' Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index bb0e0b92e907..45b94124366c 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -106,10 +106,17 @@ additionalProperties: false examples: - | + #include rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc-secure", "syscon"; reg = <0x50000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; }; ... -- cgit v1.2.3 From a37bc730a572b863253c0244a798127317bd79e0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 12 Apr 2022 12:50:13 +0200 Subject: ARM: dts: at91: use generic node name for dataflash The node names should be generic, so use "flash" for dataflash nodes and for cfi-flash. Suggested-by: Tudor Ambarus Signed-off-by: Krzysztof Kozlowski Reviewed-by: Tudor Ambarus Acked-by: Nicolas Ferre Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220412105013.249793-1-krzysztof.kozlowski@linaro.org Signed-off-by: Nicolas Ferre --- Documentation/devicetree/bindings/mfd/atmel-flexcom.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt index 692300117c64..9d837535637b 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt @@ -54,7 +54,7 @@ flexcom@f8034000 { clock-names = "spi_clk"; atmel,fifo-size = <32>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at25f512b"; reg = <0>; spi-max-frequency = <20000000>; -- cgit v1.2.3