From ce39d255dea5ff7d618ef44f61776545481793a1 Mon Sep 17 00:00:00 2001 From: SungMin Park Date: Wed, 29 Oct 2025 18:37:31 +0530 Subject: dt-bindings: samsung: exynos-pmu: Add compatible for ARTPEC-9 SoC Add Axis ARTPEC-9 pmu compatible to the bindings documentation. It reuses the older samsung,exynos7-pmu design. Signed-off-by: SungMin Park Signed-off-by: Ravi Patel Acked-by: Conor Dooley Link: https://patch.msgid.link/20251029130731.51305-5-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 6de47489ee42..0d52b0e9bc17 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -52,6 +52,7 @@ properties: - const: syscon - items: - enum: + - axis,artpec9-pmu - samsung,exynos2200-pmu - samsung,exynos7870-pmu - samsung,exynos7885-pmu -- cgit v1.2.3 From bd0b8028ce5fbc7d9f5c2751c20661b0d8114e60 Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Thu, 11 Dec 2025 14:32:35 +0530 Subject: dt-bindings: cache: qcom,llcc: Document Glymur LLCC block Document the Last Level Cache Controller on Glymur SoC Glymur LLCC has 12 base register regions and an additional AND, OR broadcast region, total 14 register regions Increase maxItems for reg and reg-names to allow 14 entries for Glymur Reviewed-by: Krzysztof Kozlowski Signed-off-by: Pankaj Patil Link: https://lore.kernel.org/r/20251211-glymur_llcc_enablement-v3-1-43457b354b0d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/cache/qcom,llcc.yaml | 47 +++++++++++++++++++++- 1 file changed, 45 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index a620a2ff5c56..4e99c405aea3 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -20,6 +20,7 @@ description: | properties: compatible: enum: + - qcom,glymur-llcc - qcom,ipq5424-llcc - qcom,kaanapali-llcc - qcom,qcs615-llcc @@ -46,11 +47,11 @@ properties: reg: minItems: 1 - maxItems: 10 + maxItems: 14 reg-names: minItems: 1 - maxItems: 10 + maxItems: 14 interrupts: maxItems: 1 @@ -84,6 +85,48 @@ allOf: items: - const: llcc0_base + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC8 base register region + - description: LLCC9 base register region + - description: LLCC10 base register region + - description: LLCC11 base register region + - description: LLCC broadcast base register region + - description: LLCC broadcast AND register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc7_base + - const: llcc8_base + - const: llcc9_base + - const: llcc10_base + - const: llcc11_base + - const: llcc_broadcast_base + - const: llcc_broadcast_and_base + - if: properties: compatible: -- cgit v1.2.3 From 71e47245f89502dafb5d944a571ccb5144a52645 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 15 Dec 2025 15:16:33 +0100 Subject: tee: Adapt documentation to cover recent additions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The previous commits introduced some helpers to reduce boilerplate and bus specific callbacks for probe and remove. Adapt the reference example to make use of these. Reviewed-by: Sumit Garg Signed-off-by: Uwe Kleine-König Signed-off-by: Jens Wiklander --- Documentation/driver-api/tee.rst | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) (limited to 'Documentation') diff --git a/Documentation/driver-api/tee.rst b/Documentation/driver-api/tee.rst index 5eaeb8103988..4d58ac0712c1 100644 --- a/Documentation/driver-api/tee.rst +++ b/Documentation/driver-api/tee.rst @@ -43,24 +43,12 @@ snippet would look like:: MODULE_DEVICE_TABLE(tee, client_id_table); static struct tee_client_driver client_driver = { + .probe = client_probe, + .remove = client_remove, .id_table = client_id_table, .driver = { .name = DRIVER_NAME, - .bus = &tee_bus_type, - .probe = client_probe, - .remove = client_remove, }, }; - static int __init client_init(void) - { - return driver_register(&client_driver.driver); - } - - static void __exit client_exit(void) - { - driver_unregister(&client_driver.driver); - } - - module_init(client_init); - module_exit(client_exit); + module_tee_client_driver(client_driver); -- cgit v1.2.3 From 5422fad3e1cc2293cb3549f8ec02013ea50a9c80 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Tue, 21 Oct 2025 23:00:26 -0700 Subject: dt-bindings: interrupt-controller: qcom,pdc: Document Kaanapali Power Domain Controller Add a compatible for the Power Domain Controller on Kaanapali platforms. Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251021-knp-pdc-v2-1-a38767f5bb8e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index 38d0c2d57dd6..b26246de3186 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -27,6 +27,7 @@ properties: items: - enum: - qcom,glymur-pdc + - qcom,kaanapali-pdc - qcom,qcs615-pdc - qcom,qcs8300-pdc - qcom,qdu1000-pdc -- cgit v1.2.3 From 6c4bbcdad042b876c8e480ed75121756b1acfde7 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Sun, 23 Nov 2025 23:31:54 -0800 Subject: dt-bindings: sram: Document qcom,kaanapali-imem and its child node On Qualcomm Kaanapali platform, IMEM is a block of SRAM shared across multiple IP blocks which can falk back to "mmio-sram". Documnent it and its child node "qcom,pil-reloc-info" which is used for collecting remoteproc ramdumps. Signed-off-by: Jingyi Wang Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251123-knp-soc-binding-v4-1-42b349a66c59@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/sram/sram.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 7c1337e159f2..c451140962c8 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -34,6 +34,7 @@ properties: - nvidia,tegra186-sysram - nvidia,tegra194-sysram - nvidia,tegra234-sysram + - qcom,kaanapali-imem - qcom,rpm-msg-ram - rockchip,rk3288-pmu-sram @@ -89,6 +90,7 @@ patternProperties: - arm,juno-scp-shmem - arm,scmi-shmem - arm,scp-shmem + - qcom,pil-reloc-info - renesas,smp-sram - rockchip,rk3066-smp-sram - samsung,exynos4210-sysram -- cgit v1.2.3 From dffaa1beea9e7a0d902fc4e25e137afcf1297267 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= Date: Tue, 18 Nov 2025 16:07:57 +0100 Subject: dt-bindings: memory: factorise LPDDR props into SDRAM props MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LPDDR and DDR bindings are SDRAM types and are likely to share the same properties (at least for density, io-width and reg). To avoid bindings duplication, factorise the properties. The compatible description has been updated because the MR (Mode registers) used to get manufacturer ID and revision ID are not present in case of DDR. Those information should be in a SPD (Serial Presence Detect) EEPROM in case of DIMM module or are known in case of soldered memory chips as they are in the datasheet of the memory chips. Signed-off-by: Clément Le Goffic Reviewed-by: Krzysztof Kozlowski Signed-off-by: Clément Le Goffic Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-1-a033ac5144da@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../memory-controllers/ddr/jedec,lpddr-props.yaml | 74 ----------------- .../memory-controllers/ddr/jedec,lpddr2.yaml | 2 +- .../memory-controllers/ddr/jedec,lpddr3.yaml | 2 +- .../memory-controllers/ddr/jedec,lpddr4.yaml | 2 +- .../memory-controllers/ddr/jedec,lpddr5.yaml | 2 +- .../memory-controllers/ddr/jedec,sdram-props.yaml | 94 ++++++++++++++++++++++ 6 files changed, 98 insertions(+), 78 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-props.yaml create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-props.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-props.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-props.yaml deleted file mode 100644 index 30267ce70124..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-props.yaml +++ /dev/null @@ -1,74 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Common properties for LPDDR types - -description: - Different LPDDR types generally use the same properties and only differ in the - range of legal values for each. This file defines the common parts that can be - reused for each type. Nodes using this schema should generally be nested under - an LPDDR channel node. - -maintainers: - - Krzysztof Kozlowski - -properties: - compatible: - description: - Compatible strings can be either explicit vendor names and part numbers - (e.g. elpida,ECB240ABACN), or generated strings of the form - lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID - (from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are - formatted in lower case hexadecimal representation with leading zeroes. - The latter form can be useful when LPDDR nodes are created at runtime by - boot firmware that doesn't have access to static part number information. - - reg: - description: - The rank number of this LPDDR rank when used as a subnode to an LPDDR - channel. - minimum: 0 - maximum: 3 - - revision-id: - $ref: /schemas/types.yaml#/definitions/uint32-array - description: - Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. ). - maxItems: 2 - items: - minimum: 0 - maximum: 255 - - density: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - Density in megabits of SDRAM chip. Decoded from Mode Register 8. - enum: - - 64 - - 128 - - 256 - - 512 - - 1024 - - 2048 - - 3072 - - 4096 - - 6144 - - 8192 - - 12288 - - 16384 - - 24576 - - 32768 - - io-width: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - IO bus width in bits of SDRAM chip. Decoded from Mode Register 8. - enum: - - 8 - - 16 - - 32 - -additionalProperties: true diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml index a237bc259273..704bbc562528 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,sdram-props.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml index e328a1195ba6..0d28df3d2bfa 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,sdram-props.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4.yaml index a078892fecee..65aa07861453 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4.yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,sdram-props.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5.yaml index e441dac5f154..cf5d5a8e94b3 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5.yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,sdram-props.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-props.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-props.yaml new file mode 100644 index 000000000000..fedd66eeb9d5 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-props.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common properties for SDRAM types + +description: + Different SDRAM types generally use the same properties and only differ in the + range of legal values for each. This file defines the common parts that can be + reused for each type. Nodes using this schema should generally be nested under + a SDRAM channel node. + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + description: | + Compatible strings can be either explicit vendor names and part numbers + (e.g. elpida,ECB240ABACN), or generated strings of the form + lpddrX-YY,ZZZZ or ddrX-YYYY,AAAA...-ZZ where X, Y, and Z are lowercase + hexadecimal with leading zeroes, and A is lowercase ASCII. + For LPDDR and DDR SDRAM, X is the SDRAM version (2, 3, 4, etc.). + For LPDDR SDRAM: + - YY is the manufacturer ID (from MR5), 1 byte + - ZZZZ is the revision ID (from MR6 and MR7), 2 bytes + For DDR4 SDRAM with SPD, according to JEDEC SPD4.1.2.L-6: + - YYYY is the manufacturer ID, 2 bytes, from bytes 320 and 321 + - AAAA... is the part number, 20 bytes (20 chars) from bytes 329 to 348 + without trailing spaces + - ZZ is the revision ID, 1 byte, from byte 349 + The former form is useful when the SDRAM vendor and part number are + known, for example, when memory is soldered on the board. The latter + form is useful when SDRAM nodes are created at runtime by boot firmware + that doesn't have access to static part number information. + + reg: + description: + The rank number of this memory rank when used as a subnode to an memory + channel. + minimum: 0 + maximum: 3 + + revision-id: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + SDRAM revision ID: + - LPDDR SDRAM, decoded from Mode Registers 6 and 7, always 2 bytes. + - DDR4 SDRAM, decoded from the SPD from byte 349 according to + JEDEC SPD4.1.2.L-6, always 1 byte. + One byte per uint32 cell (e.g., ). + maxItems: 2 + items: + minimum: 0 + maximum: 255 + + density: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Density of the SDRAM chip in megabits: + - LPDDR SDRAM, decoded from Mode Register 8. + - DDR4 SDRAM, decoded from the SPD from bits 3-0 of byte 4 according to + JEDEC SPD4.1.2.L-6. + enum: + - 64 + - 128 + - 256 + - 512 + - 1024 + - 2048 + - 3072 + - 4096 + - 6144 + - 8192 + - 12288 + - 16384 + - 24576 + - 32768 + + io-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + I/O bus width in bits of the SDRAM chip: + - LPDDR SDRAM, decoded from Mode Register 8. + - DDR4 SDRAM, decoded from the SPD from bits 2-0 of byte 12 according to + JEDEC SPD4.1.2.L-6. + enum: + - 8 + - 16 + - 32 + +additionalProperties: true -- cgit v1.2.3 From b5c1a217552c3513977a9f1138b05de0bada8a52 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= Date: Tue, 18 Nov 2025 16:07:58 +0100 Subject: dt-bindings: memory: introduce DDR4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce JEDEC compliant DDR bindings, that use new memory-props binding. The DDR4 compatible can be made of explicit vendor names and part numbers or be of the form "ddrX-YYYY,AAAA...-ZZ" when associated with an SPD, where (according to JEDEC SPD4.1.2.L-6): - YYYY is the manufacturer ID - AAAA... is the part number - ZZ is the revision ID The former form is useful when the SDRAM vendor and part number are known, for example, when memory is soldered on the board. The latter form is useful when SDRAM nodes are created at runtime by boot firmware that doesn't have access to static part number information. Signed-off-by: Clément Le Goffic Signed-off-by: Clément Le Goffic Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-2-a033ac5144da@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../memory-controllers/ddr/jedec,ddr4.yaml | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr4.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr4.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr4.yaml new file mode 100644 index 000000000000..928961c74026 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr4.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,ddr4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DDR4 SDRAM compliant to JEDEC JESD79-4D + +maintainers: + - Krzysztof Kozlowski + +allOf: + - $ref: jedec,sdram-props.yaml# + +properties: + compatible: + items: + - pattern: "^ddr4-[0-9a-f]{4},[a-z]{1,20}-[0-9a-f]{2}$" + - const: jedec,ddr4 + +required: + - compatible + - density + - io-width + +unevaluatedProperties: false + +examples: + - | + ddr { + compatible = "ddr4-00ff,azaz-ff", "jedec,ddr4"; + density = <8192>; + io-width = <8>; + }; -- cgit v1.2.3 From 6ab3581ab19fa348b93c85a793e45cd8a80912a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= Date: Tue, 18 Nov 2025 16:07:59 +0100 Subject: dt-bindings: memory: factorise LPDDR channel binding into SDRAM channel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LPDDR, DDR and so SDRAM channels exist and share the same properties, they have a compatible, ranks, and an io-width. Signed-off-by: Clément Le Goffic Reviewed-by: Rob Herring (Arm) Signed-off-by: Clément Le Goffic Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-3-a033ac5144da@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../ddr/jedec,lpddr-channel.yaml | 146 -------------------- .../ddr/jedec,sdram-channel.yaml | 147 +++++++++++++++++++++ 2 files changed, 147 insertions(+), 146 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml deleted file mode 100644 index 34b5bd153f63..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml +++ /dev/null @@ -1,146 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: LPDDR channel with chip/rank topology description - -description: - An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS, - CK, etc.) that connect one or more LPDDR chips to a host system. The main - purpose of this node is to overall LPDDR topology of the system, including the - amount of individual LPDDR chips and the ranks per chip. - -maintainers: - - Julius Werner - -properties: - compatible: - enum: - - jedec,lpddr2-channel - - jedec,lpddr3-channel - - jedec,lpddr4-channel - - jedec,lpddr5-channel - - io-width: - description: - The number of DQ pins in the channel. If this number is different - from (a multiple of) the io-width of the LPDDR chip, that means that - multiple instances of that type of chip are wired in parallel on this - channel (with the channel's DQ pins split up between the different - chips, and the CA, CS, etc. pins of the different chips all shorted - together). This means that the total physical memory controlled by a - channel is equal to the sum of the densities of each rank on the - connected LPDDR chip, times the io-width of the channel divided by - the io-width of the LPDDR chip. - enum: - - 8 - - 16 - - 32 - - 64 - - 128 - - "#address-cells": - const: 1 - - "#size-cells": - const: 0 - -patternProperties: - "^rank@[0-9]+$": - type: object - description: - Each physical LPDDR chip may have one or more ranks. Ranks are - internal but fully independent sub-units of the chip. Each LPDDR bus - transaction on the channel targets exactly one rank, based on the - state of the CS pins. Different ranks may have different densities and - timing requirements. - required: - - reg - -allOf: - - if: - properties: - compatible: - contains: - const: jedec,lpddr2-channel - then: - patternProperties: - "^rank@[0-9]+$": - $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml# - - if: - properties: - compatible: - contains: - const: jedec,lpddr3-channel - then: - patternProperties: - "^rank@[0-9]+$": - $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml# - - if: - properties: - compatible: - contains: - const: jedec,lpddr4-channel - then: - patternProperties: - "^rank@[0-9]+$": - $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml# - - if: - properties: - compatible: - contains: - const: jedec,lpddr5-channel - then: - patternProperties: - "^rank@[0-9]+$": - $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml# - -required: - - compatible - - io-width - - "#address-cells" - - "#size-cells" - -additionalProperties: false - -examples: - - | - lpddr-channel0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "jedec,lpddr3-channel"; - io-width = <32>; - - rank@0 { - compatible = "lpddr3-ff,0100", "jedec,lpddr3"; - reg = <0>; - density = <8192>; - io-width = <16>; - revision-id = <1 0>; - }; - }; - - lpddr-channel1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "jedec,lpddr4-channel"; - io-width = <32>; - - rank@0 { - compatible = "lpddr4-05,0301", "jedec,lpddr4"; - reg = <0>; - density = <4096>; - io-width = <32>; - revision-id = <3 1>; - }; - - rank@1 { - compatible = "lpddr4-05,0301", "jedec,lpddr4"; - reg = <1>; - density = <2048>; - io-width = <32>; - revision-id = <3 1>; - }; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml new file mode 100644 index 000000000000..9892da520fe4 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-channel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SDRAM channel with chip/rank topology description + +description: + A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a completely + independent set of pins (DQ, CA, CS, CK, etc.) that connect one or more memory + chips to a host system. The main purpose of this node is to overall memory + topology of the system, including the amount of individual memory chips and + the ranks per chip. + +maintainers: + - Julius Werner + +properties: + compatible: + enum: + - jedec,lpddr2-channel + - jedec,lpddr3-channel + - jedec,lpddr4-channel + - jedec,lpddr5-channel + + io-width: + description: + The number of DQ pins in the channel. If this number is different + from (a multiple of) the io-width of the SDRAM chip, that means that + multiple instances of that type of chip are wired in parallel on this + channel (with the channel's DQ pins split up between the different + chips, and the CA, CS, etc. pins of the different chips all shorted + together). This means that the total physical memory controlled by a + channel is equal to the sum of the densities of each rank on the + connected SDRAM chip, times the io-width of the channel divided by + the io-width of the SDRAM chip. + enum: + - 8 + - 16 + - 32 + - 64 + - 128 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^rank@[0-9]+$": + type: object + description: + Each physical SDRAM chip may have one or more ranks. Ranks are + internal but fully independent sub-units of the chip. Each SDRAM bus + transaction on the channel targets exactly one rank, based on the + state of the CS pins. Different ranks may have different densities and + timing requirements. + required: + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: jedec,lpddr2-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml# + - if: + properties: + compatible: + contains: + const: jedec,lpddr3-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml# + - if: + properties: + compatible: + contains: + const: jedec,lpddr4-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml# + - if: + properties: + compatible: + contains: + const: jedec,lpddr5-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml# + +required: + - compatible + - io-width + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + lpddr-channel0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,lpddr3-channel"; + io-width = <32>; + + rank@0 { + compatible = "lpddr3-ff,0100", "jedec,lpddr3"; + reg = <0>; + density = <8192>; + io-width = <16>; + revision-id = <1 0>; + }; + }; + + lpddr-channel1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,lpddr4-channel"; + io-width = <32>; + + rank@0 { + compatible = "lpddr4-05,0301", "jedec,lpddr4"; + reg = <0>; + density = <4096>; + io-width = <32>; + revision-id = <3 1>; + }; + + rank@1 { + compatible = "lpddr4-05,0301", "jedec,lpddr4"; + reg = <1>; + density = <2048>; + io-width = <32>; + revision-id = <3 1>; + }; + }; -- cgit v1.2.3 From 36ecc8346747b600892e3040e1d0ecb1e939c6e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= Date: Tue, 18 Nov 2025 16:08:00 +0100 Subject: dt-bindings: memory: add DDR4 channel compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add in the memory channel binding the DDR4 compatible to support DDR4 memory channel. Signed-off-by: Clément Le Goffic Reviewed-by: Rob Herring (Arm) Signed-off-by: Clément Le Goffic Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-4-a033ac5144da@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/ddr/jedec,sdram-channel.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml index 9892da520fe4..866af40b654d 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml @@ -19,6 +19,7 @@ maintainers: properties: compatible: enum: + - jedec,ddr4-channel - jedec,lpddr2-channel - jedec,lpddr3-channel - jedec,lpddr4-channel @@ -61,6 +62,15 @@ patternProperties: - reg allOf: + - if: + properties: + compatible: + contains: + const: jedec,ddr4-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,ddr4.yaml# - if: properties: compatible: -- cgit v1.2.3 From 9805f2cfc883018f7bf84c84e3af3786c37dac7b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= Date: Tue, 18 Nov 2025 16:08:01 +0100 Subject: dt-bindings: memory: SDRAM channel: standardise node name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a pattern for sdram channel node name. Signed-off-by: Clément Le Goffic Reviewed-by: Rob Herring (Arm) Signed-off-by: Clément Le Goffic Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-5-a033ac5144da@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/ddr/jedec,sdram-channel.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml index 866af40b654d..5cdd8ef45100 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml @@ -17,6 +17,9 @@ maintainers: - Julius Werner properties: + $nodename: + pattern: "sdram-channel-[0-9]+$" + compatible: enum: - jedec,ddr4-channel @@ -118,7 +121,7 @@ additionalProperties: false examples: - | - lpddr-channel0 { + sdram-channel-0 { #address-cells = <1>; #size-cells = <0>; compatible = "jedec,lpddr3-channel"; @@ -133,7 +136,7 @@ examples: }; }; - lpddr-channel1 { + sdram-channel-1 { #address-cells = <1>; #size-cells = <0>; compatible = "jedec,lpddr4-channel"; -- cgit v1.2.3 From 12da6f08a07ddaddd336af878350d30449d23a54 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Mon, 22 Dec 2025 16:30:05 +0000 Subject: dt-bindings: nvmem: add google,gs101-otp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add binding for the OTP controller found on Google GS101. Reviewed-by: André Draszik Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tudor Ambarus Link: https://patch.msgid.link/20251222-gs101-chipid-v4-1-aa8e20ce7bb3@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/nvmem/google,gs101-otp.yaml | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/google,gs101-otp.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/nvmem/google,gs101-otp.yaml b/Documentation/devicetree/bindings/nvmem/google,gs101-otp.yaml new file mode 100644 index 000000000000..99e322c72f9e --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/google,gs101-otp.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/google,gs101-otp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google GS101 OTP Controller + +maintainers: + - Tudor Ambarus + +description: | + OTP controller drives a NVMEM memory where system or user specific data + can be stored. The OTP controller register space is of interest as well + because it contains dedicated registers where it stores the Product ID + and the Chip ID (apart other things like TMU or ASV info). + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + items: + - const: google,gs101-otp + + clocks: + maxItems: 1 + + clock-names: + const: pclk + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + + efuse@10000000 { + compatible = "google,gs101-otp"; + reg = <0x10000000 0xf084>; + clocks = <&cmu_misc CLK_GOUT_MISC_OTP_CON_TOP_PCLK>; + clock-names = "pclk"; + interrupts = ; + }; -- cgit v1.2.3 From 5cd2a743ce384a5a4a1b5b09d4983df2592fbe1c Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Mon, 5 Jan 2026 18:30:50 +0530 Subject: dt-bindings: cache: qcom,llcc: Remove duplicate llcc7_base for Glymur Drop redundant llcc7_base entry from Glymur LLCC reg-items Fixes: bd0b8028ce5f ("dt-bindings: cache: qcom,llcc: Document Glymur LLCC block") Signed-off-by: Pankaj Patil Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260105130050.1062903-1-pankaj.patil@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 4e99c405aea3..6671e461e34a 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -119,7 +119,6 @@ allOf: - const: llcc5_base - const: llcc6_base - const: llcc7_base - - const: llcc7_base - const: llcc8_base - const: llcc9_base - const: llcc10_base -- cgit v1.2.3 From f50da52e5b2ed73913cc6d0db7c81cd33ced3ae7 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:26 +0900 Subject: dt-bindings: crypto: qcom,prng: document Milos Document Milos SoC compatible for the True Random Number Generator. Acked-by: Rob Herring (Arm) Reviewed-by: Bjorn Andersson Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-2-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml index 597441d94cf1..a9674e29144e 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml @@ -21,6 +21,7 @@ properties: - qcom,ipq5424-trng - qcom,ipq9574-trng - qcom,kaanapali-trng + - qcom,milos-trng - qcom,qcs615-trng - qcom,qcs8300-trng - qcom,sa8255p-trng -- cgit v1.2.3 From 42f2799124a4d0081b0c8c50980e37769e8d6880 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:27 +0900 Subject: dt-bindings: qcom,pdc: document the Milos Power Domain Controller Document the Power Domain Controller on the Milos SoC. Acked-by: Rob Herring (Arm) Reviewed-by: Bjorn Andersson Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-3-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index b26246de3186..f9321366cae4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -28,6 +28,7 @@ properties: - enum: - qcom,glymur-pdc - qcom,kaanapali-pdc + - qcom,milos-pdc - qcom,qcs615-pdc - qcom,qcs8300-pdc - qcom,qdu1000-pdc -- cgit v1.2.3 From 4acd805157102eef1b98794450d2e599c7497542 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 15:28:57 -0600 Subject: dt-bindings: soc: samsung: exynos-pmu: Drop unnecessary select schema The "select" schema is not necessary because "syscon" compatible is already excluded from the default select logic. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260105212858.3454174-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/soc/samsung/exynos-pmu.yaml | 22 ---------------------- 1 file changed, 22 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 0d52b0e9bc17..a6bb3093b10a 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -9,28 +9,6 @@ title: Samsung Exynos SoC series Power Management Unit (PMU) maintainers: - Krzysztof Kozlowski -# Custom select to avoid matching all nodes with 'syscon' -select: - properties: - compatible: - contains: - enum: - - google,gs101-pmu - - samsung,exynos3250-pmu - - samsung,exynos4210-pmu - - samsung,exynos4212-pmu - - samsung,exynos4412-pmu - - samsung,exynos5250-pmu - - samsung,exynos5260-pmu - - samsung,exynos5410-pmu - - samsung,exynos5420-pmu - - samsung,exynos5433-pmu - - samsung,exynos7-pmu - - samsung,exynos850-pmu - - samsung-s5pv210-pmu - required: - - compatible - properties: compatible: oneOf: -- cgit v1.2.3 From 831ee17036e259da23a6313e28a3cbdda221a88c Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Mon, 24 Nov 2025 12:06:51 +0100 Subject: dt-bindings: soc: mediatek: dvfsrc: Document clock The DVFSRC hardware has a clock on all platforms. Instead or proliferating the culture of omitting clock descriptions in the clock controller drivers or marking them critical instead of declaring these types of relationships, add this one to the binding. Any device that wishes to use this binding should figure out their incomplete or incorrect clock situation first before piling more features on top. Acked-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml index 4c96d4917967..27cce748e0ca 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml @@ -34,6 +34,10 @@ properties: maxItems: 1 description: DVFSRC common register address and length. + clocks: + items: + - description: Clock that drives the DVFSRC MCU + regulators: type: object $ref: /schemas/regulator/mediatek,mt6873-dvfsrc-regulator.yaml# @@ -50,6 +54,7 @@ additionalProperties: false examples: - | + #include soc { #address-cells = <2>; #size-cells = <2>; @@ -57,6 +62,7 @@ examples: system-controller@10012000 { compatible = "mediatek,mt8195-dvfsrc"; reg = <0 0x10012000 0 0x1000>; + clocks = <&topckgen CLK_TOP_DVFSRC>; regulators { compatible = "mediatek,mt8195-dvfsrc-regulator"; -- cgit v1.2.3 From 0d069bb381839ba252ecca4031f7eb6f2fc72ab4 Mon Sep 17 00:00:00 2001 From: "Christophe Leroy (CS GROUP)" Date: Wed, 7 Jan 2026 17:59:10 +0100 Subject: dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it so that those IRQs can then be linked to the related GPIOs. Acked-by: Conor Dooley Link: https://lore.kernel.org/r/7708243d6cca21004de8b3da87369c06dbee3848.1767804922.git.chleroy@kernel.org Signed-off-by: Christophe Leroy (CS GROUP) [moved from bindings/soc/fsl/cpm_qe/ to bindings/interrupt-controller/ while applying] --- .../interrupt-controller/fsl,qe-ports-ic.yaml | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,qe-ports-ic.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,qe-ports-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,qe-ports-ic.yaml new file mode 100644 index 000000000000..2b8e7b9c6d7a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,qe-ports-ic.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,qe-ports-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine I/O Ports Interrupt Controller + +maintainers: + - Christophe Leroy (CS GROUP) + +properties: + compatible: + enum: + - fsl,mpc8323-qe-ports-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#address-cells' + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@c00 { + compatible = "fsl,mpc8323-qe-ports-ic"; + reg = <0xc00 0x18>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupts = <74 0x8>; + interrupt-parent = <&ipic>; + }; -- cgit v1.2.3 From ebb0bbef88b3276c01e2d42b71d67c26b4eb938a Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 5 Jan 2026 18:52:49 +0530 Subject: dt-bindings: remoteproc: qcom,pas: Add iommus property On most Qualcomm platforms, the Qualcomm Hypervisor Execution Environment (QHEE) is either used as a standalone hypervisor or co-exists as a module with the Gunyah hypervisor. When QHEE is present, it configures firmware streams for remote processors. If QHEE is not available, the operating system must perform these configurations instead and for that remote processor firmware stream should be presented to the operating system. To support this, add the iommus property as an optional property for PAS-supported devices. Acked-by: Rob Herring (Arm) Reviewed-by: Bryan O'Donoghue Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260105-kvmrprocv10-v10-1-022e96815380@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml index 63a82e7a8bf8..68c17bf18987 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml @@ -44,6 +44,9 @@ properties: - const: stop-ack - const: shutdown-ack + iommus: + maxItems: 1 + power-domains: minItems: 1 maxItems: 3 -- cgit v1.2.3 From 241bdf7253502c56251ef8b25ab9cad5b6547422 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Mon, 12 Jan 2026 23:48:29 +0800 Subject: tee: add revision sysfs attribute Add a generic TEE revision sysfs attribute backed by a new optional get_tee_revision() callback. The revision string is diagnostic-only and must not be used to infer feature support. Signed-off-by: Aristo Chen Reviewed-by: Sumit Garg Signed-off-by: Jens Wiklander --- Documentation/ABI/testing/sysfs-class-tee | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-class-tee b/Documentation/ABI/testing/sysfs-class-tee index c9144d16003e..1a0a3050aaa9 100644 --- a/Documentation/ABI/testing/sysfs-class-tee +++ b/Documentation/ABI/testing/sysfs-class-tee @@ -13,3 +13,13 @@ Description: space if the variable is absent. The primary purpose of this variable is to let systemd know whether tee-supplicant is needed in the early boot with initramfs. + +What: /sys/class/tee/tee{,priv}X/revision +Date: Jan 2026 +KernelVersion: 6.19 +Contact: op-tee@lists.trustedfirmware.org +Description: + Read-only revision string reported by the TEE driver. This is + for diagnostics only and must not be used to infer feature + support. Use TEE_IOC_VERSION for capability and compatibility + checks. -- cgit v1.2.3 From 216e0a5e98e5f0f02a818884e8acf340892cecae Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 20 Jan 2026 19:10:49 +0800 Subject: dt-bindings: soc: spacemit: Add K3 reset support and IDs Update the spacemit,k1-syscon.yaml binding to document K3 SoC reset support. K3 reset devices are registered at runtime as auxiliary devices by the K3 CCU driver. Since K3 reuses the K1 syscon binding, there is no separate YAML binding file for K3 resets. Update #reset-cells description to document where reset IDs are defined. Acked-by: Alex Elder Acked-by: Krzysztof Kozlowski Signed-off-by: Guodong Xu Reviewed-by: Yixun Lan Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] Signed-off-by: Philipp Zabel --- .../devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml index 133a391ee68c..f0c6feb99be3 100644 --- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml @@ -10,7 +10,7 @@ maintainers: - Haylen Chu description: - System controllers found on SpacemiT K1 SoC, which are capable of + System controllers found on SpacemiT K1/K3 SoC, which are capable of clock, reset and power-management functions. properties: @@ -46,6 +46,12 @@ properties: "#reset-cells": const: 1 + description: | + ID of the reset controller line. Valid IDs are defined in corresponding + files: + + For SpacemiT K1, see include/dt-bindings/clock/spacemit,k1-syscon.h + For SpacemiT K3, see include/dt-bindings/reset/spacemit,k3-resets.h required: - compatible -- cgit v1.2.3