From 513006334fb01c7c19b5e005357d94de43a370dd Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Thu, 26 Jun 2014 12:55:30 +0530 Subject: ARM: dts: dra7: add routable-irqs property for gic node There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts/dra7.dtsi') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c29945e07c5a..1cf4ee10acf5 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -45,6 +45,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <192>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- cgit v1.2.3 From a46631c4cda1488a69600efb93f38d84b7a57541 Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Thu, 26 Jun 2014 12:55:31 +0530 Subject: ARM: dts: dra7: add crossbar device binding There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The Peripheral irq requests are connected to only one crossbar input and the output of the crossbar is connected to only one controller's input line. The crossbar device is used to map a peripheral input to a free mpu's interrupt controller line. Here, adding a new crossbar device node and replacing all the peripheral interrupt numbers with its fixed crossbar input lines. Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 138 +++++++++++++++++++++++++------------------- 1 file changed, 80 insertions(+), 58 deletions(-) (limited to 'arch/arm/boot/dts/dra7.dtsi') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1cf4ee10acf5..961be6b8ffbf 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -12,6 +12,9 @@ #include "skeleton.dtsi" +#define MAX_SOURCES 400 +#define DIRECT_IRQ(irq) (MAX_SOURCES + irq) + / { #address-cells = <1>; #size-cells = <1>; @@ -80,8 +83,8 @@ ti,hwmods = "l3_main_1", "l3_main_2"; reg = <0x44000000 0x1000000>, <0x45000000 0x1000>; - interrupts = , - ; + interrupts = , + ; prm: prm@4ae06000 { compatible = "ti,dra7-prm"; @@ -156,10 +159,10 @@ sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; #dma-cells = <1>; #dma-channels = <32>; #dma-requests = <127>; @@ -168,7 +171,7 @@ gpio1: gpio@4ae10000 { compatible = "ti,omap4-gpio"; reg = <0x4ae10000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio1"; gpio-controller; #gpio-cells = <2>; @@ -179,7 +182,7 @@ gpio2: gpio@48055000 { compatible = "ti,omap4-gpio"; reg = <0x48055000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; @@ -190,7 +193,7 @@ gpio3: gpio@48057000 { compatible = "ti,omap4-gpio"; reg = <0x48057000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; @@ -201,7 +204,7 @@ gpio4: gpio@48059000 { compatible = "ti,omap4-gpio"; reg = <0x48059000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; @@ -212,7 +215,7 @@ gpio5: gpio@4805b000 { compatible = "ti,omap4-gpio"; reg = <0x4805b000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; @@ -223,7 +226,7 @@ gpio6: gpio@4805d000 { compatible = "ti,omap4-gpio"; reg = <0x4805d000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; @@ -234,7 +237,7 @@ gpio7: gpio@48051000 { compatible = "ti,omap4-gpio"; reg = <0x48051000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio7"; gpio-controller; #gpio-cells = <2>; @@ -245,7 +248,7 @@ gpio8: gpio@48053000 { compatible = "ti,omap4-gpio"; reg = <0x48053000 0x200>; - interrupts = ; + interrupts = ; ti,hwmods = "gpio8"; gpio-controller; #gpio-cells = <2>; @@ -256,7 +259,7 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart1"; clock-frequency = <48000000>; status = "disabled"; @@ -265,7 +268,7 @@ uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart2"; clock-frequency = <48000000>; status = "disabled"; @@ -274,7 +277,7 @@ uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart3"; clock-frequency = <48000000>; status = "disabled"; @@ -283,7 +286,7 @@ uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart4"; clock-frequency = <48000000>; status = "disabled"; @@ -292,7 +295,7 @@ uart5: serial@48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart5"; clock-frequency = <48000000>; status = "disabled"; @@ -301,7 +304,7 @@ uart6: serial@48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; - interrupts = ; + interrupts = ; ti,hwmods = "uart6"; clock-frequency = <48000000>; status = "disabled"; @@ -310,6 +313,7 @@ uart7: serial@48420000 { compatible = "ti,omap4-uart"; reg = <0x48420000 0x100>; + interrupts = ; ti,hwmods = "uart7"; clock-frequency = <48000000>; status = "disabled"; @@ -318,6 +322,7 @@ uart8: serial@48422000 { compatible = "ti,omap4-uart"; reg = <0x48422000 0x100>; + interrupts = ; ti,hwmods = "uart8"; clock-frequency = <48000000>; status = "disabled"; @@ -326,6 +331,7 @@ uart9: serial@48424000 { compatible = "ti,omap4-uart"; reg = <0x48424000 0x100>; + interrupts = ; ti,hwmods = "uart9"; clock-frequency = <48000000>; status = "disabled"; @@ -334,6 +340,7 @@ uart10: serial@4ae2b000 { compatible = "ti,omap4-uart"; reg = <0x4ae2b000 0x100>; + interrupts = ; ti,hwmods = "uart10"; clock-frequency = <48000000>; status = "disabled"; @@ -342,7 +349,7 @@ timer1: timer@4ae18000 { compatible = "ti,omap5430-timer"; reg = <0x4ae18000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer1"; ti,timer-alwon; }; @@ -350,28 +357,28 @@ timer2: timer@48032000 { compatible = "ti,omap5430-timer"; reg = <0x48032000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer2"; }; timer3: timer@48034000 { compatible = "ti,omap5430-timer"; reg = <0x48034000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer3"; }; timer4: timer@48036000 { compatible = "ti,omap5430-timer"; reg = <0x48036000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer4"; }; timer5: timer@48820000 { compatible = "ti,omap5430-timer"; reg = <0x48820000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer5"; ti,timer-dsp; }; @@ -379,7 +386,7 @@ timer6: timer@48822000 { compatible = "ti,omap5430-timer"; reg = <0x48822000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer6"; ti,timer-dsp; ti,timer-pwm; @@ -388,7 +395,7 @@ timer7: timer@48824000 { compatible = "ti,omap5430-timer"; reg = <0x48824000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer7"; ti,timer-dsp; }; @@ -396,7 +403,7 @@ timer8: timer@48826000 { compatible = "ti,omap5430-timer"; reg = <0x48826000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer8"; ti,timer-dsp; ti,timer-pwm; @@ -405,21 +412,21 @@ timer9: timer@4803e000 { compatible = "ti,omap5430-timer"; reg = <0x4803e000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer9"; }; timer10: timer@48086000 { compatible = "ti,omap5430-timer"; reg = <0x48086000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer10"; }; timer11: timer@48088000 { compatible = "ti,omap5430-timer"; reg = <0x48088000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "timer11"; ti,timer-pwm; }; @@ -427,6 +434,7 @@ timer13: timer@48828000 { compatible = "ti,omap5430-timer"; reg = <0x48828000 0x80>; + interrupts = ; ti,hwmods = "timer13"; status = "disabled"; }; @@ -434,6 +442,7 @@ timer14: timer@4882a000 { compatible = "ti,omap5430-timer"; reg = <0x4882a000 0x80>; + interrupts = ; ti,hwmods = "timer14"; status = "disabled"; }; @@ -441,6 +450,7 @@ timer15: timer@4882c000 { compatible = "ti,omap5430-timer"; reg = <0x4882c000 0x80>; + interrupts = ; ti,hwmods = "timer15"; status = "disabled"; }; @@ -448,6 +458,7 @@ timer16: timer@4882e000 { compatible = "ti,omap5430-timer"; reg = <0x4882e000 0x80>; + interrupts = ; ti,hwmods = "timer16"; status = "disabled"; }; @@ -455,7 +466,7 @@ wdt2: wdt@4ae14000 { compatible = "ti,omap4-wdt"; reg = <0x4ae14000 0x80>; - interrupts = ; + interrupts = ; ti,hwmods = "wd_timer2"; }; @@ -469,14 +480,14 @@ dmm@4e000000 { compatible = "ti,omap5-dmm"; reg = <0x4e000000 0x800>; - interrupts = <0 113 0x4>; + interrupts = ; ti,hwmods = "dmm"; }; i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; reg = <0x48070000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -486,7 +497,7 @@ i2c2: i2c@48072000 { compatible = "ti,omap4-i2c"; reg = <0x48072000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -496,7 +507,7 @@ i2c3: i2c@48060000 { compatible = "ti,omap4-i2c"; reg = <0x48060000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; @@ -506,7 +517,7 @@ i2c4: i2c@4807a000 { compatible = "ti,omap4-i2c"; reg = <0x4807a000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c4"; @@ -516,7 +527,7 @@ i2c5: i2c@4807c000 { compatible = "ti,omap4-i2c"; reg = <0x4807c000 0x100>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c5"; @@ -526,7 +537,7 @@ mmc1: mmc@4809c000 { compatible = "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; - interrupts = ; + interrupts = ; ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; @@ -539,7 +550,7 @@ mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; - interrupts = ; + interrupts = ; ti,hwmods = "mmc2"; ti,needs-special-reset; dmas = <&sdma 47>, <&sdma 48>; @@ -550,7 +561,7 @@ mmc3: mmc@480ad000 { compatible = "ti,omap4-hsmmc"; reg = <0x480ad000 0x400>; - interrupts = ; + interrupts = ; ti,hwmods = "mmc3"; ti,needs-special-reset; dmas = <&sdma 77>, <&sdma 78>; @@ -561,7 +572,7 @@ mmc4: mmc@480d1000 { compatible = "ti,omap4-hsmmc"; reg = <0x480d1000 0x400>; - interrupts = ; + interrupts = ; ti,hwmods = "mmc4"; ti,needs-special-reset; dmas = <&sdma 57>, <&sdma 58>; @@ -704,7 +715,7 @@ mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; reg = <0x48098000 0x200>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; @@ -725,7 +736,7 @@ mcspi2: spi@4809a000 { compatible = "ti,omap4-mcspi"; reg = <0x4809a000 0x200>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi2"; @@ -741,7 +752,7 @@ mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; reg = <0x480b8000 0x200>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi3"; @@ -754,7 +765,7 @@ mcspi4: spi@480ba000 { compatible = "ti,omap4-mcspi"; reg = <0x480ba000 0x200>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi4"; @@ -774,7 +785,7 @@ clocks = <&qspi_gfclk_div>; clock-names = "fck"; num-cs = <4>; - interrupts = <0 343 0x4>; + interrupts = ; status = "disabled"; }; @@ -810,7 +821,7 @@ sata: sata@4a141100 { compatible = "snps,dwc-ahci"; reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; - interrupts = ; + interrupts = ; phys = <&sata_phy>; phy-names = "sata-phy"; clocks = <&sata_ref_clk>; @@ -887,7 +898,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss1"; reg = <0x48880000 0x10000>; - interrupts = <0 77 4>; + interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -895,7 +906,7 @@ usb1: usb@48890000 { compatible = "snps,dwc3"; reg = <0x48890000 0x17000>; - interrupts = <0 76 4>; + interrupts = ; phys = <&usb2_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; tx-fifo-resize; @@ -908,7 +919,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss2"; reg = <0x488c0000 0x10000>; - interrupts = <0 92 4>; + interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -916,7 +927,7 @@ usb2: usb@488d0000 { compatible = "snps,dwc3"; reg = <0x488d0000 0x17000>; - interrupts = <0 78 4>; + interrupts = ; phys = <&usb2_phy2>; phy-names = "usb2-phy"; tx-fifo-resize; @@ -930,7 +941,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss3"; reg = <0x48900000 0x10000>; - /* interrupts = <0 TBD 4>; */ + interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -939,7 +950,7 @@ usb3: usb@48910000 { compatible = "snps,dwc3"; reg = <0x48910000 0x17000>; - /* interrupts = <0 93 4>; */ + interrupts = ; tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; @@ -950,7 +961,7 @@ compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss4"; reg = <0x48940000 0x10000>; - /* interrupts = <0 TBD 4>; */ + interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; @@ -959,7 +970,7 @@ usb4: usb@48950000 { compatible = "snps,dwc3"; reg = <0x48950000 0x17000>; - /* interrupts = <0 TBD 4>; */ + interrupts = ; tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; @@ -969,7 +980,7 @@ elm: elm@48078000 { compatible = "ti,am3352-elm"; reg = <0x48078000 0xfc0>; /* device IO registers */ - interrupts = ; + interrupts = ; ti,hwmods = "elm"; status = "disabled"; }; @@ -978,13 +989,24 @@ compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; reg = <0x50000000 0x37c>; /* device IO registers */ - interrupts = ; + interrupts = ; gpmc,num-cs = <8>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; status = "disabled"; }; + + crossbar_mpu: crossbar@4a020000 { + compatible = "ti,irq-crossbar"; + reg = <0x4a002a48 0x130>; + ti,max-irqs = <160>; + ti,max-crossbar-sources = ; + ti,reg-size = <2>; + ti,irqs-reserved = <0 1 2 3 5 6 131 132>; + ti,irqs-skip = <10 133 139 140>; + ti,irqs-safe-map = <0>; + }; }; }; -- cgit v1.2.3 From d1ff66b52dbe6ac7c13c77767759d1ac84f5da9d Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:21 +0530 Subject: ARM: dts: dra7: Add dt data for PCIe PHY control module Added dt data for PCIe PHY control module used by PCIe PHY. The documention for this node can be found @ ../bindings/phy/ti-phy.txt Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm/boot/dts/dra7.dtsi') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 961be6b8ffbf..e4999e4b7b65 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -828,6 +828,23 @@ ti,hwmods = "sata"; }; + omap_control_pcie1phy: control-phy@0x4a003c40 { + compatible = "ti,control-phy-pcie"; + reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; + reg-names = "power", "control_sma", "pcie_pcs"; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + }; + + omap_control_pcie2phy: control-pcie@0x4a003c44 { + compatible = "ti,control-phy-pcie"; + reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; + reg-names = "power", "control_sma", "pcie_pcs"; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + status = "disabled"; + }; + omap_control_usb2phy1: control-phy@4a002300 { compatible = "ti,control-phy-usb2"; reg = <0x4a002300 0x4>; -- cgit v1.2.3 From 692df0ef5abb7d8b36d70762134b842b70a55c31 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:22 +0530 Subject: ARM: dts: dra7: Add dt data for PCIe PHY Added dt data for PCIe PHY as a child node of ocp2scp3. The documention for this node can be found @ ../bindings/phy/ti-phy.txt. 26.3.3 PCIe Shared PHY Subsystem Integration in vE of DRA7xx ES1.0 describes the PCIe PHY subsystem-related components integrated in the device. Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm/boot/dts/dra7.dtsi') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e4999e4b7b65..cbaf47db2b6e 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -816,6 +816,47 @@ clock-names = "sysclk"; #phy-cells = <0>; }; + + pcie1_phy: pciephy@4a094000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x4a094000 0x80>, /* phy_rx */ + <0x4a094400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + ctrl-module = <&omap_control_pcie1phy>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&optfclk_pciephy1_32khz>, + <&optfclk_pciephy1_clk>, + <&optfclk_pciephy1_div_clk>, + <&optfclk_pciephy_div>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div"; + #phy-cells = <0>; + id = <1>; + ti,hwmods = "pcie1-phy"; + }; + + pcie2_phy: pciephy@4a095000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x4a095000 0x80>, /* phy_rx */ + <0x4a095400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + ctrl-module = <&omap_control_pcie2phy>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&optfclk_pciephy2_32khz>, + <&optfclk_pciephy2_clk>, + <&optfclk_pciephy2_div_clk>, + <&optfclk_pciephy_div>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div"; + #phy-cells = <0>; + ti,hwmods = "pcie2-phy"; + id = <2>; + status = "disabled"; + }; }; sata: sata@4a141100 { -- cgit v1.2.3 From 18dcd79db798f710a25dee203b765ef62389f0e1 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 14 Jul 2014 16:12:23 +0530 Subject: ARM: dts: dra7: Add dt data for PCIe controller Added dt data for PCIe controller. This node contains dt data for both the DRA7 part of designware controller and for the designware core. The documention for this node can be found @ ../bindings/pci/ti-pci.txt. Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Cc: Bjorn Helgaas Cc: Jingoo Han Cc: Jason Gunthorpe Cc: Marek Vasut Cc: Arnd Bergmann Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 69 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) (limited to 'arch/arm/boot/dts/dra7.dtsi') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index cbaf47db2b6e..b6060d37d1cf 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -99,6 +99,75 @@ }; }; + axi@0 { + compatible = "simple-bus"; + #size-cells = <1>; + #address-cells = <1>; + ranges = <0x51000000 0x51000000 0x3000 + 0x0 0x20000000 0x10000000>; + pcie@51000000 { + compatible = "ti,dra7-pcie"; + reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; + reg-names = "rc_dbics", "ti_conf", "config"; + interrupts = <0 232 0x4>, <0 233 0x4>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x03000 0 0x00010000 + 0x82000000 0 0x20013000 0x13000 0 0xffed000>; + #interrupt-cells = <1>; + num-lanes = <1>; + ti,hwmods = "pcie1"; + phys = <&pcie1_phy>; + phy-names = "pcie-phy0"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 1>, + <0 0 0 2 &pcie1_intc 2>, + <0 0 0 3 &pcie1_intc 3>, + <0 0 0 4 &pcie1_intc 4>; + pcie1_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + axi@1 { + compatible = "simple-bus"; + #size-cells = <1>; + #address-cells = <1>; + ranges = <0x51800000 0x51800000 0x3000 + 0x0 0x30000000 0x10000000>; + status = "disabled"; + pcie@51000000 { + compatible = "ti,dra7-pcie"; + reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; + reg-names = "rc_dbics", "ti_conf", "config"; + interrupts = <0 355 0x4>, <0 356 0x4>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x03000 0 0x00010000 + 0x82000000 0 0x30013000 0x13000 0 0xffed000>; + #interrupt-cells = <1>; + num-lanes = <1>; + ti,hwmods = "pcie2"; + phys = <&pcie2_phy>; + phy-names = "pcie-phy0"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 1>, + <0 0 0 2 &pcie2_intc 2>, + <0 0 0 3 &pcie2_intc 3>, + <0 0 0 4 &pcie2_intc 4>; + pcie2_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + cm_core_aon: cm_core_aon@4a005000 { compatible = "ti,dra7-cm-core-aon"; reg = <0x4a005000 0x2000>; -- cgit v1.2.3