From fa781ddab92909ae06c83cf14dea09eda81d7ba4 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 24 Sep 2014 00:16:45 +0900 Subject: ARM: dts: Add rtc_src clk for s3c-rtc on exynos Peach boards commit 546b117fdf17 ("rtc: s3c: add support for RTC of Exynos3250 SoC") added an "rtc_src" DT property for the Samsung's S3C Real Time Clock controller that specifies the 32.768 kHz clock that uses the RTC as its source clock. In the case of the Peach Pit and Pi machines, the Maxim 77802 32kHz AP clock is used as the source clock. Signed-off-by: Javier Martinez Canillas Reviewed-by: Doug Anderson Reviewed-by: Chanwoo Choi Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5800-peach-pi.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/exynos5800-peach-pi.dts') diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 7bb1c8dd42dd..fdbcec693b6d 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -12,6 +12,7 @@ #include #include #include +#include #include "exynos5800.dtsi" / { @@ -150,7 +151,7 @@ status = "okay"; clock-frequency = <400000>; - max77802-pmic@9 { + max77802: max77802-pmic@9 { compatible = "maxim,max77802"; interrupt-parent = <&gpx3>; interrupts = <1 IRQ_TYPE_NONE>; @@ -715,6 +716,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; + clock-names = "rtc", "rtc_src"; }; &spi_2 { -- cgit v1.2.3