From 26508cb703c6b08df53b8c856b90227237c62361 Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Sat, 8 Feb 2014 14:15:37 +0800 Subject: ARM: dts: imx27 phycore pinctrl Add pinctrl nodes and properties for phycore device nodes. Signed-off-by: Markus Pargmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts') diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index ad76d88a90ff..959dddf60d1f 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -19,6 +19,28 @@ cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>; }; +&iomuxc { + imx27_phycore_rdk { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX27_PAD_UART2_TXD__UART2_TXD 0x0 + MX27_PAD_UART2_RXD__UART2_RXD 0x0 + MX27_PAD_UART2_CTS__UART2_CTS 0x0 + MX27_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + }; +}; + &sdhci2 { bus-width = <4>; cd-gpios = <&gpio3 29 0>; @@ -29,11 +51,15 @@ &uart1 { fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &uart2 { fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; -- cgit v1.2.3