From 8a9618f5dfca35edb0d7ab6374ff586e2e9e989b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 6 Oct 2010 16:18:08 +0100 Subject: ARM: 6432/1: move timer-sp.c from versatile to common From: Rob Herring The timer-sp h/w used on versatile platforms can also be used for other platforms, so move it to a common location. Signed-off-by: Rob Herring Signed-off-by: Russell King --- arch/arm/include/asm/hardware/timer-sp.h | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 arch/arm/include/asm/hardware/timer-sp.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h new file mode 100644 index 000000000000..21e75e30d497 --- /dev/null +++ b/arch/arm/include/asm/hardware/timer-sp.h @@ -0,0 +1,2 @@ +void sp804_clocksource_init(void __iomem *); +void sp804_clockevents_init(void __iomem *, unsigned int); -- cgit v1.2.3 From 4b3bf7aef94fc337610d78fce0d960e2ee1d5a8f Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Thu, 18 Nov 2010 19:13:19 +0100 Subject: ARM: 6486/1: provide zero vmcore_elf64_check_arch() Since we don't support 64-bit ELF vmcores. This also prevents the following warning: fs/proc/vmcore.c: In function 'parse_crash_elf64_headers': fs/proc/vmcore.c:502: warning: passing argument 1 of 'elf_check_arch' from incompatible pointer type Signed-off-by: Mika Westerberg Signed-off-by: Russell King --- arch/arm/include/asm/elf.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index 8bb66bca2e3e..c3cd8755e648 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -99,6 +99,8 @@ struct elf32_hdr; extern int elf_check_arch(const struct elf32_hdr *); #define elf_check_arch elf_check_arch +#define vmcore_elf64_check_arch(x) (0) + extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int); #define elf_read_implies_exec(ex,stk) arm_elf_read_implies_exec(&(ex), stk) -- cgit v1.2.3 From 8931360eb9c6ec8bd30efef579cef81917a2fcf3 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 12 Nov 2010 13:02:46 +0000 Subject: ARM: module: clean up handling of ELF unwind tables There's no need to keep pointers to the ELF sections available while the module is loaded - we only need the section pointers while we're finding and registering the unwind tables, which can all be done during the finalize stage of loading. Signed-off-by: Russell King --- arch/arm/include/asm/module.h | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h index cbb0bc295d2b..12c8e680cbff 100644 --- a/arch/arm/include/asm/module.h +++ b/arch/arm/include/asm/module.h @@ -8,11 +8,6 @@ struct unwind_table; #ifdef CONFIG_ARM_UNWIND -struct arm_unwind_mapping { - Elf_Shdr *unw_sec; - Elf_Shdr *sec_text; - struct unwind_table *unwind; -}; enum { ARM_SEC_INIT, ARM_SEC_DEVINIT, @@ -21,13 +16,13 @@ enum { ARM_SEC_DEVEXIT, ARM_SEC_MAX, }; +#endif + struct mod_arch_specific { - struct arm_unwind_mapping map[ARM_SEC_MAX]; -}; -#else -struct mod_arch_specific { -}; +#ifdef CONFIG_ARM_UNWIND + struct unwind_table *unwind[ARM_SEC_MAX]; #endif +}; /* * Include the ARM architecture version. -- cgit v1.2.3 From 0946b8c5c5982088a26da7ad99e8bcf57f972fb5 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Wed, 1 Dec 2010 18:05:13 +0100 Subject: ARM: 6517/1: kexec: Add missing memory clobber to inline asm in crash_setup_regs() Currently, the inline asm is passed &newregs->ARM_r0 as in input, when modifying multiple fields of newregs. It's plausible to assume that GCC will assume newregs->ARM_r0 is modified when passed the address, but unfortunately this assumption is incorrect. Also, GCC has no way to guess that the other ARM_r* fields are modified without the addition of a "memory" clobber. Signed-off-by: Dave Martin Acked-by: Catalin Marinas Acked-by: Will Deacon Signed-off-by: Russell King --- arch/arm/include/asm/kexec.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h index 8ec9ef5c3c7b..b37e02c91693 100644 --- a/arch/arm/include/asm/kexec.h +++ b/arch/arm/include/asm/kexec.h @@ -34,7 +34,7 @@ static inline void crash_setup_regs(struct pt_regs *newregs, memcpy(newregs, oldregs, sizeof(*newregs)); } else { __asm__ __volatile__ ("stmia %0, {r0 - r15}" - : : "r" (&newregs->ARM_r0)); + : : "r" (&newregs->ARM_r0) : "memory"); __asm__ __volatile__ ("mrs %0, cpsr" : "=r" (newregs->ARM_cpsr)); } -- cgit v1.2.3 From cd849ae9cd291117c0f7e0e8d531ab62a906e308 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Wed, 1 Dec 2010 18:05:14 +0100 Subject: ARM: 6518/1: kexec: Fix crash_setup_regs() for ARMv7 and CONFIG_THUMB2_KERNEL * Fix kexec build failure with CONFIG_THUMB2_KERNEL. * Avoids deprecated/forbidden sp and pc usage in for ARMv7 onwards, retaining compatibility with older architecture versions. * The pc value saved to newregs is now aligned on a predictable instruction boundary. (stmia { ... pc } or str pc has implementation-defined results in most versions of the ARM architecutre, and is prohibited (unpredictable) in Thumb-2.) * Switch to named inline asm arguments (else I get readily confused ...) The resulting code should be compatible with all architecture versions >= v3, with or without CONFIG_THUMB2_KERNEL. Reviewed-by: Will Deacon Tested-by: Mika Westerberg Signed-off-by: Dave Martin Acked-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/include/asm/kexec.h | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h index b37e02c91693..c0094d8edae4 100644 --- a/arch/arm/include/asm/kexec.h +++ b/arch/arm/include/asm/kexec.h @@ -33,10 +33,20 @@ static inline void crash_setup_regs(struct pt_regs *newregs, if (oldregs) { memcpy(newregs, oldregs, sizeof(*newregs)); } else { - __asm__ __volatile__ ("stmia %0, {r0 - r15}" - : : "r" (&newregs->ARM_r0) : "memory"); - __asm__ __volatile__ ("mrs %0, cpsr" - : "=r" (newregs->ARM_cpsr)); + __asm__ __volatile__ ( + "stmia %[regs_base], {r0-r12}\n\t" + "mov %[_ARM_sp], sp\n\t" + "str lr, %[_ARM_lr]\n\t" + "adr %[_ARM_pc], 1f\n\t" + "mrs %[_ARM_cpsr], cpsr\n\t" + "1:" + : [_ARM_pc] "=r" (newregs->ARM_pc), + [_ARM_cpsr] "=r" (newregs->ARM_cpsr), + [_ARM_sp] "=r" (newregs->ARM_sp), + [_ARM_lr] "=o" (newregs->ARM_lr) + : [regs_base] "r" (&newregs->ARM_r0) + : "memory" + ); } } -- cgit v1.2.3 From 161d1907607a5a562a152058c8daf1780ce7a00b Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 16 Nov 2010 00:48:07 +0100 Subject: ARM: 6475/1: Introduce asm/hardware/entry-macro-gic.S This patch is the identical GIC demux implementation merge V3. Instead of implementing same code over and over simply share it in entry-macro-gic.S. The shared code is based on the realview implementation. Each GIC demux instance still has to setup the base address of the controller using the get_irqnr_preamble macro. The rest of the GIC specific code can be shared. Signed-off-by: Magnus Damm Acked-by: Srinidhi Kasagar Signed-off-by: Russell King --- arch/arm/include/asm/hardware/entry-macro-gic.S | 68 +++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 arch/arm/include/asm/hardware/entry-macro-gic.S (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S new file mode 100644 index 000000000000..05587f125a13 --- /dev/null +++ b/arch/arm/include/asm/hardware/entry-macro-gic.S @@ -0,0 +1,68 @@ +/* + * arch/arm/include/asm/hardware/entry-macro-gic.S + * + * Low-level IRQ helper macros for GIC + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + +/* + * The interrupt numbering scheme is defined in the + * interrupt controller spec. To wit: + * + * Interrupts 0-15 are IPI + * 16-28 are reserved + * 29-31 are local. We allow 30 to be used for the watchdog. + * 32-1020 are global + * 1021-1022 are reserved + * 1023 is "spurious" (no interrupt) + * + * For now, we ignore all local interrupts so only return an interrupt if it's + * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. + * + * A simple read from the controller will tell us the number of the highest + * priority enabled interrupt. We then just need to check whether it is in the + * valid range for an IRQ (30-1020 inclusive). + */ + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + ldr \irqstat, [\base, #GIC_CPU_INTACK] + /* bits 12-10 = src CPU, 9-0 = int # */ + + ldr \tmp, =1021 + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #29 + cmpcc \irqnr, \irqnr + cmpne \irqnr, \tmp + cmpcs \irqnr, \irqnr + .endm + +/* We assume that irqstat (the raw value of the IRQ acknowledge + * register) is preserved from the macro above. + * If there is an IPI, we immediately signal end of interrupt on the + * controller, since this requires the original irqstat value which + * we won't easily be able to recreate later. + */ + + .macro test_for_ipi, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #16 + strcc \irqstat, [\base, #GIC_CPU_EOI] + cmpcs \irqnr, \irqnr + .endm + +/* As above, this assumes that irqstat and base are preserved.. */ + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #29 + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 + .endm -- cgit v1.2.3 From a0b7bd0829194c03921915a68ee4a331ee394223 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 8 Dec 2010 13:49:04 +0000 Subject: ARM: io: make iounmap() a simple macro Defining iounmap() with arguments prevents it from being used as a function pointer, causing platforms to work around this. Instead, define it to be a simple macro. Do the same for __arch_io(re|un)map too. Signed-off-by: Russell King --- arch/arm/include/asm/io.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 815efa2d4e07..91be1f8c2d25 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -245,13 +245,13 @@ extern void _memset_io(volatile void __iomem *, int, size_t); #define ioremap_nocache(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE) #define ioremap_cached(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_CACHED) #define ioremap_wc(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_WC) -#define iounmap(cookie) __iounmap(cookie) +#define iounmap __iounmap #else #define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE) #define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE) #define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED) #define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC) -#define iounmap(cookie) __arch_iounmap(cookie) +#define iounmap __arch_iounmap #endif /* -- cgit v1.2.3 From 28257f7fdee0facc3b7f934e82c2485f27120d41 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 8 Dec 2010 13:57:48 +0000 Subject: ARM: io: simplify ioremap* and iounmap definitions We don't need to repeat the same definitions of the ioremap*(), once in terms of __arch_ioremap() and again in terms of __arm_ioremap(). Instead, if the platform hasn't provided an __arch_ioremap, define this to be __arm_ioremap, and only define the ioremap*() set using __arch_ioremap. Signed-off-by: Russell King --- arch/arm/include/asm/io.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 91be1f8c2d25..20e0f7c9e03e 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -241,18 +241,15 @@ extern void _memset_io(volatile void __iomem *, int, size_t); * */ #ifndef __arch_ioremap -#define ioremap(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE) -#define ioremap_nocache(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE) -#define ioremap_cached(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_CACHED) -#define ioremap_wc(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_WC) -#define iounmap __iounmap -#else +#define __arch_ioremap __arm_ioremap +#define __arch_iounmap __iounmap +#endif + #define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE) #define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE) #define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED) #define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC) #define iounmap __arch_iounmap -#endif /* * io{read,write}{8,16,32} macros -- cgit v1.2.3 From b580b899dd05a007ad232ee49a07b32d91876462 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Dec 2010 15:55:14 +0000 Subject: ARM: GIC: provide a single initialization function for boot CPU Provide gic_init() which initializes the GIC distributor and current CPU's GIC interface for the boot (or single) CPU. Reviewed-by: Catalin Marinas Tested-by: Abhijeet Dharmapurikar Signed-off-by: Russell King --- arch/arm/include/asm/hardware/gic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 7f34333bb545..387c6ae55673 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -33,8 +33,8 @@ #define GIC_DIST_SOFTINT 0xf00 #ifndef __ASSEMBLY__ -void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start); void gic_cpu_init(unsigned int gic_nr, void __iomem *base); +void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); #endif -- cgit v1.2.3 From 384895330e0f3954d9478fd0853145f9c169df12 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Dec 2010 16:01:03 +0000 Subject: ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_init We don't need to re-pass the base address for the CPU interfaces to the GIC for secondary CPUs, as it will never be different from the boot CPU - and even if it was, we'd overwrite the boot CPU's base address. Get rid of this argument, and rename to gic_secondary_init(). Reviewed-by: Catalin Marinas Tested-by: Abhijeet Dharmapurikar Signed-off-by: Russell King --- arch/arm/include/asm/hardware/gic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 387c6ae55673..48876a3fbda8 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -33,8 +33,8 @@ #define GIC_DIST_SOFTINT 0xf00 #ifndef __ASSEMBLY__ -void gic_cpu_init(unsigned int gic_nr, void __iomem *base); void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); +void gic_secondary_init(unsigned int); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); #endif -- cgit v1.2.3 From ff2e27ae0b17f53a6a289c87d325f706598f3788 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Dec 2010 16:13:29 +0000 Subject: ARM: GIC: consolidate gic_cpu_base_addr to common GIC code Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas Tested-by: Abhijeet Dharmapurikar Signed-off-by: Russell King --- arch/arm/include/asm/hardware/gic.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 48876a3fbda8..a82a77703544 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -33,6 +33,8 @@ #define GIC_DIST_SOFTINT 0xf00 #ifndef __ASSEMBLY__ +extern void __iomem *gic_cpu_base_addr; + void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); void gic_secondary_init(unsigned int); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); -- cgit v1.2.3 From 7627dc802a98aebebc6a34e5b6558ea4717c968c Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 5 Dec 2010 08:51:38 +0000 Subject: ARM: GIC: private a standard get_irqnr_preamble assembler macro Provide a standard get_irqnr_preamble assembler macro for platforms to use, which retrieves the base address of the GIC CPU interface from gic_cpu_base_addr. Allow platforms to override this by defining HAVE_GET_IRQNR_PREAMBLE. Reviewed-by: Catalin Marinas Tested-by: Abhijeet Dharmapurikar Signed-off-by: Russell King --- arch/arm/include/asm/hardware/entry-macro-gic.S | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S index 05587f125a13..c115b82fe80a 100644 --- a/arch/arm/include/asm/hardware/entry-macro-gic.S +++ b/arch/arm/include/asm/hardware/entry-macro-gic.S @@ -10,6 +10,13 @@ #include +#ifndef HAVE_GET_IRQNR_PREAMBLE + .macro get_irqnr_preamble, base, tmp + ldr \base, =gic_cpu_base_addr + ldr \base, [\base] + .endm +#endif + /* * The interrupt numbering scheme is defined in the * interrupt controller spec. To wit: -- cgit v1.2.3 From ac61d143ffe2a6db4d4bcf47c21a5159d6a1b644 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 6 Dec 2010 10:38:14 +0000 Subject: ARM: GIC: move enablement of PPI interrupts to gic.c Avoid adding nasty genirq-specific code to local timers to enable PPI interrupts. Instead, provide a gic function to do this. Signed-off-by: Russell King --- arch/arm/include/asm/hardware/gic.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index a82a77703544..84557d321001 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -39,6 +39,7 @@ void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); void gic_secondary_init(unsigned int); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); +void gic_enable_ppi(unsigned int); #endif #endif -- cgit v1.2.3