From 5817d10b8b8a6003bfb7551d0c3feb92deb74ed2 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 15 Aug 2012 19:07:30 +0200 Subject: ARM: dove: unify clock setup This patch synchronizes the clock setup of dove with other orion-based platforms. In dove_find_tclk there was a note about DOVE_SAMPLE_HI/LO register to detect tclk. While it might be possible to set a different tclk frequency with reset strapping the Dove datasheets don't tell anything about tclk frequency here. Therefore, I removed that comment. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/mach-dove/common.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-dove/common.c') diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 6321567d8eaa..8629e3043acd 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -33,8 +33,6 @@ #include #include "common.h" -static int get_tclk(void); - /***************************************************************************** * I/O Address Mapping ****************************************************************************/ @@ -70,12 +68,13 @@ void __init dove_map_io(void) /***************************************************************************** * CLK tree ****************************************************************************/ +static int dove_tclk; static struct clk *tclk; -static void __init clk_init(void) +static void __init dove_clk_init(void) { tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, - get_tclk()); + dove_tclk); orion_clkdev_init(tclk); } @@ -188,16 +187,16 @@ void __init dove_init_early(void) orion_time_set_base(TIMER_VIRT_BASE); } -static int get_tclk(void) +static int __init dove_find_tclk(void) { - /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */ return 166666667; } static void __init dove_timer_init(void) { + dove_tclk = dove_find_tclk(); orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, - IRQ_DOVE_BRIDGE, get_tclk()); + IRQ_DOVE_BRIDGE, dove_tclk); } struct sys_timer dove_timer = { @@ -285,8 +284,8 @@ void __init dove_sdio1_init(void) void __init dove_init(void) { - printk(KERN_INFO "Dove 88AP510 SoC, "); - printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); + pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", + (dove_tclk + 499999) / 1000000); #ifdef CONFIG_CACHE_TAUROS2 tauros2_init(); @@ -294,7 +293,7 @@ void __init dove_init(void) dove_setup_cpu_mbus(); /* Setup root of clk tree */ - clk_init(); + dove_clk_init(); /* internal devices that every board has */ dove_rtc_init(); -- cgit v1.2.3 From 521674718af0f20fada7311a74c3f8fe23767d55 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 15 Aug 2012 19:07:31 +0200 Subject: ARM: dove: add clock gating control This patch adds clock gates from the clock gating control register available on dove. All clock gates are hooked up to tclk, except for gigabit ethernet controller (ge) which is a child of gephy to allow both enabled/disabled at the same time. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/mach-dove/common.c | 57 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-dove/common.c') diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 8629e3043acd..38e2cc3b206b 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -69,14 +70,68 @@ void __init dove_map_io(void) * CLK tree ****************************************************************************/ static int dove_tclk; + +static DEFINE_SPINLOCK(gating_lock); static struct clk *tclk; +static struct clk __init *dove_register_gate(const char *name, + const char *parent, u8 bit_idx) +{ + return clk_register_gate(NULL, name, parent, 0, + (void __iomem *)CLOCK_GATING_CONTROL, + bit_idx, 0, &gating_lock); +} + static void __init dove_clk_init(void) { + struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; + struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; + struct clk *xor0, *xor1, *ge, *gephy; + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, dove_tclk); - orion_clkdev_init(tclk); + usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); + usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); + sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA); + pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0); + pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1); + sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0); + sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1); + nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND); + camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA); + i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0); + i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1); + crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO); + ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97); + pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA); + xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0); + xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1); + gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY); + ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE); + + orion_clkdev_add(NULL, "orion_spi.0", tclk); + orion_clkdev_add(NULL, "orion_spi.1", tclk); + orion_clkdev_add(NULL, "orion_wdt", tclk); + orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk); + + orion_clkdev_add(NULL, "orion-ehci.0", usb0); + orion_clkdev_add(NULL, "orion-ehci.1", usb1); + orion_clkdev_add(NULL, "mv643xx_eth.0", ge); + orion_clkdev_add("0", "sata_mv.0", sata); + orion_clkdev_add("0", "pcie", pex0); + orion_clkdev_add("1", "pcie", pex1); + orion_clkdev_add(NULL, "sdhci-dove.0", sdio0); + orion_clkdev_add(NULL, "sdhci-dove.1", sdio1); + orion_clkdev_add(NULL, "orion_nand", nand); + orion_clkdev_add(NULL, "cafe1000-ccic.0", camera); + orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0); + orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1); + orion_clkdev_add(NULL, "mv_crypto", crypto); + orion_clkdev_add(NULL, "dove-ac97", ac97); + orion_clkdev_add(NULL, "dove-pdma", pdma); + orion_clkdev_add(NULL, "mv_xor_shared.0", xor0); + orion_clkdev_add(NULL, "mv_xor_shared.1", xor1); } /***************************************************************************** -- cgit v1.2.3 From 624d0b52758d312ce1339bc88d23e6ef7ba980ee Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 15 Aug 2012 19:07:32 +0200 Subject: ARM: dove: add crypto engine This patch adds a dove specific setup function for the Marvell CESA crypto engine available on orion based SoCs. Dove setup was just missing a function to call orion_crypto_init with dove specific setup. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/mach-dove/common.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/mach-dove/common.c') diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 38e2cc3b206b..d5de814c52a3 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -258,6 +258,15 @@ struct sys_timer dove_timer = { .init = dove_timer_init, }; +/***************************************************************************** + * Cryptographic Engines and Security Accelerator (CESA) + ****************************************************************************/ +void __init dove_crypto_init(void) +{ + orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE, + DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO); +} + /***************************************************************************** * XOR 0 ****************************************************************************/ -- cgit v1.2.3 From 81d2ef7c40eceb7189872ecea5964f2041118d4a Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 15 Aug 2012 19:07:33 +0200 Subject: ARM: dove: add device tree based machine descriptor This adds a generic DT_MACHINE for mach-dove. As with other orion based SoCs there still is some glue code required to make all internal devices work, i.e. auxdata is provided to pass clocks to corresponding device drivers. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/mach-dove/common.c | 67 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) (limited to 'arch/arm/mach-dove/common.c') diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index d5de814c52a3..b12d11a5f2d0 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #include #include @@ -29,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -380,3 +383,67 @@ void dove_restart(char mode, const char *cmd) while (1) ; } + +#if defined(CONFIG_MACH_DOVE_DT) +/* + * Auxdata required until real OF clock provider + */ +struct of_dev_auxdata dove_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL), + OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL), + OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL), + OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0", + NULL), + OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL), + OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL), + OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL), + {}, +}; + +static struct mv643xx_eth_platform_data dove_dt_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, +}; + +static void __init dove_dt_init(void) +{ + pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", + (dove_tclk + 499999) / 1000000); + +#ifdef CONFIG_CACHE_TAUROS2 + tauros2_init(); +#endif + dove_setup_cpu_mbus(); + + /* Setup root of clk tree */ + dove_clk_init(); + + /* Internal devices not ported to DT yet */ + dove_rtc_init(); + dove_xor0_init(); + dove_xor1_init(); + + dove_ge00_init(&dove_dt_ge00_data); + dove_ehci0_init(); + dove_ehci1_init(); + dove_pcie_init(1, 1); + dove_crypto_init(); + + of_platform_populate(NULL, of_default_bus_match_table, + dove_auxdata_lookup, NULL); +} + +static const char * const dove_dt_board_compat[] = { + "marvell,dove", + NULL +}; + +DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)") + .map_io = dove_map_io, + .init_early = dove_init_early, + .init_irq = orion_dt_init_irq, + .timer = &dove_timer, + .init_machine = dove_dt_init, + .restart = dove_restart, + .dt_compat = dove_dt_board_compat, +MACHINE_END +#endif -- cgit v1.2.3