From 3ac804e31199c55440a423c76068d693b37fd50b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 2 Feb 2012 20:02:32 -0200 Subject: ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI The LPM field of register CCMR is used to select the mode that the processor will run when it goes to WFI. When mx31 enters in WFI mode the LPM field is at its reset value of 0, which configures the mx31 to enter in "wait mode". On mx35, the LPM field on mx35 is also at 0 after reset, which corresponds to "run mode" instead of "wait mode". Instead of relying on the reset value of LPM to set the low power mode for WFI, configure mx31 and mx35 to run in "wait mode" Reported-by: Benoit Thebaudeau Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/mm-imx3.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-imx/mm-imx3.c') diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index 31807d2a8b7b..905aafc1352c 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c @@ -34,6 +34,8 @@ static void imx3_idle(void) { unsigned long reg = 0; + mx3_cpu_lp_set(MX3_WAIT); + if (!need_resched()) __asm__ __volatile__( /* disable I and D cache */ -- cgit v1.2.3 From bb07d7511e0884f913a0610d5f9a2f8a27914042 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 29 Feb 2012 10:28:08 -0300 Subject: ARM: mx3: Setup AIPS registers It was observed on a mx31pdk board that audio playback only worked when the bootloader was Redboot, and did not work when U-boot was used. Comparing the sources of these bootloaders showed that the AIPS registers were not setup in U-boot. Instead of relying on the bootloader to setup the AIPS registers, do it in the kernel so that audio playback can work independantly of the bootloader being used. Copied the AIPS settings from Redboot to the kernel. Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/mm-imx3.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/mach-imx/mm-imx3.c') diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index 905aafc1352c..35ce8b5fe75d 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c @@ -177,6 +177,9 @@ void __init imx31_soc_init(void) } imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); + + imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR)); + imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR)); } #endif /* ifdef CONFIG_SOC_IMX31 */ -- cgit v1.2.3 From 38bb3630bcba25f16106166a4aaf211c1d195863 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 2 Mar 2012 07:45:59 -0300 Subject: ARM: mx35: Setup the AIPS registers Setup the AIPS registers on mx35. Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/mm-imx3.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/mach-imx/mm-imx3.c') diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index 31807d2a8b7b..d0c835c85b93 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c @@ -259,5 +259,9 @@ void __init imx35_soc_init(void) } imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); + + /* Setup AIPS registers */ + imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR)); + imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR)); } #endif /* ifdef CONFIG_SOC_IMX35 */ -- cgit v1.2.3