From 36b611f5e8c751a882f35eb6ec3647367e204d93 Mon Sep 17 00:00:00 2001 From: Gary Zhang Date: Fri, 4 Jan 2013 09:38:23 +0800 Subject: ENGR00238809-1 mx6sl: clock: add dependency of IRAM clk when IRAM is used by SSI, add IRAM clock dependency to SSI clock Signed-off-by: Gary Zhang --- arch/arm/mach-mx6/clock_mx6sl.c | 125 +++++++++++++++++++++++----------------- 1 file changed, 73 insertions(+), 52 deletions(-) (limited to 'arch/arm/mach-mx6') diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c index 961e7ee829ff..c6b08cbce8cb 100755 --- a/arch/arm/mach-mx6/clock_mx6sl.c +++ b/arch/arm/mach-mx6/clock_mx6sl.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -2427,23 +2427,30 @@ static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent) return 0; } -static struct clk ssi1_clk = { - __INIT_CLK_DEBUG(ssi1_clk) - .parent = &pll3_pfd2_508M, - .enable_reg = MXC_CCM_CCGR5, - .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable, - .set_parent = _clk_ssi1_set_parent, - .set_rate = _clk_ssi1_set_rate, - .round_rate = _clk_ssi_round_rate, - .get_rate = _clk_ssi1_get_rate, -#ifdef CONFIG_SND_MXC_SOC_IRAM - .secondary = &ocram_clk, -#else +static struct clk ssi1_clk[] = { + { + __INIT_CLK_DEBUG(ssi1_clk) + .parent = &pll3_pfd2_508M, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ssi1_set_parent, + .set_rate = _clk_ssi1_set_rate, + .round_rate = _clk_ssi_round_rate, + .get_rate = _clk_ssi1_get_rate, + .flags = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#ifndef CONFIG_SND_MXC_SOC_IRAM .secondary = &mmdc_ch1_axi_clk[0], + }, +#else + .secondary = &ssi1_clk[1], + }, + { + .parent = &mmdc_ch1_axi_clk[0], + .secondary = &ocram_clk, + }, #endif - .flags = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static unsigned long _clk_ssi2_get_rate(struct clk *clk) @@ -2501,23 +2508,30 @@ static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent) return 0; } -static struct clk ssi2_clk = { - __INIT_CLK_DEBUG(ssi2_clk) - .parent = &pll3_pfd2_508M, - .enable_reg = MXC_CCM_CCGR5, - .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable, - .set_parent = _clk_ssi2_set_parent, - .set_rate = _clk_ssi2_set_rate, - .round_rate = _clk_ssi_round_rate, - .get_rate = _clk_ssi2_get_rate, -#ifdef CONFIG_SND_MXC_SOC_IRAM - .secondary = &ocram_clk, -#else +static struct clk ssi2_clk[] = { + { + __INIT_CLK_DEBUG(ssi2_clk) + .parent = &pll3_pfd2_508M, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ssi2_set_parent, + .set_rate = _clk_ssi2_set_rate, + .round_rate = _clk_ssi_round_rate, + .get_rate = _clk_ssi2_get_rate, + .flags = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#ifndef CONFIG_SND_MXC_SOC_IRAM .secondary = &mmdc_ch1_axi_clk[0], + }, +#else + .secondary = &ssi2_clk[1], + }, + { + .parent = &mmdc_ch1_axi_clk[0], + .secondary = &ocram_clk, + }, #endif - .flags = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static unsigned long _clk_ssi3_get_rate(struct clk *clk) @@ -2574,23 +2588,30 @@ static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent) return 0; } -static struct clk ssi3_clk = { - __INIT_CLK_DEBUG(ssi3_clk) - .parent = &pll3_pfd2_508M, - .enable_reg = MXC_CCM_CCGR5, - .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable, - .set_parent = _clk_ssi3_set_parent, - .set_rate = _clk_ssi3_set_rate, - .round_rate = _clk_ssi_round_rate, - .get_rate = _clk_ssi3_get_rate, -#ifdef CONFIG_SND_MXC_SOC_IRAM - .secondary = &ocram_clk, -#else +static struct clk ssi3_clk[] = { + { + __INIT_CLK_DEBUG(ssi3_clk) + .parent = &pll3_pfd2_508M, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ssi3_set_parent, + .set_rate = _clk_ssi3_set_rate, + .round_rate = _clk_ssi_round_rate, + .get_rate = _clk_ssi3_get_rate, + .flags = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#ifndef CONFIG_SND_MXC_SOC_IRAM .secondary = &mmdc_ch1_axi_clk[0], + }, +#else + .secondary = &ssi3_clk[1], + }, + { + .parent = &mmdc_ch1_axi_clk[0], + .secondary = &ocram_clk, + }, #endif - .flags = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static unsigned long _clk_epdc_lcdif_pix_round_rate(struct clk *clk, @@ -3755,11 +3776,11 @@ static int _clk_clko2_set_parent(struct clk *clk, struct clk *parent) sel = 14; else if (parent == &usdhc2_clk) sel = 17; - else if (parent == &ssi1_clk) + else if (parent == &ssi1_clk[0]) sel = 18; - else if (parent == &ssi2_clk) + else if (parent == &ssi2_clk[0]) sel = 19; - else if (parent == &ssi3_clk) + else if (parent == &ssi3_clk[0]) sel = 20; else if (parent == &uart_clk[0]) sel = 28; @@ -3912,9 +3933,9 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk), _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk), _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, usdhc4_clk), - _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk), - _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk), - _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk), + _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk[0]), + _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk[0]), + _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk[0]), _REGISTER_CLOCK(NULL, "pxp_axi", pxp_axi_clk), _REGISTER_CLOCK(NULL, "epdc_axi", epdc_axi_clk), _REGISTER_CLOCK(NULL, "epdc_pix", epdc_pix_clk), -- cgit v1.2.3