From 5523e4092ee4f2ef58d00c78365c8bddf730c900 Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Thu, 10 Oct 2013 13:13:48 +0530 Subject: ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register The realtime counter called master counter, produces the count used by the private timer peripherals in the MPU_CLUSTER. The CNTFRQ per cpu register is used to denote the frequency of the counter. Currently the frequency value is passed from the DT file, but this is not scalable when we have other non-DT guest OS. This register must be set to the right value by the secure rom code. Setting this register helps in propagating the right frequency value across OSes. More discussions and the reason for adding this in a non-DT way can be seen from below. http://www.mail-archive.com/linux-omap@vger.kernel.org/msg93832.html So configuring this secure register for all the cpus here. Cc: Nishanth Menon Cc: Rajendra Nayak Cc: Marc Zyngier Cc: Mark Rutland Tested-by: Nishanth Menon Acked-by: Santosh Shilimkar Signed-off-by: Sricharan R Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap-secure.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/mach-omap2/omap-secure.h') diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 0e729170c46b..a5ee09d20ac9 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -42,6 +42,8 @@ #define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109 #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 +#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 + /* Secure PPA(Primary Protected Application) APIs */ #define OMAP4_PPA_L2_POR_INDEX 0x23 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 @@ -60,5 +62,7 @@ extern int omap_barrier_reserve_memblock(void); static inline void omap_barrier_reserve_memblock(void) { } #endif + +void set_cntfreq(void); #endif /* __ASSEMBLER__ */ #endif /* OMAP_ARCH_OMAP_SECURE_H */ -- cgit v1.2.3