From 7d7c3999aaa232e88fb84ce5aadb349d690dae6f Mon Sep 17 00:00:00 2001 From: Bo Yan Date: Fri, 18 May 2012 19:38:05 -0700 Subject: ARM: tegra11: Update cache flush/invalidate for power gating The field ENABLE_EXT in CSR register controls what power partition to be gated. If it's CPU-partition power gating only, there is no need to flush or invalidate L2 cache before/after power gating. With this change, L2 cache is flushed/invalidated only when the non-CPU partition is to be power gated or when rail gating is selected. Change-Id: I6be522de694117a058eedc9584f2157d89f99dc4 Signed-off-by: Bo Yan Reviewed-on: http://git-master/r/103476 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mark Stadler Reviewed-by: Jin Qian Reviewed-by: Krishna Reddy Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Rebase-Id: R3108cb94a1efc64574ff58067e239bd8539e6059 --- arch/arm/mach-tegra/sleep.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-tegra/sleep.S') diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index e640e25e685f..e7b8c654ee85 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -162,7 +162,7 @@ ENTRY(tegra_flush_l1_cache) dsb ldmfd sp!, {r4-r5, r7, r9-r11, lr} mov pc, lr -ENDPROC(tegra_flush_l1_dcache) +ENDPROC(tegra_flush_l1_cache) #ifdef CONFIG_PM_SLEEP /* -- cgit v1.2.3