From 3e6b424e14636a558c081290d14f8fc64ff16e87 Mon Sep 17 00:00:00 2001 From: Sumit Bhattacharya Date: Fri, 21 Oct 2011 11:58:36 +0530 Subject: arm: tegra: Add HDA support Modify HDA device names to be inline with Intel HDA driver. Also add entries for both HDA controller memory base address and HDA controller PCI base address. Also modify the dev_id and con_id of HDA related clocks so that they can be used by HDA driver. Bug 872652 Change-Id: Ifa05fe7d3d524e9ae310594a0e582c297dc52ef7 Signed-off-by: Sumit Bhattacharya Reviewed-on: http://git-master/r/59506 Reviewed-by: Scott Peterson Reviewed-by: Stephen Warren Rebase-Id: R098f861d94a78a1401841b71b8c591b902b7b0bc --- arch/arm/mach-tegra/tegra3_clocks.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-tegra/tegra3_clocks.c') diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 3b92d7d7bec5..f485a957cae8 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -3945,9 +3945,9 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), - PERIPH_CLK("hda", "hda", NULL, 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("hda2codec_2x", "hda2codec_2x", NULL, 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), - PERIPH_CLK("hda2hdmi", "hda2hdmi", NULL, 128, 0, 48000000, mux_clk_m, 0), + PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0), PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), -- cgit v1.2.3