From 97617674c5ccf02e5ae6803b645442c9147958cb Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Fri, 18 Nov 2011 13:03:46 -0800 Subject: ARM: tegra: clock: Enforce Tegra3 cbus parent assignments Tegra3 graphics bus (cbus) modules do not use PLLM as a clock source after boot. Explicitly enforced this policy now by failing set parent API if PLLM is selected as a target for any cbus clock. Bug 884419 Signed-off-by: Alex Frid (cherry picked from commit eb2662b7d90af77ee01202e57afa3ed46d4f9053) Change-Id: Ia17972c8c711d3498541ad62aef3961656433665 Reviewed-on: http://git-master/r/67832 Tested-by: Aleksandr Frid Reviewed-by: Yu-Huan Hsu --- arch/arm/mach-tegra/tegra3_clocks.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/mach-tegra/tegra3_clocks.c') diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 5f4586a9ca63..c0bd12a4f2b8 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -306,6 +306,8 @@ /* FIXME: recommended safety delay after lock is detected */ #define PLL_POST_LOCK_DELAY 100 +static bool tegra3_clk_is_parent_allowed(struct clk *c, struct clk *p); + static int tegra3_clk_shared_bus_update(struct clk *bus); static struct clk *emc_bridge; @@ -2048,6 +2050,9 @@ static int tegra3_periph_clk_set_parent(struct clk *c, struct clk *p) if (!(c->flags & MUX)) return (p == c->parent) ? 0 : (-EINVAL); + if (!tegra3_clk_is_parent_allowed(c, p)) + return -EINVAL; + for (sel = c->inputs; sel->input != NULL; sel++) { if (sel->input == p) { val = clk_readl(c->reg); @@ -2844,6 +2849,9 @@ static void tegra_clk_shared_bus_init(struct clk *c) c->u.shared_bus_user.client_id); return; } + c->u.shared_bus_user.client->flags |= + c->parent->flags & PERIPH_ON_CBUS; + c->flags |= c->parent->flags & PERIPH_ON_CBUS; c->div = c->u.shared_bus_user.client_div ? : 1; c->mul = 1; } @@ -3918,6 +3926,7 @@ static struct clk tegra_clk_cbus = { .max_rate = 700000000, .mul = 1, .div = 2, + .flags = PERIPH_ON_CBUS, .shared_bus_backup = { .input = &tegra_pll_p, .value = 2, @@ -4208,6 +4217,12 @@ struct clk *tegra_ptr_clks[] = { &tegra_clk_cbus, }; +static bool tegra3_clk_is_parent_allowed(struct clk *c, struct clk *p) +{ + if (c->flags & PERIPH_ON_CBUS) + return p != &tegra_pll_m; + return true; +} static void tegra3_init_one_clock(struct clk *c) { -- cgit v1.2.3