From d704606c727a8c3e14c66a5a5eb2c59afe327e8b Mon Sep 17 00:00:00 2001 From: Wen Yi Date: Wed, 18 Jan 2012 10:13:52 -0800 Subject: arm: tegra: enterprise: add 12.75mhz memory freq Add operation parameters for running emc at 12.75 MHz into emc dvfs table. Bug 922351 Bug 943239 Signed-off-by: Wen Yi Reviewed-on: http://git-master/r/79577 (cherry picked from commit 98f225dae75c8ed04cd11d0f6514f5259f3b9a9b) Change-Id: I98d972e76a988d167a214ddaac800a5a442f01c3 Signed-off-by: Mayuresh Kulkarni Reviewed-on: http://git-master/r/86298 Reviewed-by: Bharat Nihalani Tested-by: Bharat Nihalani --- arch/arm/mach-tegra/board-enterprise-memory.c | 120 ++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra3_clocks.c | 2 +- 2 files changed, 121 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/board-enterprise-memory.c b/arch/arm/mach-tegra/board-enterprise-memory.c index 1f09dfc4eec4..ba088f054cfc 100644 --- a/arch/arm/mach-tegra/board-enterprise-memory.c +++ b/arch/arm/mach-tegra/board-enterprise-memory.c @@ -24,6 +24,126 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { + { + 0x32, /* Rev 3.2 */ + 12750, /* SDRAM frequency */ + { + 0x00000000, /* EMC_RC */ + 0x00000001, /* EMC_RFC */ + 0x00000002, /* EMC_RAS */ + 0x00000002, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x00000004, /* EMC_W2R */ + 0x00000001, /* EMC_R2P */ + 0x00000005, /* EMC_W2P */ + 0x00000002, /* EMC_RD_RCD */ + 0x00000002, /* EMC_WR_RCD */ + 0x00000001, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000001, /* EMC_WDV */ + 0x00000003, /* EMC_QUSE */ + 0x00000001, /* EMC_QRST */ + 0x00000009, /* EMC_QSAFE */ + 0x0000000a, /* EMC_RDV */ + 0x0000002f, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x0000000b, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001, /* EMC_PDEX2WR */ + 0x00000001, /* EMC_PDEX2RD */ + 0x00000002, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000001, /* EMC_AR2PDEN */ + 0x00000007, /* EMC_RW2PDEN */ + 0x00000002, /* EMC_TXSR */ + 0x00000002, /* EMC_TXSRDLL */ + 0x00000003, /* EMC_TCKE */ + 0x00000008, /* EMC_TFAW */ + 0x00000004, /* EMC_TRPAB */ + 0x00000001, /* EMC_TCLKSTABLE */ + 0x00000002, /* EMC_TCLKSTOP */ + 0x00000036, /* EMC_TREFBW */ + 0x00000004, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00004282, /* EMC_FBIO_CFG5 */ + 0x007800a4, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000, /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ3 */ + 0x00100220, /* EMC_XM2CMDPADCTRL */ + 0x0800201c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc004, /* EMC_XM2CLKPADCTRL */ + 0x01f1f008, /* EMC_XM2COMPPADCTRL */ + 0x00000000, /* EMC_XM2VTTGENPADCTRL */ + 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000068, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00064000, /* EMC_ZCAL_INTERVAL */ + 0x00000009, /* EMC_ZCAL_WAIT_CNT */ + 0x00090009, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80000164, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00050001, /* MC_EMEM_ARB_CFG */ + 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000001, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000000, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2R */ + 0x02020001, /* MC_EMEM_ARB_DA_TURNS */ + 0x00060402, /* MC_EMEM_ARB_DA_COVERS */ + 0x77230303, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0x50000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ + }, + 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000001, /* EMC_CFG.PERIODIC_QRST */ + 0x00000000, /* Mode Register 0 */ + 0x00010022, /* Mode Register 1 */ + 0x00020001, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ + }, { 0x32, /* Rev 3.2 */ 25500, /* SDRAM frequency */ diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 1ecf1bacfaf3..de51b1e7627e 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -4106,7 +4106,7 @@ static struct clk tegra_clk_emc = { .ops = &tegra_emc_clk_ops, .reg = 0x19c, .max_rate = 900000000, - .min_rate = 25000000, + .min_rate = 12000000, .inputs = mux_pllm_pllc_pllp_clkm, .flags = MUX | DIV_U71 | PERIPH_EMC_ENB, .u.periph = { -- cgit v1.2.3