From edabd38e1a017e922e3e3b485ee3ddb4df433aa4 Mon Sep 17 00:00:00 2001 From: Saeed Bishara Date: Thu, 6 Aug 2009 15:12:43 +0300 Subject: ARM: add base support for Marvell Dove SoC The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek Signed-off-by: Saeed Bishara Signed-off-by: Nicolas Pitre --- arch/arm/mm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mm/Kconfig') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 9264d814cd7a..1549863d7b54 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -388,7 +388,7 @@ config CPU_FEROCEON_OLD_ID # ARMv6 config CPU_V6 - bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX + bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE select CPU_32v6 select CPU_ABRT_EV6 select CPU_PABRT_V6 -- cgit v1.2.3 From 573a652fb0da50a1ff3fca2c67afd81138fd06d2 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Tue, 24 Nov 2009 19:33:52 +0200 Subject: ARM: Add Tauros2 L2 cache controller support Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek Signed-off-by: Saeed Bishara Signed-off-by: Nicolas Pitre --- arch/arm/mm/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/mm/Kconfig') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 1549863d7b54..4958ef2c6254 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -764,6 +764,15 @@ config CACHE_L2X0 help This option enables the L2x0 PrimeCell. +config CACHE_TAUROS2 + bool "Enable the Tauros2 L2 cache controller" + depends on ARCH_DOVE + default y + select OUTER_CACHE + help + This option enables the Tauros2 L2 cache controller (as + found on PJ1/PJ4). + config CACHE_XSC3L2 bool "Enable the L2 cache on XScale3" depends on CPU_XSC3 -- cgit v1.2.3