From e426e71b4fe2b2907cba29f7be472e68efe2e47e Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Thu, 26 Jul 2012 15:24:38 +0800 Subject: ENGR00180931-1 mvf: add MSL support for MVF platform Add MSL support for MVF platform. Signed-off-by: Jason Jin Signed-off-by: Alison Wang Signed-off-by: Jingchang Lu --- arch/arm/plat-mxc/Kconfig | 18 + arch/arm/plat-mxc/Makefile | 9 +- arch/arm/plat-mxc/devices/Kconfig | 9 + arch/arm/plat-mxc/devices/Makefile | 3 + arch/arm/plat-mxc/include/mach/common.h | 7 + arch/arm/plat-mxc/include/mach/debug-macro.S | 6 +- arch/arm/plat-mxc/include/mach/devices-common.h | 35 ++ arch/arm/plat-mxc/include/mach/hardware.h | 4 + arch/arm/plat-mxc/include/mach/iomux-mvf.h | 285 +++++++++++ arch/arm/plat-mxc/include/mach/irqs.h | 4 +- arch/arm/plat-mxc/include/mach/memory.h | 6 +- arch/arm/plat-mxc/include/mach/mvf.h | 604 ++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mxc.h | 8 + arch/arm/plat-mxc/include/mach/timex.h | 4 +- arch/arm/plat-mxc/pit.c | 259 ++++++++++ 15 files changed, 1256 insertions(+), 5 deletions(-) create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mvf.h create mode 100644 arch/arm/plat-mxc/include/mach/mvf.h create mode 100644 arch/arm/plat-mxc/pit.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index e708ed448585..fb9f6e962f45 100755 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -54,11 +54,18 @@ config ARCH_MX6 help This enable support for systems based on the Freescale i.MX 6 Series family +config ARCH_MVF + bool "MVF-based" + select CPU_V7 + help + This enable support for systems based on the Freescale MVF Series family + endchoice source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-mx5/Kconfig" source "arch/arm/mach-mx6/Kconfig" +source "arch/arm/mach-mvf/Kconfig" endmenu ## Freescale private USB driver support @@ -118,6 +125,17 @@ config MXC_USE_EPIT uses the same clocks as the GPT. Anyway, on some systems the GPT may be in use for other purposes. +config HAVE_PIT + bool + +config MXC_USE_PIT + bool "Use PIT" + depends on HAVE_PIT + help + Use PIT as the system timer on systems that have it. + Anyway, on some systems the GPT may be in use such as mvf platform. + + config MXC_ULPI bool diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 6ff1c9072104..e2abb624f9d1 100755 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -3,7 +3,13 @@ # # Common support -obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o usb_common.o usb_wakeup.o +obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o usb_common.o usb_wakeup.o + +ifdef CONFIG_ARCH_MVF +obj-y += gpio-mvf.o +else +obj-y += gpio.o +endif # MX51 uses the TZIC interrupt controller, older platforms use AVIC obj-$(CONFIG_MXC_TZIC) += tzic.o @@ -15,6 +21,7 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o obj-$(CONFIG_MXC_PWM) += pwm.o obj-$(CONFIG_MXC_ULPI) += ulpi.o obj-$(CONFIG_MXC_USE_EPIT) += epit.o +obj-$(CONFIG_MXC_USE_PIT) += pit.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 3eead8ebda92..de80caba49c3 100755 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -169,3 +169,12 @@ config IMX_HAVE_PLATFORM_IMX_MIPI_DSI config IMX_HAVE_PLATFORM_IMX_MIPI_CSI2 bool + +config IMX_HAVE_PLATFORM_MVF_SPI + bool + +config IMX_HAVE_PLATFORM_MVF_DCU + bool + +config IMX_HAVE_PLATFORM_MVF_SAI + bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 71cfefa7cccb..63be99251f08 100755 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -61,3 +61,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI) += platform-imx-hdmi-soc-dai.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC) += platform-imx-asrc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI) += platform-imx-mipi_dsi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2) += platform-imx-mipi_csi2.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MVF_SPI) += platform-mvf-spi.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MVF_DCU) += platform-mvf-dcu.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MVF_SAI) += platform-mvf-sai.o diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 62489695af0f..aeda988171a7 100755 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -33,6 +33,7 @@ extern void mx50_map_io(void); extern void mx51_map_io(void); extern void mx53_map_io(void); extern void mx6_map_io(void); +extern void mvf_map_io(void); extern void mxc91231_map_io(void); extern void imx1_init_early(void); extern void imx21_init_early(void); @@ -56,7 +57,9 @@ extern void mx50_init_irq(void); extern void mx51_init_irq(void); extern void mx53_init_irq(void); extern void mx6_init_irq(void); +extern void mvf_init_irq(void); extern void mxc91231_init_irq(void); +extern void pit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); @@ -73,7 +76,10 @@ extern int mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1); extern int mx6_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); +extern int mvf_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckihl, unsigned long ckih2); extern void imx6_init_fec(struct fec_platform_data fec_data); +extern void mvf_init_fec(struct fec_platform_data fec_data); extern int mxc91231_clocks_init(unsigned long fref); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); @@ -88,4 +94,5 @@ extern int mx50_revision(void); extern int mx53_display_revision(void); extern unsigned long mx6_timer_rate(void); extern int mxs_reset_block(void __iomem *); +extern void __init early_console_setup(unsigned long base, struct clk *clk); #endif diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index e19086cc5015..5ea60acf447f 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -51,8 +51,12 @@ #define UART_PADDR MX6Q_UART4_BASE_ADDR #endif +#ifdef CONFIG_ARCH_MVF +#define UART_PADDR MVF_UART1_BASE_ADDR +#define UART_VADDR (0xF2000000 + MVF_UART1_BASE_ADDR) +#else #define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) - +#endif .macro addruart, rp, rv ldr \rp, =UART_PADDR @ physical ldr \rv, =UART_VADDR @ virtual diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 2f5f04c39638..2ba8c8663402 100755 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -2,6 +2,8 @@ * Copyright (C) 2009-2010 Pengutronix * Uwe Kleine-Koenig * + * Copyright 2012 Freescale Semiconductor, Inc. + * * This program is free software; you can redistribute it and/or modify it under * the terms of the GNU General Public License version 2 as published by the * Free Software Foundation. @@ -164,6 +166,22 @@ struct platform_device *__init imx_add_imx_esai( const struct imx_imx_esai_data *data, const struct imx_esai_platform_data *pdata); +#include +struct mvf_sai_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; + resource_size_t dmatx0; + resource_size_t dmarx0; + resource_size_t dmatx1; + resource_size_t dmarx1; +}; +struct platform_device *__init mvf_add_sai( + int id, + const struct mvf_sai_data *data, + const struct mvf_sai_platform_data *pdata); + #include struct imx_imx_uart_3irq_data { int id; @@ -322,6 +340,7 @@ struct platform_device *__init imx_add_sdhci_esdhc_imx( const struct esdhc_platform_data *pdata); #include +#include struct imx_spi_imx_data { const char *devid; int id; @@ -333,6 +352,10 @@ struct platform_device *__init imx_add_spi_imx( const struct imx_spi_imx_data *data, const struct spi_imx_master *pdata); +struct platform_device *__init mvf_add_spi_mvf( + const struct imx_spi_imx_data *data, + const struct spi_mvf_master *pdata); + #include struct imx_ipuv3_data { resource_size_t iobase; @@ -365,6 +388,18 @@ struct imx_vpu_data { struct platform_device *__init imx_add_vpu( const struct imx_vpu_data *data); +#include +struct mvf_dcu_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; + int (*init) (int); +}; +struct platform_device *__init mvf_add_dcu( + const int id, + const struct mvf_dcu_data *data, + struct mvf_dcu_platform_data *pdata); + #include struct imx_dvfs_core_data { resource_size_t iobase; diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index e1c523443ca8..871fa49959f5 100755 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -97,6 +97,10 @@ #include +#ifdef CONFIG_ARCH_MVF +#include +#endif + #ifdef CONFIG_ARCH_MX5 #include #include diff --git a/arch/arm/plat-mxc/include/mach/iomux-mvf.h b/arch/arm/plat-mxc/include/mach/iomux-mvf.h new file mode 100644 index 000000000000..92db9ebf5f2b --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mvf.h @@ -0,0 +1,285 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#ifndef __MACH_IOMUX_MVFA5_H__ +#define __MACH_IOMUX_MVFA5_H__ + +#include + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ +} iomux_pin_cfg_t; + +#define NON_MUX_I 0x3FF +#define NON_PAD_I 0x7FF + +#define MVF600_SDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) + +#define MVF600_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_50ohm) + +#define MVF600_I2C_PAD_CTRL (PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH) + +#define MVF600_SAI_PAD_CTRL (PAD_CTL_DSE_50ohm | PAD_CTL_HYS | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) + +#define MVF600_ESAI_PAD_CTRL (PAD_CTL_DSE_50ohm | PAD_CTL_HYS | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) + +#define MVF600_USB_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_50ohm) + +#define MVF600_DSPI_PAD_CTRL (PAD_CTL_SPEED_LOW | PAD_CTL_DSE_25ohm) + +#define MVF600_HIGH_DRV PAD_CTL_DSE_150ohm + +#define MVF600_DCU_PAD_CTRL (MVF600_HIGH_DRV | PAD_CTL_OBE_ENABLE) + +#define MVF600_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_25ohm) + +#define MVF600_GPIO_GENERAL_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_DSE_25ohm) + +/*SDHC1*/ +#define MVF600_PAD14_PTA24__SDHC1_CLK \ + IOMUX_PAD(0x0038, 0x0038, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL) +#define MVF600_PAD15_PTA25__SDHC1_CMD \ + IOMUX_PAD(0x003C, 0x003C, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL) +#define MVF600_PAD16_PTA26__SDHC1_DAT0 \ + IOMUX_PAD(0x0040, 0x0040, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL) +#define MVF600_PAD17_PTA27__SDHC1_DAT1 \ + IOMUX_PAD(0x0044, 0x0044, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL) +#define MVF600_PAD18_PTA28__SDHC1_DAT2 \ + IOMUX_PAD(0x0048, 0x0048, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL) +#define MVF600_PAD19_PTA29__SDHC1_DAT3 \ + IOMUX_PAD(0x004C, 0x004C, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL) +/*set PTA7 as GPIO for sdhc card detecting*/ +#define MVF600_PAD134_PTA7__SDHC1_SW_CD \ + IOMUX_PAD(0x0218, 0x0218, 0, 0x0000, 0, \ + MVF600_GPIO_GENERAL_CTRL | PAD_CTL_IBE_ENABLE) + +/*I2C0*/ +#define MVF600_PAD36_PTB14__I2C0_SCL \ + IOMUX_PAD(0x0090, 0x0090, 2, 0x033C, 1, \ + MVF600_I2C_PAD_CTRL | PAD_CTL_OBE_IBE_ENABLE) +#define MVF600_PAD37_PTB15__I2C0_SDA \ + IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, \ + MVF600_I2C_PAD_CTRL | PAD_CTL_OBE_IBE_ENABLE) + +/*CAN1*/ +#define MVF600_PAD38_PTB16__CAN1_RX \ + IOMUX_PAD(0x0098, 0x0098, 1, 0x0000, 0, 0) +#define MVF600_PAD39_PTB17__CAN1_TX \ + IOMUX_PAD(0x009C, 0x009C, 1, 0x0000, 0, 0) + +/*DSPI0*/ +#define MVF600_PAD41_PTB19__DSPI0_PCS0 \ + IOMUX_PAD(0x00A4, 0x00A4, 1, 0x0000, 0, \ + MVF600_DSPI_PAD_CTRL | PAD_CTL_OBE_ENABLE) +#define MVF600_PAD42_PTB20__DSPI0_SIN \ + IOMUX_PAD(0x00A8, 0x00A8, 1, 0x0000, 0, \ + MVF600_DSPI_PAD_CTRL | PAD_CTL_IBE_ENABLE) +#define MVF600_PAD43_PTB21__DSPI0_SOUT \ + IOMUX_PAD(0x00AC, 0x00AC, 1, 0x0000, 0, \ + MVF600_DSPI_PAD_CTRL | PAD_CTL_OBE_ENABLE) +#define MVF600_PAD44_PTB22__DSPI0_SCK \ + IOMUX_PAD(0x00B0, 0x00B0, 1, 0x0000, 0, \ + MVF600_DSPI_PAD_CTRL | PAD_CTL_OBE_IBE_ENABLE) + +/*FEC0*/ +#define MVF600_PAD0_PTA6__RMII_CLKIN \ + IOMUX_PAD(0x0000, 0x0000, 2, 0x02F0, 0, \ + MVF600_ENET_PAD_CTRL | PAD_CTL_IBE_ENABLE) +#define MVF600_PAD45_PTC0__RMII0_MDC \ + IOMUX_PAD(0x00B4, 0x00B4, 1, 0x0000, 0, \ + MVF600_ENET_PAD_CTRL | PAD_CTL_OBE_ENABLE) +#define MVF600_PAD46_PTC1__RMII0_MDIO \ + IOMUX_PAD(0x00B8, 0x00B8, 1, 0x0000, 0, \ + MVF600_ENET_PAD_CTRL | PAD_CTL_OBE_IBE_ENABLE) +/*check ?*/ +#define MVF600_PAD47_PTC2__RMII0_CRS_DV \ + IOMUX_PAD(0x00BC, 0x00BC, 1, 0x0000, 0, \ + MVF600_ENET_PAD_CTRL | PAD_CTL_IBE_ENABLE) +#define MVF600_PAD48_PTC3__RMII0_RXD1 \ + IOMUX_PAD(0x00C0, 0x00C0, 1, 0x0000, 0, \ + MVF600_ENET_PAD_CTRL | PAD_CTL_IBE_ENABLE) +#define MVF600_PAD49_PTC4__RMII0_RXD0 \ + IOMUX_PAD(0x00C4, 0x00C4, 1, 0x0000, 0, \ + MVF600_ENET_PAD_CTRL | PAD_CTL_IBE_ENABLE) +#define MVF600_PAD50_PTC5__RMII0_RXER \ + IOMUX_PAD(0x00C8, 0x00C8, 1, 0x0000, 0, \ + MVF600_ENET_PAD_CTRL | PAD_CTL_IBE_ENABLE) +#define MVF600_PAD51_PTC6__RMII0_TXD1 \ + IOMUX_PAD(0x00CC, 0x00CC, 1, 0x0000, 0, \ + MVF600_ENET_PAD_CTRL | PAD_CTL_OBE_ENABLE) +#define MVF600_PAD52_PTC7__RMII0_TXD0 \ + IOMUX_PAD(0x00D0, 0x00D0, 1, 0x0000, 0, \ + MVF600_ENET_PAD_CTRL | PAD_CTL_OBE_ENABLE) +#define MVF600_PAD53_PTC8__RMII0_TXEN \ + IOMUX_PAD(0x00D4, 0x00D4, 1, 0x0000, 0, \ + MVF600_ENET_PAD_CTRL | PAD_CTL_OBE_ENABLE) + +/*USB0/1 VBUS, using the GPIO*/ +#define MVF600_PAD85_PTD6__USB0_VBUS_EN \ + IOMUX_PAD(0x0154, 0x0154, 0, 0x0000, 0, \ + MVF600_GPIO_GENERAL_CTRL) +#define MVF600_PAD92_PTD13__USB1_VBUS_EN \ + IOMUX_PAD(0x0170, 0x0170, 0, 0x0000, 0, \ + MVF600_GPIO_GENERAL_CTRL) + +/*ESAI0(share with FEC1)*/ +#define MVF600_PAD54_PTC9__ESAI_SCKT \ + IOMUX_PAD(0x00D8, 0x00D8, 3, 0x0310, 1, MVF600_ESAI_PAD_CTRL) +#define MVF600_PAD55_PTC10__ESAI_FST \ + IOMUX_PAD(0x00DC, 0x00DC, 3, 0x030C, 1, MVF600_ESAI_PAD_CTRL) +#define MVF600_PAD56_PTC11__ESAI_SDO0 \ + IOMUX_PAD(0x00E0, 0x00E0, 3, 0x0314, 1, MVF600_ESAI_PAD_CTRL) +#define MVF600_PAD57_PTC12__ESAI_SDO1 \ + IOMUX_PAD(0x00E4, 0x00E4, 3, 0x0318, 1, MVF600_ESAI_PAD_CTRL) +#define MVF600_PAD58_PTC13__ESAI_SDO2 \ + IOMUX_PAD(0x00E8, 0x00E8, 3, 0x031C, 1, MVF600_ESAI_PAD_CTRL) +#define MVF600_PAD59_PTC14__ESAI_SDO3 \ + IOMUX_PAD(0x00EC, 0x00EC, 3, 0x0320, 1, MVF600_ESAI_PAD_CTRL) +#define MVF600_PAD60_PTC15__ESAI_SDI0 \ + IOMUX_PAD(0x00F0, 0x00F0, 3, 0x0328, 1, MVF600_ESAI_PAD_CTRL) +#define MVF600_PAD61_PTC16__ESAI_SDI1 \ + IOMUX_PAD(0x00F4, 0x00F4, 3, 0x0324, 1, MVF600_ESAI_PAD_CTRL) +/*ESAI0 ?*/ +#define MVF600_PAD75_PTD19__ESAI_SCKR \ + IOMUX_PAD(0x012C, 0x012C, 3, 0x0324, 1, MVF600_ESAI_PAD_CTRL) +#define MVF600_PAD76_PTD18__ESAI_FSR \ + IOMUX_PAD(0x0130, 0x0130, 3, 0x0324, 1, MVF600_ESAI_PAD_CTRL) +#define MVF600_PAD77_PTD17__ESAI_HCKR \ + IOMUX_PAD(0x0134, 0x0134, 3, 0x0324, 1, MVF600_ESAI_PAD_CTRL) +#define MVF600_PAD78_PTD16__ESAI_HCKT \ + IOMUX_PAD(0x0138, 0x0138, 3, 0x0324, 1, MVF600_ESAI_PAD_CTRL) + +/*SAI2*/ +#define MVF600_PAD6_PTA16_SAI2_TX_BCLK \ + IOMUX_PAD(0x0018, 0x0018, 5, 0x0370, 0, \ + MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE) +#define MVF600_PAD8_PTA18_SAI2_TX_DATA \ + IOMUX_PAD(0x0020, 0x0020, 5, 0x0000, 0, \ + MVF600_SAI_PAD_CTRL | PAD_CTL_OBE_ENABLE) +#define MVF600_PAD9_PTA19_SAI2_TX_SYNC \ + IOMUX_PAD(0x0024, 0x0024, 5, 0x0374, 0, \ + MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE) +#define MVF600_PAD11_PTA21_SAI2_RX_BCLK \ + IOMUX_PAD(0x002C, 0x002C, 5, 0x0364, 0, \ + MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE) +#define MVF600_PAD12_PTA22_SAI2_RX_DATA \ + IOMUX_PAD(0x0030, 0x0030, 5, 0x0368, 0, \ + MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE) +#define MVF600_PAD13_PTA23_SAI2_RX_SYNC \ + IOMUX_PAD(0x0034, 0x0034, 5, 0x036c, 0, \ + MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE) +#define MVF600_PAD40_PTB18_EXT_AUDIO_MCLK \ + IOMUX_PAD(0x00A0, 0x00A0, 2, 0x02ec, 2, \ + MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE) + +/*DCU0*/ +#define MVF600_PAD30_PTB8_LCD_ENABLE \ + IOMUX_PAD(0x78, 0x78, 0, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD105_PTE0_DCU0_HSYNC \ + IOMUX_PAD(0x01A4, 0x01A4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD106_PTE1_DCU0_VSYNC \ + IOMUX_PAD(0x01A8, 0x01A8, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD107_PTE2_DCU0_PCLK \ + IOMUX_PAD(0x01AC, 0x01AC, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD109_PTE4_DCU0_DE \ + IOMUX_PAD(0x01B4, 0x01B4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD110_PTE5_DCU0_R0 \ + IOMUX_PAD(0x01B8, 0x01B8, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD111_PTE6_DCU0_R1 \ + IOMUX_PAD(0x01BC, 0x01BC, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD112_PTE7_DCU0_R2 \ + IOMUX_PAD(0x01C0, 0x01C0, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD113_PTE8_DCU0_R3 \ + IOMUX_PAD(0x01C4, 0x01C4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD114_PTE9_DCU0_R4 \ + IOMUX_PAD(0x01C8, 0x01C8, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD115_PTE10_DCU0_R5 \ + IOMUX_PAD(0x01CC, 0x01CC, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD116_PTE11_DCU0_R6 \ + IOMUX_PAD(0x01D0, 0x01D0, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD117_PTE12_DCU0_R7 \ + IOMUX_PAD(0x01D4, 0x01D4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD118_PTE13_DCU0_G0 \ + IOMUX_PAD(0x01D8, 0x01D8, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD119_PTE14_DCU0_G1 \ + IOMUX_PAD(0x01DC, 0x01DC, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD120_PTE15_DCU0_G2 \ + IOMUX_PAD(0x01E0, 0x01E0, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD121_PTE16_DCU0_G3 \ + IOMUX_PAD(0x01E4, 0x01E4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD122_PTE17_DCU0_G4 \ + IOMUX_PAD(0x01E8, 0x01E8, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD123_PTE18_DCU0_G5 \ + IOMUX_PAD(0x01EC, 0x01EC, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD124_PTE19_DCU0_G6 \ + IOMUX_PAD(0x01F0, 0x01F0, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD125_PTE20_DCU0_G7 \ + IOMUX_PAD(0x01F4, 0x01F4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD126_PTE21_DCU0_B0 \ + IOMUX_PAD(0x01F8, 0x01F8, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD127_PTE22_DCU0_B1 \ + IOMUX_PAD(0x01FC, 0x01FC, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD128_PTE23_DCU0_B2 \ + IOMUX_PAD(0x0200, 0x0200, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD129_PTE24_DCU0_B3 \ + IOMUX_PAD(0x0204, 0x0204, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD130_PTE25_DCU0_B4 \ + IOMUX_PAD(0x0208, 0x0208, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD131_PTE26_DCU0_B5 \ + IOMUX_PAD(0x020C, 0x020C, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD132_PTE27_DCU0_B6 \ + IOMUX_PAD(0x0210, 0x0210, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD133_PTE28_DCU0_B7 \ + IOMUX_PAD(0x0214, 0x0214, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) + +/*UART1*/ +#define MVF600_PAD26_PTB4_UART1_TX \ + IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, \ + MVF600_UART_PAD_CTRL | PAD_CTL_OBE_ENABLE) +#define MVF600_PAD27_PTB5_UART1_RX \ + IOMUX_PAD(0x006C, 0x006C, 2, 0x037C, 0, \ + MVF600_UART_PAD_CTRL | PAD_CTL_IBE_ENABLE) + +#define MVF600_PAD32_PTB10_UART0_TX \ + IOMUX_PAD(0x0080, 0x0080, 1, 0x0000, 0, \ + MVF600_UART_PAD_CTRL | PAD_CTL_OBE_ENABLE) +#define MVF600_PAD33_PTB11_UART0_RX \ + IOMUX_PAD(0x0084, 0x0084, 1, 0x0000, 0, \ + MVF600_UART_PAD_CTRL | PAD_CTL_IBE_ENABLE) + +#endif diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 9e44eaa4824c..9fce85784a32 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2012 Freescale Semiconductor, Inc. */ /* @@ -42,6 +42,8 @@ #define MXC_GPIO_IRQS (32 * 3) #elif defined CONFIG_ARCH_MX6 #define MXC_GPIO_IRQS (32 * 7) +#elif defined CONFIG_ARCH_MVF +#define MXC_GPIO_IRQS (32 * 5) #endif /* diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index f478eb8c418b..2c91eed98e76 100755 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -23,6 +23,7 @@ #define MX51_PHYS_OFFSET UL(0x90000000) #define MX53_PHYS_OFFSET UL(0x70000000) #define MX6_PHYS_OFFSET UL(0x10000000) +#define MVF_PHYS_OFFSET UL(0x80000000) #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) # if defined CONFIG_ARCH_MX1 @@ -45,6 +46,8 @@ # define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET # elif defined CONFIG_ARCH_MX6 # define PLAT_PHYS_OFFSET MX6_PHYS_OFFSET +# elif defined CONFIG_ARCH_MVF +# define PLAT_PHYS_OFFSET MVF_PHYS_OFFSET # endif #endif @@ -63,7 +66,8 @@ #define CONSISTENT_DMA_SIZE SZ_4M #else -#if defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX6) +#if defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX6) \ + || defined(CONFIG_ARCH_MVF) #define ARM_DMA_ZONE_SIZE (184 * SZ_1M) #define CONSISTENT_DMA_SIZE ARM_DMA_ZONE_SIZE #else diff --git a/arch/arm/plat-mxc/include/mach/mvf.h b/arch/arm/plat-mxc/include/mach/mvf.h new file mode 100644 index 000000000000..cd5f8c252c6e --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mvf.h @@ -0,0 +1,604 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MVF_H__ +#define __MACH_MVF_H__ + +/* + * IROM + */ +#define MVF_IROM_BASE_ADDR 0x0 +#define MVF_IROM_SIZE (SZ_64K + SZ_32K) +#define BOOT_ROM_BASE_ADDR MVF_IROM_BASE_ADDR +#define ROMCP_SIZE MVF_IROM_SIZE +/* TZASC */ +#define MVF_TZASC_BASE_ADDR 0x40010000 + +/* + * AHCI SATA + */ +#define MVF_SATA_BASE_ADDR 0x10000000 + +/* + * NFC + */ +#define MVF_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */ +#define MVF_NFC_AXI_SIZE SZ_64K + +/* CPU Memory Map */ +#define DDRMC0_BASE_ADDR 0x80000000 +#define DDRMC0_END_ADDR 0xDFFFFFFF +#define DDRMC1_BASE_ADDR 0xE0000000 +#define DDRMC1_END_ADDR 0xEFFFFFFF +#define OCRAM_ARB_BASE_ADDR 0x3F000000 +#define OCRAM_ARB_END_ADDR 0x3F3FFFFF +#define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR + +/* + * IRAM + */ +#define MVF_IRAM_BASE_ADDR 0x3F000000 /* internal ram */ +#define MVF_IRAM_PARTITIONS 2 +#define MVF_IRAM_SIZE (MVF_IRAM_PARTITIONS * SZ_256K) /* 512KB */ + + +#ifdef CONFIG_MXC_VPU_IRAM +#define VPU_IRAM_SIZE 0x100000 +#else +#define VPU_IRAM_SIZE 0 +#endif + +#define ANADIG_BASE_ADDR 0x40050000 +/* + * Graphics Memory of GPU + */ +/* +#define MVF_IPU_CTRL_BASE_ADDR 0x18000000 +#define MVF_GPU2D_BASE_ADDR 0x20000000 +#define MVF_GPU_BASE_ADDR 0x30000000 +#define MVF_GPU_GMEM_BASE_ADDR 0xF8020000 +#define MVF_GPU_GMEM_SIZE SZ_256K + +#define MVF_DEBUG_BASE_ADDR 0x40000000 +#define MVF_DEBUG_SIZE SZ_1M +#define MVF_ETB_BASE_ADDR (MVF_DEBUG_BASE_ADDR + 0x00001000) +#define MVF_ETM_BASE_ADDR (MVF_DEBUG_BASE_ADDR + 0x00002000) +#define MVF_TPIU_BASE_ADDR (MVF_DEBUG_BASE_ADDR + 0x00003000) +#define MVF_CTI0_BASE_ADDR (MVF_DEBUG_BASE_ADDR + 0x00004000) +#define MVF_CTI1_BASE_ADDR (MVF_DEBUG_BASE_ADDR + 0x00005000) +#define MVF_CTI2_BASE_ADDR (MVF_DEBUG_BASE_ADDR + 0x00006000) +#define MVF_CTI3_BASE_ADDR (MVF_DEBUG_BASE_ADDR + 0x00007000) +#define MVF_CORTEX_DBG_BASE_ADDR (MVF_DEBUG_BASE_ADDR + 0x00008000) +*/ +/* + * SPBA global module enabled #0 + */ +/* +#define MVF_SPBA0_BASE_ADDR 0x50000000 +#define MVF_SPBA0_SIZE SZ_1M + +#define MVF_ESDHC1_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x00004000) +#define MVF_ESDHC2_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x00008000) +#define MVF_UART3_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x0000C000) +#define MVF_ECSPI1_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x00010000) +#define MVF_SSI2_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x00014000) +#define MVF_ESAI_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x00018000) +#define MVF_ESDHC3_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x00020000) +#define MVF_ESDHC4_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x00024000) +#define MVF_SPDIF_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x00028000) +#define MVF_ASRC_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x0002C000) +#define MVF_ATA_DMA_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x00030000) +#define MVF_SLIM_DMA_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x00034000) +#define MVF_HSI2C_DMA_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x00038000) +#define MVF_SPBA_CTRL_BASE_ADDR (MVF_SPBA0_BASE_ADDR + 0x0003C000) +*/ +/* + * AIPS-Lite 0 + */ +#define MVF_AIPS0_BASE_ADDR 0x40000000 +#define MVF_AIPS0_SIZE (0x70000) + + +#define MVF_MSCM_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00001000) +#define MVF_SCUGIC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00002000) +#define MVF_INTD_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00003000) +#define MVF_L2C_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00006000) +#define MVF_NIC0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00008000) +#define MVF_AHBTZASC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00010000) +#define MVF_CSU_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00017000) +#define MVF_DMA0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00018000) +#define MVF_DMA0TCD_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00019000) +#define MVF_SEMA4_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0001D000) +#define MVF_FLEXBUS_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0001E000) +#define MVF_FLEXCAN0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00021000) +#define MVF_DMAMUX0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00024000) +#define MVF_DMAMUX1_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00025000) +#define MVF_UART0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00027000) +#define MVF_UART1_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00028000) +#define MVF_UART2_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00029000) +#define MVF_UART3_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0002A000) + +#define MVF_DSPI0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0002C000) +#define MVF_DSPI1_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0002D000) +#define MVF_SAI0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0002F000) +#define MVF_SAI1_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00030000) +#define MVF_SAI2_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00031000) +#define MVF_SAI3_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00032000) + +#define MVF_CRC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00033000) +#define MVF_USB1_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00034000) +#define MVF_PDB_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00036000) +#define MVF_PIT_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00037000) +#define MVF_FTM0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00038000) +#define MVF_FTM1_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00039000) +#define MVF_ADC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0003B000) +#define MVF_TCON0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0003D000) +#define MVF_WDOG1_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0003E000) +#define MVF_LPTMR_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00040000) +#define MVF_RLE_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00042000) +#define MVF_MLB_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00043000) +#define MVF_QUADSPI0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00044000) +#define MVF_IOMUXC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00048000) +#define MVF_GPIOA_MUX_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00049000) +#define MVF_GPIOB_MUX_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0004A000) +#define MVF_GPIOC_MUX_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0004B000) +#define MVF_GPIOD_MUX_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0004C000) +#define MVF_GPIOE_MUX_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0004D000) +#define MVF_ANATOP_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00050000) +#define MVF_SCSC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00052000) +#define MVF_DCU0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00058000) +#define MVF_ASRC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00060000) +#define MVF_SPDIF_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00061000) +#define MVF_ESAI_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00062000) +#define MVF_ESAIBIFIFO_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00063000) +#define MVF_EWM_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00065000) +#define MVF_I2C0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00066000) +#define MVF_I2C1_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00067000) +#define MVF_WKUP_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006A000) + +#define MVF_CCM_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006B000) +#define MVF_GPC_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006C000) +#define MVF_VREG_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006D000) +#define MVF_SRC_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006E000) +#define MVF_CMU_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006F000) + +#define L2_BASE_ADDR MVF_L2C_BASE_ADDR + +#define MVF_USBC0_CTRL_BASE_ADDR 0x40034800 +#define MVF_USBC1_CTRL_BASE_ADDR 0x400B4800 +#define MVF_USBC0_PHY_BASE_ADDR 0x40034818 +#define MVF_USBC1_PHY_BASE_ADDR 0x400B4818 +#define MVF_USBC0_BASE_ADDR 0x40034000 +#define MVF_USBC1_BASE_ADDR 0x400B4000 +#define MVF_USBPHY0_BASE_ADDR 0x40050800 +#define MVF_USBPHY1_BASE_ADDR 0x40050B00 + +#define MVF_MSCM_INT_ROUTER_BASE (MVF_MSCM_BASE_ADDR + 0x800) + + +/* + * AIPS 1 + */ +#define MVF_AIPS1_BASE_ADDR 0x40080000 +#define MVF_AIPS1_SIZE (0x80000) + +#define MVF_DAP_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x00087000) +#define MVF_DBG_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x00088000) +#define MVF_PMU_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x00089000) +#define MVF_ETM_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x0008C000) + +#define MVF_DMA1_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x00098000) +#define MVF_DMA1TCD_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x00099000) +#define MVF_DMAMUX2_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000A1000) +#define MVF_DMAMUX3_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000A2000) +#define MVF_OTP_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000A5000) +#define MVF_SNVS_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000A7000) +#define MVF_WDOGSNVS_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000A8000) +#define MVF_UART4_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000A9000) +#define MVF_UART5_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000AB000) +#define MVF_DSPI2_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000AC0000) +#define MVF_DSPI3_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000AD0000) + +#define MVF_MMDC_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000AE000) +#define MVF_ESDHC0_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000B1000) +#define MVF_ESDHC1_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000B2000) +#define MVF_OTG1_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000B4000) +#define MVF_FTM2_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000B8000) +#define MVF_FTM3_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000B9000) +#define MVF_ADC1_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000BB000) +#define MVF_TCON1_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000BD000) +#define MVF_SEGLCD_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000BE000) +#define MVF_QUADSPI1_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000C4000) +#define MVF_VADC_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000C7000) +#define MVF_VDEC_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000C8000) +#define MVF_VIU3_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000C9000) +#define MVF_DAC0_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000CC000) +#define MVF_DAC1_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000CD000) +#define MVF_OPENVG_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000CF000) +#define MVF_MAC0_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000D0000) +#define MVF_MAC1_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000D1000) +#define MVF_FLEXCAN1_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000D4000) +#define MVF_DCU1_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000D8000) +#define MVF_NFC_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000E0000) +#define MVF_I2C2_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000E6000) +#define MVF_I2C3_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000E7000) +#define MVF_L2SWITCH_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000E8000) +#define MVF_CAAM_BASE_ADDR (MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000F0000) + +#define MVF_GPIO1_BASE_ADDR (0x400FF000) +#define MVF_GPIO2_BASE_ADDR (0x400FF040) +#define MVF_GPIO3_BASE_ADDR (0x400FF080) +#define MVF_GPIO4_BASE_ADDR (0x400FF0C0) +#define MVF_GPIO5_BASE_ADDR (0x400FF100) + +#define MVF_GPIO1_INT_BASE_ADDR (0x40049000) +#define MVF_GPIO2_INT_BASE_ADDR (0x4004A000) +#define MVF_GPIO3_INT_BASE_ADDR (0x4004B000) +#define MVF_GPIO4_INT_BASE_ADDR (0x4004C000) +#define MVF_GPIO5_INT_BASE_ADDR (0x4004D000) + +#define MVF_FEC_BASE_ADDR MVF_MAC0_BASE_ADDR + +/* + */ +#if 0 + +#define MVF_IO_P2V(x) IMX_IO_P2V(x) +#define MVF_IO_ADDRESS(x) IOMEM(MVF_IO_P2V(x)) +#else +#define PERIPBASE_VIRT 0xF2000000UL +#define MVF_IO_ADDRESS(x) (\ + (x) >= 0x40000000UL ? (void __iomem *)(x - 0x40000000 + SZ_128K \ + + PERIPBASE_VIRT) : (void __iomem *)(x + PERIPBASE_VIRT) \ + ) + +#define IO_ADDRESS(x) MVF_IO_ADDRESS(x) +#endif + +/* GPC */ +#define MVF_GPC_BASE (MVF_IO_ADDRESS(MVF_GPC_BASE_ADDR)) +#define MVF_PGC_IPU_BASE (MVF_GPC_BASE + 0x220) +#define MVF_PGC_VPU_BASE (MVF_GPC_BASE + 0x240) +#define MVF_PGC_GPU_BASE (MVF_GPC_BASE + 0x260) +#define MVF_PGC_IPU_PGCR (MVF_PGC_IPU_BASE + 0x0) +#define MVF_PGC_IPU_PGSR (MVF_PGC_IPU_BASE + 0xC) +#define MVF_PGC_VPU_PGCR (MVF_PGC_VPU_BASE + 0x0) +#define MVF_PGC_VPU_PGSR (MVF_PGC_VPU_BASE + 0xC) +#define MVF_PGC_GPU_PGCR (MVF_PGC_GPU_BASE + 0x0) +#define MVF_PGC_GPU_PGSR (MVF_PGC_GPU_BASE + 0xC) + +/* + * defines for SPBA modules + */ +#define MVF_SPBA_SDHC1 0x04 +#define MVF_SPBA_SDHC2 0x08 +#define MVF_SPBA_UART3 0x0C +#define MVF_SPBA_CSPI1 0x10 +#define MVF_SPBA_SSI2 0x14 +#define MVF_SPBA_SDHC3 0x20 +#define MVF_SPBA_SDHC4 0x24 +#define MVF_SPBA_SPDIF 0x28 +#define MVF_SPBA_ATA 0x30 +#define MVF_SPBA_SLIM 0x34 +#define MVF_SPBA_HSI2C 0x38 +#define MVF_SPBA_CTRL 0x3C + +/* + * DMA request assignments + */ + +/* DMA MUX0,3 request source number */ +#define DMA_MUX03_UART0_RX 2 +#define DMA_MUX03_UART0_TX 3 +#define DMA_MUX03_UART1_RX 4 +#define DMA_MUX03_UART1_TX 5 +#define DMA_MUX03_UART2_RX 6 +#define DMA_MUX03_UART2_TX 7 +#define DMA_MUX03_UART3_RX 8 +#define DMA_MUX03_UART3_TX 9 +#define DMA_MUX03_DSPI0_RX 12 +#define DMA_MUX03_DSPI0_TX 13 +#define DMA_MUX03_DSPI1_RX 14 +#define DMA_MUX03_DSPI1_TX 15 +#define DMA_MUX03_SAI0_RX 16 +#define DMA_MUX03_SAI0_TX 17 +#define DMA_MUX03_SAI1_RX 18 +#define DMA_MUX03_SAI1_TX 19 +#define DMA_MUX03_SAI2_RX 20 +#define DMA_MUX03_SAI2_TX 21 +#define DMA_MUX03_PDB 22 +#define DMA_MUX03_FTM0_CH0 24 +#define DMA_MUX03_FTM0_CH1 25 +#define DMA_MUX03_FTM0_CH2 26 +#define DMA_MUX03_FTM0_CH3 27 +#define DMA_MUX03_FTM0_CH4 28 +#define DMA_MUX03_FTM0_CH5 29 +#define DMA_MUX03_FTM0_CH6 30 +#define DMA_MUX03_FTM0_CH7 31 +#define DMA_MUX03_FTM1_CH0 32 +#define DMA_MUX03_FTM1_CH1 33 +#define DMA_MUX03_ADC0 34 +#define DMA_MUX03_QUADSPI0 36 +#define DMA_MUX03_GPIOA 38 +#define DMA_MUX03_GPIOB 39 +#define DMA_MUX03_GPIOC 40 +#define DMA_MUX03_GPIOD 41 +#define DMA_MUX03_GPIOE 42 +#define DMA_MUX03_RLE_RX 45 +#define DMA_MUX03_RLE_TX 46 +#define DMA_MUX03_SPDIF_RX 47 +#define DMA_MUX03_SPDIF_TX 48 +#define DMA_MUX03_I2C0_RX 50 +#define DMA_MUX03_I2C0_TX 51 +#define DMA_MUX03_I2C1_RX 52 +#define DMA_MUX03_I2C1_TX 53 +#define DMA_MUX03_ALWAYS0 54 +#define DMA_MUX03_ALWAYS1 55 +#define DMA_MUX03_ALWAYS2 56 +#define DMA_MUX03_ALWAYS3 57 +#define DMA_MUX03_ALWAYS4 58 +#define DMA_MUX03_ALWAYS5 59 +#define DMA_MUX03_ALWAYS6 60 +#define DMA_MUX03_ALWAYS7 61 +#define DMA_MUX03_ALWAYS8 62 +#define DMA_MUX03_ALWAYS9 63 + +/* DMA MUX1,2 request source number */ +#define DMA_MUX12_UART4_RX 2 +#define DMA_MUX12_UART4_TX 3 +#define DMA_MUX12_UART5_RX 4 +#define DMA_MUX12_UART5_TX 5 +#define DMA_MUX12_SAI3_RX 8 +#define DMA_MUX12_SAI3_TX 9 +#define DMA_MUX12_DSPI2_RX 10 +#define DMA_MUX12_DSPI2_TX 11 +#define DMA_MUX12_DSPI3_RX 12 +#define DMA_MUX12_DSPI3_TX 13 +#define DMA_MUX12_FTM2_CH0 16 +#define DMA_MUX12_FTM2_CH1 17 +#define DMA_MUX12_FTM3_CH0 18 +#define DMA_MUX12_FTM3_CH1 19 +#define DMA_MUX12_FTM3_CH2 20 +#define DMA_MUX12_FTM3_CH3 21 +#define DMA_MUX12_FTM3_CH4 22 +#define DMA_MUX12_FTM3_CH5 24 +#define DMA_MUX12_FTM3_CH6 25 +#define DMA_MUX12_FTM3_CH7 26 +#define DMA_MUX12_QUADSPI1 27 +#define DMA_MUX12_DAC0 32 +#define DMA_MUX12_DAC1 33 +#define DMA_MUX12_ESAI_BIFIFO_TX 34 +#define DMA_MUX12_ESAI_BIFIFO_RX 35 +#define DMA_MUX12_I2C2_RX 36 +#define DMA_MUX12_I2C2_TX 37 +#define DMA_MUX12_I2C3_RX 38 +#define DMA_MUX12_I2C3_TX 39 +#define DMA_MUX12_ASRC0_TX 40 +#define DMA_MUX12_ASRC0_RX 41 +#define DMA_MUX12_ASRC1_TX 42 +#define DMA_MUX12_ASRC1_RX 43 +#define DMA_MUX12_TIMER0 44 +#define DMA_MUX12_TIMER1 45 +#define DMA_MUX12_TIMER2 46 +#define DMA_MUX12_TIMER3 47 +#define DMA_MUX12_TIMER4 48 +#define DMA_MUX12_TIMER5 49 +#define DMA_MUX12_TIMER6 50 +#define DMA_MUX12_TIMER7 51 +#define DMA_MUX12_ASRC2_TX 52 +#define DMA_MUX12_ASRC2_RX 53 +#define DMA_MUX12_ALWAYS0 54 +#define DMA_MUX12_ALWAYS1 55 +#define DMA_MUX12_ALWAYS2 56 +#define DMA_MUX12_ALWAYS3 57 +#define DMA_MUX12_ALWAYS4 58 +#define DMA_MUX12_ALWAYS5 59 +#define DMA_MUX12_ALWAYS6 60 +#define DMA_MUX12_ALWAYS7 61 +#define DMA_MUX12_ALWAYS8 62 +#define DMA_MUX12_ALWAYS9 63 + + +/* 16 DMA channel per MUX*/ +#define DMAMUX0_CHCFG0 MVF_DMAMUX0_BASE_ADDR +#define DMAMUX0_CHCFG(n) (MVF_DMAMUX0_BASE_ADDR + 8*(n)) +#define DMAMUX1_CHCFG0 MVF_DMAMUX1_BASE_ADDR +#define DMAMUX1_CHCFG(n) (MVF_DMAMUX1_BASE_ADDR + 8*(n)) +#define DMAMUX2_CHCFG0 MVF_DMAMUX2_BASE_ADDR +#define DMAMUX2_CHCFG(n) (MVF_DMAMUX2_BASE_ADDR + 8*(n)) +#define DMAMUX3_CHCFG0 MVF_DMAMUX3_BASE_ADDR +#define DMAMUX3_CHCFG(n) (MVF_DMAMUX3_BASE_ADDR + 8*(n)) + + +/* DMA slot number 53 periph and 10 alway-on source */ +#define MVF_DMA_REQ_SSI3_TX0 47 +#define MVF_DMA_REQ_SSI3_RX0 46 +#define MVF_DMA_REQ_SSI3_TX1 45 +#define MVF_DMA_REQ_SSI3_RX1 44 +#define MVF_DMA_REQ_UART3_TX 43 +#define MVF_DMA_REQ_UART3_RX 42 +#define MVF_DMA_REQ_ESAI_TX 41 +#define MVF_DMA_REQ_ESAI_RX 40 +#define MVF_DMA_REQ_CSPI_TX 39 +#define MVF_DMA_REQ_CSPI_RX 38 +#define MVF_DMA_REQ_ASRC_DMA6 37 +#define MVF_DMA_REQ_ASRC_DMA5 36 +#define MVF_DMA_REQ_ASRC_DMA4 35 +#define MVF_DMA_REQ_ASRC_DMA3 34 +#define MVF_DMA_REQ_ASRC_DMA2 33 +#define MVF_DMA_REQ_ASRC_DMA1 32 +#define MVF_DMA_REQ_EMI_WR 31 +#define MVF_DMA_REQ_EMI_RD 30 +#define MVF_DMA_REQ_SSI1_TX0 29 +#define MVF_DMA_REQ_SSI1_RX0 28 +#define MVF_DMA_REQ_SSI1_TX1 27 +#define MVF_DMA_REQ_SSI1_RX1 26 +#define MVF_DMA_REQ_SSI2_TX0 25 +#define MVF_DMA_REQ_SSI2_RX0 24 +#define MVF_DMA_REQ_SSI2_TX1 23 +#define MVF_DMA_REQ_SSI2_RX1 22 +#define MVF_DMA_REQ_I2C2_SDHC2 21 +#define MVF_DMA_REQ_I2C1_SDHC1 20 +#define MVF_DMA_REQ_UART1_TX 19 +#define MVF_DMA_REQ_UART1_RX 18 +#define MVF_DMA_REQ_UART5_TX 17 +#define MVF_DMA_REQ_UART5_RX 16 +#define MVF_DMA_REQ_SPDIF_TX 15 +#define MVF_DMA_REQ_SPDIF_RX 14 +#define MVF_DMA_REQ_UART2_FIRI_TX 13 +#define MVF_DMA_REQ_UART2_FIRI_RX 12 +#define MVF_DMA_REQ_SDHC4 11 +#define MVF_DMA_REQ_I2C3_SDHC3 10 +#define MVF_DMA_REQ_CSPI2_TX 9 +#define MVF_DMA_REQ_CSPI2_RX 8 +#define MVF_DMA_REQ_CSPI1_TX 7 +#define MVF_DMA_REQ_CSPI1_RX 6 +#define MVF_DMA_REQ_IPU 5 +#define MVF_DMA_REQ_ATA_TX_END 4 +#define MVF_DMA_REQ_ATA_UART4_TX 3 +#define MVF_DMA_REQ_ATA_UART4_RX 2 +#define MVF_DMA_REQ_GPC 1 +#define MVF_DMA_REQ_VPU 0 + +/* + * Interrupt Vector numbers + */ +#define MXC_INT_START 27 +#define MVF_INT_GLOBAL_TIMER 27 +#define MVF_INT_LEGACY_NFIQ 28 +#define MVF_INT_CORE_TIMER 29 +#define MVF_INT_CORE_WDOG1 30 +#define MVF_INT_LEGACY_NIRQ 31 +#define MVF_INT_CPU_INT0 32 +#define MVF_INT_CPU_INT1 33 +#define MVF_INT_CPU_INT2 34 +#define MVF_INT_CPU_INT3 35 +#define MVF_INT_SEMA4 36 +#define MVF_INT_DBG 37 +#define MVF_INT_L2CC 38 +#define MVF_INT_PMU 39 +#define MVF_INT_DMA0_TX 40 +#define MVF_INT_DMA0_ERR 41 +#define MVF_INT_DMA1_TX 42 +#define MVF_INT_DMA1_ERR 43 +#define MVF_INT_MSCM_ECC0 46 +#define MVF_INT_MSCM_ECC1 47 +#define MVF_INT_CSU_ALARM 48 +#define MVF_INT_MSCM_ACTZS 50 +#define MVF_INT_WDOG 52 +#define MVF_INT_WDOG_SNVS 54 +#define MVF_INT_QUADSPI0 56 +#define MVF_INT_QUADSPI1 57 +#define MVF_INT_DDRMC 58 +#define MVF_INT_ESDHC0 59 +#define MVF_INT_ESDHC1 60 +#define MVF_INT_DCU0 62 +#define MVF_INT_DCU1 63 +#define MVF_INT_VIU 64 +#define MVF_INT_GC355 66 +#define MVF_INT_RLE 67 +#define MVF_INT_SEG_LCD 68 +#define MVF_INT_PIT 71 +#define MVF_INT_LPTIMER0 72 +#define MVF_INT_FLEXTIMER0 74 +#define MVF_INT_FLEXTIMER1 75 +#define MVF_INT_FLEXTIMER2 76 +#define MVF_INT_FLEXTIMER3 77 +#define MVF_INT_ANATOP_USBPHY0 82 +#define MVF_INT_ANATOP_USBPHY1 83 +#define MVF_INT_ADC0 85 +#define MVF_INT_ADC1 86 +#define MVF_INT_DAC0 87 +#define MVF_INT_DAC1 88 +#define MVF_INT_CAN0 90 +#define MVF_INT_CAN1 91 +#define MVF_INT_MLB 92 +#define MVF_INT_UART0 93 +#define MVF_INT_UART1 94 +#define MVF_INT_UART2 95 +#define MVF_INT_UART3 96 +#define MVF_INT_UART4 97 +#define MVF_INT_UART5 98 +#define MVF_INT_DSPI0 99 +#define MVF_INT_DSPI1 100 +#define MVF_INT_DSPI2 101 +#define MVF_INT_DSPI3 102 +#define MVF_INT_I2C0 103 +#define MVF_INT_I2C1 104 +#define MVF_INT_I2C2 105 +#define MVF_INT_I2C3 106 +#define MVF_INT_USBOTG0 107 +#define MVF_INT_USB2 108 +#define MVF_INT_ENET_MAC0 110 +#define MVF_INT_ENET_MAC1 111 +#define MVF_INT_1588_TIMER0 112 +#define MVF_INT_1588_TIMER1 113 +#define MVF_INT_ENET_SWITCH 114 +#define MVF_INT_NFC 115 +#define MVF_INT_SAI0 116 +#define MVF_INT_SAI1 117 +#define MVF_INT_SAI2 118 +#define MVF_INT_SAI3 119 +#define MVF_INT_ESAI_BIFIFO 120 +#define MVF_INT_SPDIF 121 +#define MVF_INT_ASRC 122 +#define MVF_INT_CMU 123 +#define MVF_INT_WKPU0 124 +#define MVF_INT_WKPU1 125 +#define MVF_INT_CCM 126 + +#define MVF_INT_SRC 128 +#define MVF_INT_PDB 129 +#define MVF_INT_EWM 130 +#define MVF_INT_SNVS 132 + +#define MVF_INT_CAAM 134 + +#define MVF_INT_GPIO0 139 +#define MVF_INT_GPIO1 140 +#define MVF_INT_GPIO2 141 +#define MVF_INT_GPIO3 142 +#define MVF_INT_GPIO4 143 +#define MXC_INT_END 143 + +#define MVF_INT_FEC MVF_INT_ENET_MAC0 + +/* silicon revisions specific to i.MVF */ +#define MVF_CHIP_REV_1_0 0x10 +#define MVF_CHIP_REV_1_1 0x11 +#define MVF_CHIP_REV_1_2 0x12 +#define MVF_CHIP_REV_1_3 0x13 +#define MVF_CHIP_REV_2_0 0x20 +#define MVF_CHIP_REV_2_1 0x21 +#define MVF_CHIP_REV_2_2 0x22 +#define MVF_CHIP_REV_2_3 0x23 +#define MVF_CHIP_REV_3_0 0x30 +#define MVF_CHIP_REV_3_1 0x31 +#define MVF_CHIP_REV_3_2 0x32 + +/*! + * IIM bank info + */ +#define MXC_IIM_MX51_BANK_START_ADDR 0x0800 +#define MXC_IIM_MX51_BANK_END_ADDR 0x147c +#define MXC_IIM_MVF_BANK_START_ADDR 0x0800 +#define MXC_IIM_MVF_BANK_END_ADDR 0x183c +#define MXC_IIM_MVF_BANK_AREA_1_OFFSET 0xc00 +#define MXC_IIM_MVF_MAC_ADDR_OFFSET 0x24 + +#endif /* ifndef __MACH_MVF_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index c8f18052c6af..afcf1255150b 100755 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -38,6 +38,7 @@ #define MXC_CPU_MX53 53 #define MXC_CPU_MX6Q 63 #define MXC_CPU_MX6DL 61 +#define MXC_CPU_MVF 54 #define IMX_CHIP_REVISION_1_0 0x10 #define IMX_CHIP_REVISION_1_1 0x11 @@ -229,6 +230,13 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx6dl() (0) #endif +#ifdef CONFIG_SOC_MVFA5 +# define mxc_cpu_type __mxc_cpu_type +# define cpu_is_mvf() (mxc_cpu_type == MXC_CPU_MVF) +#else +# define cpu_is_mvf() (0) +#endif + #ifndef __ASSEMBLY__ #ifdef CONFIG_SOC_IMX6Q extern int mx6q_revision(void); diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 695063bd7214..b048a714adef 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -1,6 +1,6 @@ /* * Copyright (C) 1999 ARM Limited - * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. + * Copyright 2004-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,6 +28,8 @@ #define CLOCK_TICK_RATE 8000000 #elif defined CONFIG_ARCH_MX6 #define CLOCK_TICK_RATE 8000000 +#elif defined CONFIG_ARCH_MVF +#define CLOCK_TICK_RATE 66000000 #endif #endif /* __ASM_ARCH_MXC_TIMEX_H__ */ diff --git a/arch/arm/plat-mxc/pit.c b/arch/arm/plat-mxc/pit.c new file mode 100644 index 000000000000..1d13a2817bbb --- /dev/null +++ b/arch/arm/plat-mxc/pit.c @@ -0,0 +1,259 @@ +/* + * linux/arch/arm/plat-mxc/pit.c + * + * Copyright 2012 Freescale Semiconductor, Inc. + * based on linux/arch/arm/plat-mxc/epit.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#include + +static unsigned long pit_cnt; + +#define PITMCR 0x00 +#define PITLTMR64H 0xE0 +#define PITLTMR64L 0xE4 + +#define PITOFFSET 0x120 +#define PITLDVAL 0x00 +#define PITCVAL 0x04 +#define PITTCTRL 0x08 +#define PITTFLG 0x0C + +/* + * Total 8 pit timer, each memory map occupy 0x10 Bytes + * get base offset for pit(n) + */ +#define PITOFFSETx(n) (PITOFFSET + 0x10*n) + +/* bit definitation */ +#define PITMCR_MDIS (1 << 1) +#define PITMCR_FRZ (1 << 0) + +#define PITTCTRL_TEN (1 << 0) +#define PITTCTRL_TIE (1 << 1) +#define PITCTRL_CHN (1 << 2) + +#define PITTFLG_TIF (1 << 0) + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct clock_event_device clockevent_pit; +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; + +static void __iomem *timer_base; +static unsigned long pit_cycle_per_jiffy; + +static inline void pit_irq_disable(void) +{ + u32 val; + + val = __raw_readl(timer_base + PITOFFSET + PITTCTRL); + val &= ~PITTCTRL_TIE; + __raw_writel(val, timer_base + PITOFFSET + PITTCTRL); +} + +static inline void pit_irq_enable(void) +{ + u32 val; + + val = __raw_readl(timer_base + PITOFFSET + PITTCTRL); + val |= PITTCTRL_TIE; + __raw_writel(val, timer_base + PITOFFSET + PITTCTRL); +} + +static void pit_irq_acknowledge(void) +{ + __raw_writel(PITTFLG_TIF, timer_base + PITOFFSET + PITTFLG); +} + +static cycle_t pit_read_clk(struct clocksource *cs); + +static DEFINE_CLOCK_DATA(cd); +static void __iomem *sched_clock_reg; + +static void notrace mvf_update_sched_clock(void) +{ + cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; + update_sched_clock(&cd, cyc, (u32)~0); +} +static int __init pit_clocksource_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + void __iomem *reg = timer_base + PITOFFSET + PITCVAL; + + sched_clock_reg = reg; + + init_sched_clock(&cd, mvf_update_sched_clock, 32, c); + return clocksource_mmio_init(timer_base + PITOFFSET + PITCVAL, "pit", + c, 0, 32, + pit_read_clk/*clocksource_mmio_readl_down*/); +} + +/* clock event */ + +static int pit_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + return 0; +} + +static void pit_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned long flags; + + /* + * The timer interrupt generation is disabled at least + * for enough time to call epit_set_next_event() + */ + local_irq_save(flags); + + /* Disable interrupt in PIT module */ + pit_irq_disable(); + + if (mode != clockevent_mode) { + /* Set event time into far-far future */ + + /* Clear pending interrupt */ + pit_irq_acknowledge(); + } + + /* Remember timer mode */ + clockevent_mode = mode; + local_irq_restore(flags); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + + __raw_writel(0, timer_base + PITOFFSET + PITTCTRL); + __raw_writel(pit_cycle_per_jiffy, + timer_base + PITOFFSET + PITLDVAL); + __raw_writel(PITTCTRL_TEN, timer_base + PITOFFSET + PITTCTRL); + + pit_irq_enable(); + + break; + case CLOCK_EVT_MODE_ONESHOT: + /* + * Do not put overhead of interrupt enable/disable into + * epit_set_next_event(), the core has about 4 minutes + * to call epit_set_next_event() or shutdown clock after + * mode switching + */ + local_irq_save(flags); + pit_irq_enable(); + local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appear */ + break; + } +} + +/* + * IRQ handler for the timer + */ +static irqreturn_t pit_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_pit; + + pit_irq_acknowledge(); + + pit_cnt += pit_cycle_per_jiffy; + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static cycle_t pit_read_clk(struct clocksource *cs) +{ + unsigned long flags; + u32 cycles; + u16 pcntr; + + local_irq_save(flags); + pcntr = __raw_readl(timer_base + PITOFFSET + PITCVAL); + cycles = pit_cnt; + local_irq_restore(flags); + + return cycles + pit_cycle_per_jiffy - pcntr; +} + + +static struct irqaction pit_timer_irq = { + .name = "MVF PIT Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = pit_timer_interrupt, +}; + +static struct clock_event_device clockevent_pit = { + .name = "pit", + .features = CLOCK_EVT_FEAT_PERIODIC, + .shift = 32, + .set_mode = pit_set_mode, + .set_next_event = pit_set_next_event, + .rating = 100, +}; + +static int __init pit_clockevent_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + clockevent_pit.mult = div_sc(c, NSEC_PER_SEC, + clockevent_pit.shift); + clockevent_pit.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &clockevent_pit); + clockevent_pit.min_delta_ns = + clockevent_delta2ns(0x800, &clockevent_pit); + clockevent_pit.cpumask = cpumask_of(0); + clockevents_register_device(&clockevent_pit); + + return 0; +} + +void __init pit_timer_init(struct clk *timer_clk, void __iomem *base, int irq) +{ + + timer_base = base; + + pit_cycle_per_jiffy = clk_get_rate(timer_clk)/(HZ); + + /* + * Initialise to a known state (all timers off, and timing reset) + */ + __raw_writel(0x0, timer_base + PITMCR); + + __raw_writel(0xffffffff, timer_base + PITOFFSET + PITLDVAL); + __raw_writel(PITTCTRL_TEN, timer_base + PITOFFSET + PITTCTRL); + + /* init and register the timer to the framework */ + pit_clocksource_init(timer_clk); + + pit_clockevent_init(timer_clk); + + /* Make irqs happen */ + setup_irq(irq, &pit_timer_irq); +} -- cgit v1.2.3