From 1a0e8a52ad56075663d8e120e2468fc96fb6fa6c Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 14 Jan 2010 08:13:37 +0900 Subject: ARM: S5P6440: Add Clock and PLL support This patch adds clock and pll support for S5P6440. This patch are based on Harald Welte's patches and Ben's plat-samsung. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/plat-s5p/clock.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 arch/arm/plat-s5p/clock.c (limited to 'arch/arm/plat-s5p/clock.c') diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c new file mode 100644 index 000000000000..3d3c0f1934fc --- /dev/null +++ b/arch/arm/plat-s5p/clock.c @@ -0,0 +1,136 @@ +/* linux/arch/arm/plat-s5p/clock.c + * + * Copyright 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P - Common clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call + * clk_ext_xtal_mux. +*/ +struct clk clk_ext_xtal_mux = { + .name = "ext_xtal", + .id = -1, +}; + +/* 48MHz USB Phy clock output */ +struct clk clk_48m = { + .name = "clk_48m", + .id = -1, + .rate = 48000000, +}; + +/* APLL clock output + * No need .ctrlbit, this is always on +*/ +struct clk clk_fout_apll = { + .name = "fout_apll", + .id = -1, +}; + +/* MPLL clock output + * No need .ctrlbit, this is always on +*/ +struct clk clk_fout_mpll = { + .name = "fout_mpll", + .id = -1, +}; + +/* EPLL clock output */ +struct clk clk_fout_epll = { + .name = "fout_epll", + .id = -1, + .ctrlbit = (1 << 31), +}; + +/* ARM clock */ +struct clk clk_arm = { + .name = "armclk", + .id = -1, + .rate = 0, + .ctrlbit = 0, +}; + +/* Possible clock sources for APLL Mux */ +static struct clk *clk_src_apll_list[] = { + [0] = &clk_fin_apll, + [1] = &clk_fout_apll, +}; + +struct clksrc_sources clk_src_apll = { + .sources = clk_src_apll_list, + .nr_sources = ARRAY_SIZE(clk_src_apll_list), +}; + +/* Possible clock sources for MPLL Mux */ +static struct clk *clk_src_mpll_list[] = { + [0] = &clk_fin_mpll, + [1] = &clk_fout_mpll, +}; + +struct clksrc_sources clk_src_mpll = { + .sources = clk_src_mpll_list, + .nr_sources = ARRAY_SIZE(clk_src_mpll_list), +}; + +/* Possible clock sources for EPLL Mux */ +static struct clk *clk_src_epll_list[] = { + [0] = &clk_fin_epll, + [1] = &clk_fout_epll, +}; + +struct clksrc_sources clk_src_epll = { + .sources = clk_src_epll_list, + .nr_sources = ARRAY_SIZE(clk_src_epll_list), +}; + +int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable) +{ + unsigned int ctrlbit = clk->ctrlbit; + u32 con; + + con = __raw_readl(reg); + con = enable ? (con | ctrlbit) : (con & ~ctrlbit); + __raw_writel(con, reg); + return 0; +} + +static struct clk *s5p_clks[] __initdata = { + &clk_ext_xtal_mux, + &clk_48m, + &clk_fout_apll, + &clk_fout_mpll, + &clk_fout_epll, + &clk_arm, +}; + +void __init s5p_register_clocks(unsigned long xtal_freq) +{ + int ret; + + clk_ext_xtal_mux.rate = xtal_freq; + + ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks)); + if (ret > 0) + printk(KERN_ERR "Failed to register s5p clocks\n"); +} -- cgit v1.2.3 From 0c1945d336116e82454b5461238618ef81696669 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Wed, 24 Feb 2010 16:40:36 +0900 Subject: ARM: S5PV210: Add clock support for S5PV210 This patch adds clock support for S5PV210. This patch adds the clock register definitions and the various system clocks in S5PV210. Clocks that are common to other S5P SoC'c are added in the common S5P clock support. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/plat-s5p/clock.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/plat-s5p/clock.c') diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c index 3d3c0f1934fc..aa96e335073b 100644 --- a/arch/arm/plat-s5p/clock.c +++ b/arch/arm/plat-s5p/clock.c @@ -33,6 +33,12 @@ struct clk clk_ext_xtal_mux = { .id = -1, }; +static struct clk s5p_clk_27m = { + .name = "clk_27m", + .id = -1, + .rate = 27000000, +}; + /* 48MHz USB Phy clock output */ struct clk clk_48m = { .name = "clk_48m", @@ -104,6 +110,11 @@ struct clksrc_sources clk_src_epll = { .nr_sources = ARRAY_SIZE(clk_src_epll_list), }; +struct clk clk_vpll = { + .name = "vpll", + .id = -1, +}; + int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable) { unsigned int ctrlbit = clk->ctrlbit; @@ -118,10 +129,12 @@ int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable) static struct clk *s5p_clks[] __initdata = { &clk_ext_xtal_mux, &clk_48m, + &s5p_clk_27m, &clk_fout_apll, &clk_fout_mpll, &clk_fout_epll, &clk_arm, + &clk_vpll, }; void __init s5p_register_clocks(unsigned long xtal_freq) -- cgit v1.2.3