From 1d826d14cc2783d0c09750c2e1eeb2bdd358769b Mon Sep 17 00:00:00 2001 From: Jaecheol Lee Date: Wed, 15 Sep 2010 15:57:37 +0900 Subject: ARM: S5PV210: Add DMC map_desc table for supporting DMC access This patch adds DMC(DRAM Memory Controller) map_desc table. Because some driver such as CPUFREQ need to access DMC register. Signed-off-by: Jaecheol Lee Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/include/plat/map-s5p.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/plat-s5p/include/plat') diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index c4ff88bf6477..24728947682d 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -18,6 +18,8 @@ #define S5P_VA_SYSTIMER S3C_ADDR(0x01200000) #define S5P_VA_SROMC S3C_ADDR(0x01100000) #define S5P_VA_SYSRAM S3C_ADDR(0x01180000) +#define S5P_VA_DMC0 S3C_ADDR(0x00A00000) +#define S5P_VA_DMC1 S3C_ADDR(0x00A80000) #define S5P_VA_COMBINER_BASE S3C_ADDR(0x00600000) #define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10) -- cgit v1.2.3 From ca1931ca1e87c32f9abaef378c6996b25774cb02 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 29 Sep 2010 22:10:51 +0900 Subject: ARM: S5PV210: Enable USB HSOTG gadget build Add the necessary definitions and mapping information to enable the s3c-hsotg gadget to build. Signed-off-by: Marek Szyprowski Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/include/plat/map-s5p.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/plat-s5p/include/plat') diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index 24728947682d..c833f3f21816 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -18,6 +18,7 @@ #define S5P_VA_SYSTIMER S3C_ADDR(0x01200000) #define S5P_VA_SROMC S3C_ADDR(0x01100000) #define S5P_VA_SYSRAM S3C_ADDR(0x01180000) +#define S3C_VA_USB_HSPHY S3C_ADDR(0x02000000) #define S5P_VA_DMC0 S3C_ADDR(0x00A00000) #define S5P_VA_DMC1 S3C_ADDR(0x00A80000) -- cgit v1.2.3 From 170a46177094b390299d1206748d7f15cd375dc9 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 1 Oct 2010 10:40:37 +0900 Subject: ARM: S5P: Add common S5P GPIO Interrupt support This patch adds common code to enable support of GPIO interrupt on S5P SoCs. The total number of GPIO pins is quite large on S5P SoCs. Registering irq support for all of them would be a resource waste. Because of that the interrupt support for standard GPIO pins is registered dynamically by the s5p_register_gpio_interrupt() function. Signed-off-by: Marek Szyprowski Signed-off-by: Joonyoung Shim Signed-off-by: Kyungmin Park [kgene.kim@samsung.com: minor title fixes] Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/include/plat/irqs.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/plat-s5p/include/plat') diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h index 3fb3a3a17465..23603c7f1943 100644 --- a/arch/arm/plat-s5p/include/plat/irqs.h +++ b/arch/arm/plat-s5p/include/plat/irqs.h @@ -94,4 +94,13 @@ ((irq) - S5P_EINT_BASE1) : \ ((irq) + 16 - S5P_EINT_BASE2)) +/* Typically only a few gpio chips require gpio interrupt support. + To avoid memory waste irq descriptors are allocated only for + S5P_GPIOINT_GROUP_COUNT chips, each with total number of + S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged + to any gpio chip with the s5p_register_gpio_interrupt() function */ +#define S5P_GPIOINT_GROUP_COUNT 4 +#define S5P_GPIOINT_GROUP_SIZE 8 +#define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE) + #endif /* __ASM_PLAT_S5P_IRQS_H */ -- cgit v1.2.3 From 9adf5d222cfbbc4b7e972bfe3472368f9b453091 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Sat, 2 Oct 2010 11:48:09 +0900 Subject: ARM: S5P: Unify defines for both gpio interrupt types Samsung S5P SoCs have the same interrupt type defines for both external interrupts and gpio interrupts. This patch removes all duplicates from S5PC100 and S5PV210 specific includes as well as gpio interrupt code and put a common defines to plat/irqs.h NOTE: Do not use this for S5P6440 and S5P6450. Signed-off-by: Marek Szyprowski Signed-off-by: Kyungmin Park [kgene.kim@samsung.com: add note for S5P64X0] Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/include/plat/irqs.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/plat-s5p/include/plat') diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h index 23603c7f1943..7f653bce3c13 100644 --- a/arch/arm/plat-s5p/include/plat/irqs.h +++ b/arch/arm/plat-s5p/include/plat/irqs.h @@ -103,4 +103,11 @@ #define S5P_GPIOINT_GROUP_SIZE 8 #define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE) +/* IRQ types common for all s5p platforms */ +#define S5P_IRQ_TYPE_LEVEL_LOW (0x00) +#define S5P_IRQ_TYPE_LEVEL_HIGH (0x01) +#define S5P_IRQ_TYPE_EDGE_FALLING (0x02) +#define S5P_IRQ_TYPE_EDGE_RISING (0x03) +#define S5P_IRQ_TYPE_EDGE_BOTH (0x04) + #endif /* __ASM_PLAT_S5P_IRQS_H */ -- cgit v1.2.3 From dc6c0ca39daad44f3169656296ef81d39a6dc7f5 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 14 Oct 2010 15:35:07 +0900 Subject: ARM: S5P: Fix missed IRQ_EINT_BIT() When merged patches, missed IRQ_EINT_BIT() definition from commit ea31fd43 (ARM: S5PV210: Add Power Management Support). The IRQ_EINT_BIT() is used in the Power Management operation (plat-samsung/pm.c). Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/include/plat/irqs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/plat-s5p/include/plat') diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h index 7f653bce3c13..ba9121c60a2a 100644 --- a/arch/arm/plat-s5p/include/plat/irqs.h +++ b/arch/arm/plat-s5p/include/plat/irqs.h @@ -94,6 +94,8 @@ ((irq) - S5P_EINT_BASE1) : \ ((irq) + 16 - S5P_EINT_BASE2)) +#define IRQ_EINT_BIT(x) EINT_OFFSET(x) + /* Typically only a few gpio chips require gpio interrupt support. To avoid memory waste irq descriptors are allocated only for S5P_GPIOINT_GROUP_COUNT chips, each with total number of -- cgit v1.2.3 From dd56d2df56485553f4777f68e0ead87fbb02f706 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Tue, 5 Oct 2010 10:49:38 +0900 Subject: ARM: S5P: Cleanup the S5P SoCs' VA address mapping Basically S5P SoCs use the Samsung common VA address mapping where plat-samsung and use plat-s5p's mapping also. The later is a little mess. So this patch cleans it up. Cc: Ben Dooks Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/include/plat/map-s5p.h | 40 +++++++++++++++++--------------- 1 file changed, 21 insertions(+), 19 deletions(-) (limited to 'arch/arm/plat-s5p/include/plat') diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index c833f3f21816..ec96a193f5e1 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -13,27 +13,35 @@ #ifndef __ASM_PLAT_MAP_S5P_H #define __ASM_PLAT_MAP_S5P_H __FILE__ -#define S5P_VA_CHIPID S3C_ADDR(0x00700000) -#define S5P_VA_GPIO S3C_ADDR(0x00500000) -#define S5P_VA_SYSTIMER S3C_ADDR(0x01200000) -#define S5P_VA_SROMC S3C_ADDR(0x01100000) -#define S5P_VA_SYSRAM S3C_ADDR(0x01180000) -#define S3C_VA_USB_HSPHY S3C_ADDR(0x02000000) -#define S5P_VA_DMC0 S3C_ADDR(0x00A00000) -#define S5P_VA_DMC1 S3C_ADDR(0x00A80000) - -#define S5P_VA_COMBINER_BASE S3C_ADDR(0x00600000) +#define S5P_VA_CHIPID S3C_ADDR(0x02000000) +#define S5P_VA_CMU S3C_ADDR(0x02100000) +#define S5P_VA_GPIO S3C_ADDR(0x02200000) + +#define S5P_VA_SYSRAM S3C_ADDR(0x02400000) +#define S5P_VA_DMC0 S3C_ADDR(0x02440000) +#define S5P_VA_DMC1 S3C_ADDR(0x02480000) +#define S5P_VA_SROMC S3C_ADDR(0x024C0000) + +#define S5P_VA_SYSTIMER S3C_ADDR(0x02500000) +#define S5P_VA_L2CC S3C_ADDR(0x02600000) + +#define S5P_VA_COMBINER_BASE S3C_ADDR(0x02700000) #define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10) -#define S5P_VA_COREPERI_BASE S3C_ADDR(0x00800000) +#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000) #define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x)) #define S5P_VA_SCU S5P_VA_COREPERI(0x0) #define S5P_VA_GIC_CPU S5P_VA_COREPERI(0x100) #define S5P_VA_TWD S5P_VA_COREPERI(0x600) #define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000) -#define S5P_VA_L2CC S3C_ADDR(0x00900000) -#define S5P_VA_CMU S3C_ADDR(0x00920000) +#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000) + +#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) +#define VA_VIC0 VA_VIC(0) +#define VA_VIC1 VA_VIC(1) +#define VA_VIC2 VA_VIC(2) +#define VA_VIC3 VA_VIC(3) #define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) #define S5P_VA_UART0 S5P_VA_UART(0) @@ -45,10 +53,4 @@ #define S3C_UART_OFFSET (0x400) #endif -#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) -#define VA_VIC0 VA_VIC(0) -#define VA_VIC1 VA_VIC(1) -#define VA_VIC2 VA_VIC(2) -#define VA_VIC3 VA_VIC(3) - #endif /* __ASM_PLAT_MAP_S5P_H */ -- cgit v1.2.3 From d4b34c6c849d67b7afaa90d55dc7fab981c72950 Mon Sep 17 00:00:00 2001 From: Seungwhan Youn Date: Thu, 14 Oct 2010 10:39:08 +0900 Subject: ARM: S5P: Reduce duplicated EPLL control codes S5P Samsung SoCs has a EPLL to support various PLL clock sources for other H/W blocks. Until now, to control EPLL, each of SoCs make their own functions in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and 'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move these duplicated codes to common EPLL functions that use platform wide. Signed-off-by: Seungwhan Youn Acked-by: Jassi Brar Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/include/plat/s5p-clock.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/plat-s5p/include/plat') diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h index 17036c898409..2b6dcff8ab2b 100644 --- a/arch/arm/plat-s5p/include/plat/s5p-clock.h +++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h @@ -43,4 +43,8 @@ extern struct clksrc_sources clk_src_dpll; extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); +/* Common EPLL operations for S5P platform */ +extern int s5p_epll_enable(struct clk *clk, int enable); +extern unsigned long s5p_epll_get_rate(struct clk *clk); + #endif /* __ASM_PLAT_S5P_CLOCK_H */ -- cgit v1.2.3 From 37ea63b14bec667957ca3cfaa899c6e103fdb854 Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Thu, 14 Oct 2010 15:46:18 +0900 Subject: ARM: S5P: Add initial map for GPIO2 and GPIO3 This patch adds initial map for GPIO2 and GPIO3. S5PV310/S5PC210 has separated GPIO1, GPIO2 and GPIO3. Signed-off-by: Jongpill Lee Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/include/plat/map-s5p.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/plat-s5p/include/plat') diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index ec96a193f5e1..fef353d44513 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -16,6 +16,9 @@ #define S5P_VA_CHIPID S3C_ADDR(0x02000000) #define S5P_VA_CMU S3C_ADDR(0x02100000) #define S5P_VA_GPIO S3C_ADDR(0x02200000) +#define S5P_VA_GPIO1 S5P_VA_GPIO +#define S5P_VA_GPIO2 S3C_ADDR(0x02240000) +#define S5P_VA_GPIO3 S3C_ADDR(0x02280000) #define S5P_VA_SYSRAM S3C_ADDR(0x02400000) #define S5P_VA_DMC0 S3C_ADDR(0x02440000) -- cgit v1.2.3