From 8cf460a5d7c12e16ba29d0e4940df4657a7439cc Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Mon, 15 Nov 2010 09:18:57 +0900 Subject: ARM: S5P: Move the SROM register definitions to plat-s5p The SROM register difinitions of S5PV310/S5PC210 (mach/regs-srom.h) can be used to other S5P SoCs such as S5PV210/S5PC110. So moved into plat/regs-srom.h of plat-s5p directory. Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/include/plat/regs-srom.h | 50 ++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 arch/arm/plat-s5p/include/plat/regs-srom.h (limited to 'arch/arm/plat-s5p') diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-s5p/include/plat/regs-srom.h new file mode 100644 index 000000000000..0fdac48a5985 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-srom.h @@ -0,0 +1,50 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-srom.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5P SROMC register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_REGS_SROM_H +#define __ASM_PLAT_S5P_REGS_SROM_H __FILE__ + +#include + +#define S5P_SROMREG(x) (S5P_VA_SROMC + (x)) + +#define S5P_SROM_BW S5P_SROMREG(0x0) +#define S5P_SROM_BC0 S5P_SROMREG(0x4) +#define S5P_SROM_BC1 S5P_SROMREG(0x8) +#define S5P_SROM_BC2 S5P_SROMREG(0xc) +#define S5P_SROM_BC3 S5P_SROMREG(0x10) + +/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ + +#define S5P_SROM_BW__DATAWIDTH__SHIFT 0 +#define S5P_SROM_BW__ADDRMODE__SHIFT 1 +#define S5P_SROM_BW__WAITENABLE__SHIFT 2 +#define S5P_SROM_BW__BYTEENABLE__SHIFT 3 + +#define S5P_SROM_BW__CS_MASK 0xf + +#define S5P_SROM_BW__NCS0__SHIFT 0 +#define S5P_SROM_BW__NCS1__SHIFT 4 +#define S5P_SROM_BW__NCS2__SHIFT 8 +#define S5P_SROM_BW__NCS3__SHIFT 12 + +/* applies to same to BCS0 - BCS3 */ + +#define S5P_SROM_BCX__PMC__SHIFT 0 +#define S5P_SROM_BCX__TACP__SHIFT 4 +#define S5P_SROM_BCX__TCAH__SHIFT 8 +#define S5P_SROM_BCX__TCOH__SHIFT 12 +#define S5P_SROM_BCX__TACC__SHIFT 16 +#define S5P_SROM_BCX__TCOS__SHIFT 24 +#define S5P_SROM_BCX__TACS__SHIFT 28 + +#endif /* __ASM_PLAT_S5P_REGS_SROM_H */ -- cgit v1.2.3 From abc6c3602200a3b9268c9edece6ba2e85be7b2c4 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Mon, 15 Nov 2010 09:24:49 +0900 Subject: ARM: S5P: Add SROM control register shift macros for other banks. This patch adds shift macros for the SROM Bus width and control register to represent the shift count for the 5th and 6th SROM banks. Some of the S5P SOCs have them. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/include/plat/regs-srom.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/plat-s5p') diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-s5p/include/plat/regs-srom.h index 0fdac48a5985..06189dac87bc 100644 --- a/arch/arm/plat-s5p/include/plat/regs-srom.h +++ b/arch/arm/plat-s5p/include/plat/regs-srom.h @@ -36,6 +36,8 @@ #define S5P_SROM_BW__NCS1__SHIFT 4 #define S5P_SROM_BW__NCS2__SHIFT 8 #define S5P_SROM_BW__NCS3__SHIFT 12 +#define S5P_SROM_BW__NCS4__SHIFT 16 +#define S5P_SROM_BW__NCS5__SHIFT 20 /* applies to same to BCS0 - BCS3 */ -- cgit v1.2.3 From 8233ab6aecf8c103504c3c3b1b055b2d9806fa3e Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Wed, 1 Dec 2010 18:02:30 +0530 Subject: ARM: S5P: Add SROM bank 4 and 5 register offsets Some of the S5P platforms like S5PC100 and S5PV210 include SROM banks 4 and 5 in addition to SROM banks 0 to 3. This patch adds register offsets for SROM bank 4 and 5. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/include/plat/regs-srom.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/plat-s5p') diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-s5p/include/plat/regs-srom.h index 06189dac87bc..f121ab5e76cb 100644 --- a/arch/arm/plat-s5p/include/plat/regs-srom.h +++ b/arch/arm/plat-s5p/include/plat/regs-srom.h @@ -22,6 +22,8 @@ #define S5P_SROM_BC1 S5P_SROMREG(0x8) #define S5P_SROM_BC2 S5P_SROMREG(0xc) #define S5P_SROM_BC3 S5P_SROMREG(0x10) +#define S5P_SROM_BC4 S5P_SROMREG(0x14) +#define S5P_SROM_BC5 S5P_SROMREG(0x18) /* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ -- cgit v1.2.3 From be297f0374d8609ccb8be805bd6de7adc90abea5 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 2 Dec 2010 18:06:50 +0900 Subject: ARM: S5P: Move SROM controller IO mapping to plat-s5p for S5P SoCs This patch modifies the following. 1. Moves the SROM controller mapping from S5PV210 specific code to S5P common code. The SROM controller mapping can be used for all S5P SoCs. 2. Define the SROM controller physical address for S5P64X0, S5P6442, S5PC100, S5PV210 and S5PV310. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/plat-s5p') diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index 74f7f5a5446c..047d31c1bbd8 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -108,6 +108,11 @@ static struct map_desc s5p_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C_PA_WDT), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SROMC, + .pfn = __phys_to_pfn(S5P_PA_SROMC), + .length = SZ_4K, + .type = MT_DEVICE, }, }; -- cgit v1.2.3 From 3bbef1b912df64a86a86e402d7686a8ed38abaf4 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Fri, 17 Dec 2010 15:08:07 +0900 Subject: ARM: S5P: Add platform support for MIPI CSIS devices There may be up to two MIPI CSI slave interfaces depending on the SoC version. Signed-off-by: Sylwester Nawrocki Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/Kconfig | 10 ++++++++++ arch/arm/plat-s5p/Makefile | 2 ++ arch/arm/plat-s5p/dev-csis0.c | 34 ++++++++++++++++++++++++++++++++++ arch/arm/plat-s5p/dev-csis1.c | 34 ++++++++++++++++++++++++++++++++++ arch/arm/plat-s5p/include/plat/csis.h | 28 ++++++++++++++++++++++++++++ 5 files changed, 108 insertions(+) create mode 100644 arch/arm/plat-s5p/dev-csis0.c create mode 100644 arch/arm/plat-s5p/dev-csis1.c create mode 100644 arch/arm/plat-s5p/include/plat/csis.h (limited to 'arch/arm/plat-s5p') diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 65dbfa8e0a86..6a161f317a79 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -56,3 +56,13 @@ config S5P_DEV_ONENAND bool help Compile in platform device definition for OneNAND controller + +config S5P_DEV_CSIS0 + bool + help + Compile in platform device definitions for MIPI-CSIS channel 0 + +config S5P_DEV_CSIS1 + bool + help + Compile in platform device definitions for MIPI-CSIS channel 1 diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index de65238a7aef..2b7317378103 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -28,3 +28,5 @@ obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o +obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o +obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o diff --git a/arch/arm/plat-s5p/dev-csis0.c b/arch/arm/plat-s5p/dev-csis0.c new file mode 100644 index 000000000000..dfab1c85f54f --- /dev/null +++ b/arch/arm/plat-s5p/dev-csis0.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * + * S5P series device definition for MIPI-CSIS channel 0 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +static struct resource s5p_mipi_csis0_resource[] = { + [0] = { + .start = S5P_PA_MIPI_CSIS0, + .end = S5P_PA_MIPI_CSIS0 + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MIPI_CSIS0, + .end = IRQ_MIPI_CSIS0, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device s5p_device_mipi_csis0 = { + .name = "s5p-mipi-csis", + .id = 0, + .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource), + .resource = s5p_mipi_csis0_resource, +}; diff --git a/arch/arm/plat-s5p/dev-csis1.c b/arch/arm/plat-s5p/dev-csis1.c new file mode 100644 index 000000000000..e3053f27fbbf --- /dev/null +++ b/arch/arm/plat-s5p/dev-csis1.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * + * S5P series device definition for MIPI-CSIS channel 1 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +static struct resource s5p_mipi_csis1_resource[] = { + [0] = { + .start = S5P_PA_MIPI_CSIS1, + .end = S5P_PA_MIPI_CSIS1 + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MIPI_CSIS1, + .end = IRQ_MIPI_CSIS1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s5p_device_mipi_csis1 = { + .name = "s5p-mipi-csis", + .id = 1, + .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource), + .resource = s5p_mipi_csis1_resource, +}; diff --git a/arch/arm/plat-s5p/include/plat/csis.h b/arch/arm/plat-s5p/include/plat/csis.h new file mode 100644 index 000000000000..51e308c7981d --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/csis.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * + * S5P series MIPI CSI slave device support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef PLAT_S5P_CSIS_H_ +#define PLAT_S5P_CSIS_H_ __FILE__ + +/** + * struct s5p_platform_mipi_csis - platform data for MIPI-CSIS + * @clk_rate: bus clock frequency + * @lanes: number of data lanes used + * @alignment: data alignment in bits + * @hs_settle: HS-RX settle time + */ +struct s5p_platform_mipi_csis { + unsigned long clk_rate; + u8 lanes; + u8 alignment; + u8 hs_settle; +}; + +#endif /* PLAT_S5P_CSIS_H_ */ -- cgit v1.2.3