From e9bc0765cc1274b7221360f462a3a993b41cac92 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 29 Jul 2019 15:26:20 +0200 Subject: arm64: dts: meson-g12a: enable DVFS on G12A boards Enable DVFS for the U200, SEI520 and X96-Max Amlogic G12A based board by setting the clock, OPP and supply for each CPU cores. The CPU cluster power supply can achieve 0.73V to 1.01V using a PWM output clocked at 800KHz with an inverse duty-cycle. DVFS has been tested by running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Reviewed-by: Martin Blumenstingl Signed-off-by: Neil Armstrong Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 54 +++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts') diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index 8551fbd4a488..2a324f0136e3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -129,6 +129,24 @@ regulator-always-on; }; + vddcpu: regulator-vddcpu { + /* + * MP8756GD Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&main_12v>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; }; &cec_AO { @@ -145,6 +163,34 @@ hdmi-phandle = <&hdmi_tx>; }; +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + &cvbs_vdac_port { cvbs_vdac_out: endpoint { remote-endpoint = <&cvbs_connector_in>; @@ -197,6 +243,14 @@ pinctrl-names = "default"; }; +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + /* SD card */ &sd_emmc_b { status = "okay"; -- cgit v1.2.3