From e45dda53d38b8e0956be6b8db239611514c7d8dc Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 29 Nov 2017 12:26:35 +0100 Subject: arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC This patch adds support for MSCL power domain to Exynos 5433 SoCs, which contains following devices: a clock controller, JPEG codec device and its SYSMMU. Signed-off-by: Marek Szyprowski Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64/boot/dts/exynos') diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 95f30ccc00a3..0a06be283a31 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -476,6 +476,7 @@ clocks = <&xxti>, <&cmu_top CLK_SCLK_JPEG_MSCL>, <&cmu_top CLK_ACLK_MSCL_400>; + power-domains = <&pd_mscl>; }; cmu_mfc: clock-controller@15280000 { @@ -552,6 +553,13 @@ label = "GSCL"; }; + pd_mscl: power-domain@105c4040 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c4040 0x20>; + #power-domain-cells = <0>; + label = "MSCL"; + }; + pd_disp: power-domain@105c4080 { compatible = "samsung,exynos5433-pd"; reg = <0x105c4080 0x20>; @@ -971,6 +979,7 @@ <&cmu_mscl CLK_ACLK_XIU_MSCLX>, <&cmu_mscl CLK_SCLK_JPEG>; iommus = <&sysmmu_jpeg>; + power-domains = <&pd_mscl>; }; mfc: codec@152E0000 { @@ -1070,6 +1079,7 @@ clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>, <&cmu_mscl CLK_ACLK_SMMU_JPEG>; #iommu-cells = <0>; + power-domains = <&pd_mscl>; }; sysmmu_mfc_0: sysmmu@15200000 { -- cgit v1.2.3