From 64a7eb034c1cca19f537103d9ad091acd6c75b41 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Tue, 20 Jun 2017 17:39:22 +0800 Subject: MLK-15110-11 arm64: dtsi: fsl-imx8qxp: Add DPR0/1 irq resources for DPU The Display Prefetch Resolve(DPR) engine is the prefetch engine of DPU. This patch adds the DPR0/1's irq resources for DPU. Signed-off-by: Liu Ying --- arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi') diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index f98e035fc3e2..1f7a6cc6491d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -967,7 +967,9 @@ , , , - ; + , + , + ; interrupt-names = "irq_common", "irq_stream0a", "irq_stream0b", /* to M4? */ @@ -975,7 +977,9 @@ "irq_stream1b", /* to M4? */ "irq_reserved0", "irq_reserved1", - "irq_blit"; + "irq_blit", + "irq_dpr0", + "irq_dpr1"; clocks = <&clk IMX8QXP_DC0_PLL0_CLK>, <&clk IMX8QXP_DC0_PLL1_CLK>, <&clk IMX8QXP_DC0_DISP0_CLK>, -- cgit v1.2.3