From 7a9ffad308a8ec4fc23ea268fdbeff6fbd30b79c Mon Sep 17 00:00:00 2001 From: Huang Chaofan Date: Wed, 6 Jun 2018 14:02:43 +0800 Subject: MLK-17305 [MX8QXP-MEK] VPU: "couldn't set vpu_dec_clk clk rate to 600000000 (-22)" and "clk: couldn't set vpu_enc_clk clk rate to 600000000 (-22), current rate: 0" when boot up. 100% vpu clock is not settable, remove the assigned-clock-rates from the dts Signed-off-by: Huang Chaofan --- arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi') diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index a3cb4d60c515..43c0a41a6d78 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -3113,7 +3113,6 @@ clocks = <&clk IMX8QXP_VPU_DEC_CLK>; clock-names = "vpu_clk"; assigned-clocks = <&clk IMX8QXP_VPU_DEC_CLK>; - assigned-clock-rates = <600000000>; power-domains = <&pd_vpu_dec>; status = "disabled"; }; @@ -3127,7 +3126,6 @@ clocks = <&clk IMX8QXP_VPU_ENC_CLK>; clock-names = "vpu_encoder_clk"; assigned-clocks = <&clk IMX8QXP_VPU_ENC_CLK>; - assigned-clock-rates = <600000000>; power-domains = <&pd_vpu_enc>; status = "disabled"; }; -- cgit v1.2.3