From 534cfce193bbaff52612007c9d1c387508a75496 Mon Sep 17 00:00:00 2001 From: Florinel Iordache Date: Mon, 5 Nov 2018 17:02:19 +0200 Subject: arm64: dts: lx2160: PCS PHY definitions for 10GBase-KR and 40GBase-KR backplane modes Signed-off-by: Florinel Iordache --- arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts') diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts index 7eb616938499..fed55d5c6c37 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts @@ -162,3 +162,43 @@ &usb1 { status = "okay"; }; + +&pcs_mdio1 { + pcs_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + backplane-mode = "40gbase-kr"; + reg = <0x0>; + fsl,lane-handle = <&serdes1>; + fsl,lane-reg = <0xF00 0xE00 0xD00 0xC00>; /* lanes H, G, F, E */ + }; +}; + +&pcs_mdio2 { + pcs_phy2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + backplane-mode = "40gbase-kr"; + reg = <0x0>; + fsl,lane-handle = <&serdes1>; + fsl,lane-reg = <0xB00 0xA00 0x900 0x800>; /* lanes D, C, B, A */ + }; +}; + +&pcs_mdio3 { + pcs_phy3: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + backplane-mode = "10gbase-kr"; + reg = <0x0>; + fsl,lane-handle = <&serdes1>; + fsl,lane-reg = <0xF00 0x100>; /* lane H */ + }; +}; + +&pcs_mdio4 { + pcs_phy4: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + backplane-mode = "10gbase-kr"; + reg = <0x0>; + fsl,lane-handle = <&serdes1>; + fsl,lane-reg = <0xE00 0x100>; /* lane G */ + }; +}; -- cgit v1.2.3